From: kan.liang@linux.intel.com
To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org,
tglx@linutronix.de, bp@alien8.de, x86@kernel.org,
linux-kernel@vger.kernel.org
Cc: mark.rutland@arm.com, alexander.shishkin@linux.intel.com,
jolsa@redhat.com, namhyung@kernel.org, dave.hansen@intel.com,
yu-cheng.yu@intel.com, bigeasy@linutronix.de, gorcunov@gmail.com,
hpa@zytor.com, alexey.budankov@linux.intel.com,
eranian@google.com, ak@linux.intel.com, like.xu@linux.intel.com,
yao.jin@linux.intel.com, wei.w.wang@intel.com,
Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH V2 07/23] x86/msr-index: Add bunch of MSRs for Arch LBR
Date: Fri, 26 Jun 2020 11:20:04 -0700 [thread overview]
Message-ID: <1593195620-116988-8-git-send-email-kan.liang@linux.intel.com> (raw)
In-Reply-To: <1593195620-116988-1-git-send-email-kan.liang@linux.intel.com>
From: Kan Liang <kan.liang@linux.intel.com>
Add Arch LBR related MSRs and the new LBR INFO bits in MSR-index.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/include/asm/msr-index.h | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index e8370e6..bdc07fc 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -158,7 +158,23 @@
#define LBR_INFO_MISPRED BIT_ULL(63)
#define LBR_INFO_IN_TX BIT_ULL(62)
#define LBR_INFO_ABORT BIT_ULL(61)
+#define LBR_INFO_CYC_CNT_VALID BIT_ULL(60)
#define LBR_INFO_CYCLES 0xffff
+#define LBR_INFO_BR_TYPE_OFFSET 56
+#define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET)
+
+#define MSR_ARCH_LBR_CTL 0x000014ce
+#define ARCH_LBR_CTL_LBREN BIT(0)
+#define ARCH_LBR_CTL_CPL_OFFSET 1
+#define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET)
+#define ARCH_LBR_CTL_STACK_OFFSET 3
+#define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET)
+#define ARCH_LBR_CTL_FILTER_OFFSET 16
+#define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET)
+#define MSR_ARCH_LBR_DEPTH 0x000014cf
+#define MSR_ARCH_LBR_FROM_0 0x00001500
+#define MSR_ARCH_LBR_TO_0 0x00001600
+#define MSR_ARCH_LBR_INFO_0 0x00001200
#define MSR_IA32_PEBS_ENABLE 0x000003f1
#define MSR_PEBS_DATA_CFG 0x000003f2
--
2.7.4
next prev parent reply other threads:[~2020-06-26 18:24 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-26 18:19 [PATCH V2 00/23] Support Architectural LBR kan.liang
2020-06-26 18:19 ` [PATCH V2 01/23] x86/cpufeatures: Add Architectural LBRs feature bit kan.liang
2020-06-29 18:35 ` Liang, Kan
2020-06-26 18:19 ` [PATCH V2 02/23] perf/x86/intel/lbr: Add a function pointer for LBR reset kan.liang
2020-06-26 18:20 ` [PATCH V2 03/23] perf/x86/intel/lbr: Add a function pointer for LBR read kan.liang
2020-06-26 18:20 ` [PATCH V2 04/23] perf/x86/intel/lbr: Add the function pointers for LBR save and restore kan.liang
2020-06-26 18:20 ` [PATCH V2 05/23] perf/x86/intel/lbr: Factor out a new struct for generic optimization kan.liang
2020-06-26 18:20 ` [PATCH V2 06/23] perf/x86/intel/lbr: Use dynamic data structure for task_ctx kan.liang
2020-06-26 18:20 ` kan.liang [this message]
2020-06-26 18:20 ` [PATCH V2 08/23] perf/x86: Expose CPUID enumeration bits for arch LBR kan.liang
2020-06-30 15:01 ` Peter Zijlstra
2020-06-30 15:36 ` Liang, Kan
2020-06-30 16:39 ` Peter Zijlstra
2020-06-26 18:20 ` [PATCH V2 09/23] perf/x86/intel: Check Arch LBR MSRs kan.liang
2020-06-30 14:57 ` Peter Zijlstra
2020-06-30 15:29 ` Liang, Kan
2020-06-26 18:20 ` [PATCH V2 10/23] perf/x86/intel/lbr: Support LBR_CTL kan.liang
2020-06-26 18:20 ` [PATCH V2 11/23] perf/x86/intel/lbr: Unify the stored format of LBR information kan.liang
2020-06-26 18:20 ` [PATCH V2 12/23] perf/x86/intel/lbr: Factor out rdlbr_all() and wrlbr_all() kan.liang
2020-06-26 18:20 ` [PATCH V2 13/23] perf/x86/intel/lbr: Factor out intel_pmu_store_lbr kan.liang
2020-06-30 15:43 ` Peter Zijlstra
2020-06-26 18:20 ` [PATCH V2 14/23] perf/x86/intel/lbr: Support Architectural LBR kan.liang
2020-06-30 15:49 ` Peter Zijlstra
2020-06-30 16:17 ` Liang, Kan
2020-06-30 16:42 ` Peter Zijlstra
2020-06-26 18:20 ` [PATCH V2 15/23] perf/core: Factor out functions to allocate/free the task_ctx_data kan.liang
2020-06-26 18:20 ` [PATCH V2 16/23] perf/core: Use kmem_cache to allocate the PMU specific data kan.liang
2020-06-26 18:20 ` [PATCH V2 17/23] perf/x86/intel/lbr: Create kmem_cache for the LBR context data kan.liang
2020-06-26 18:20 ` [PATCH V2 18/23] perf/x86: Remove task_ctx_size kan.liang
2020-06-26 18:20 ` [PATCH V2 19/23] x86/fpu: Use proper mask to replace full instruction mask kan.liang
2020-06-26 18:20 ` [PATCH V2 20/23] x86/fpu/xstate: Support dynamic supervisor feature for LBR kan.liang
2020-06-26 18:20 ` [PATCH V2 21/23] x86/fpu/xstate: Add helpers for LBR dynamic supervisor feature kan.liang
2020-06-26 18:20 ` [PATCH V2 22/23] perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switch kan.liang
2020-06-26 18:20 ` [PATCH V2 23/23] perf/x86/intel/lbr: Support XSAVES for arch LBR read kan.liang
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