From: kan.liang@linux.intel.com
To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org,
tglx@linutronix.de, bp@alien8.de, x86@kernel.org,
linux-kernel@vger.kernel.org
Cc: mark.rutland@arm.com, alexander.shishkin@linux.intel.com,
jolsa@redhat.com, namhyung@kernel.org, dave.hansen@intel.com,
yu-cheng.yu@intel.com, bigeasy@linutronix.de, gorcunov@gmail.com,
hpa@zytor.com, alexey.budankov@linux.intel.com,
eranian@google.com, ak@linux.intel.com, like.xu@linux.intel.com,
yao.jin@linux.intel.com, wei.w.wang@intel.com,
Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH V2 08/23] perf/x86: Expose CPUID enumeration bits for arch LBR
Date: Fri, 26 Jun 2020 11:20:05 -0700 [thread overview]
Message-ID: <1593195620-116988-9-git-send-email-kan.liang@linux.intel.com> (raw)
In-Reply-To: <1593195620-116988-1-git-send-email-kan.liang@linux.intel.com>
From: Kan Liang <kan.liang@linux.intel.com>
The LBR capabilities of Architecture LBR are retrieved from the CPUID
enumeration once at boot time. The capabilities have to be saved for
future usage.
Several new fields are added into structure x86_pmu to indicate the
capabilities. The fields will be used in the following patches.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/perf_event.h | 5 +++++
arch/x86/include/asm/perf_event.h | 40 +++++++++++++++++++++++++++++++++++++++
2 files changed, 45 insertions(+)
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index d04818b..9b0e533 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -690,6 +690,11 @@ struct x86_pmu {
const int *lbr_sel_map; /* lbr_select mappings */
bool lbr_double_abort; /* duplicated lbr aborts */
bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
+ bool arch_lbr; /* Arch LBR supported */
+
+ union cpuid28_eax lbr_eax;
+ union cpuid28_ebx lbr_ebx;
+ union cpuid28_ecx lbr_ecx;
void (*lbr_reset)(void);
void (*lbr_read)(struct cpu_hw_events *cpuc);
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index e855e9c..d33cc82 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -142,6 +142,46 @@ union cpuid10_edx {
unsigned int full;
};
+/*
+ * Intel Architectural LBR CPUID detection/enumeration details:
+ */
+union cpuid28_eax {
+ struct {
+ /* Supported LBR depth values */
+ unsigned int lbr_depth_mask:8;
+ unsigned int reserved:22;
+ /* Deep C-state Reset */
+ unsigned int lbr_deep_c_reset:1;
+ /* IP values contain LIP */
+ unsigned int lbr_lip:1;
+ } split;
+ unsigned int full;
+};
+
+union cpuid28_ebx {
+ struct {
+ /* CPL Filtering Supported */
+ unsigned int lbr_cpl:1;
+ /* Branch Filtering Supported */
+ unsigned int lbr_filter:1;
+ /* Call-stack Mode Supported */
+ unsigned int lbr_call_stack:1;
+ } split;
+ unsigned int full;
+};
+
+union cpuid28_ecx {
+ struct {
+ /* Mispredict Bit Supported */
+ unsigned int lbr_mispred:1;
+ /* Timed LBRs Supported */
+ unsigned int lbr_timed_lbr:1;
+ /* Branch Type Field Supported */
+ unsigned int lbr_br_type:1;
+ } split;
+ unsigned int full;
+};
+
struct x86_pmu_capability {
int version;
int num_counters_gp;
--
2.7.4
next prev parent reply other threads:[~2020-06-26 18:24 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-26 18:19 [PATCH V2 00/23] Support Architectural LBR kan.liang
2020-06-26 18:19 ` [PATCH V2 01/23] x86/cpufeatures: Add Architectural LBRs feature bit kan.liang
2020-06-29 18:35 ` Liang, Kan
2020-06-26 18:19 ` [PATCH V2 02/23] perf/x86/intel/lbr: Add a function pointer for LBR reset kan.liang
2020-06-26 18:20 ` [PATCH V2 03/23] perf/x86/intel/lbr: Add a function pointer for LBR read kan.liang
2020-06-26 18:20 ` [PATCH V2 04/23] perf/x86/intel/lbr: Add the function pointers for LBR save and restore kan.liang
2020-06-26 18:20 ` [PATCH V2 05/23] perf/x86/intel/lbr: Factor out a new struct for generic optimization kan.liang
2020-06-26 18:20 ` [PATCH V2 06/23] perf/x86/intel/lbr: Use dynamic data structure for task_ctx kan.liang
2020-06-26 18:20 ` [PATCH V2 07/23] x86/msr-index: Add bunch of MSRs for Arch LBR kan.liang
2020-06-26 18:20 ` kan.liang [this message]
2020-06-30 15:01 ` [PATCH V2 08/23] perf/x86: Expose CPUID enumeration bits for arch LBR Peter Zijlstra
2020-06-30 15:36 ` Liang, Kan
2020-06-30 16:39 ` Peter Zijlstra
2020-06-26 18:20 ` [PATCH V2 09/23] perf/x86/intel: Check Arch LBR MSRs kan.liang
2020-06-30 14:57 ` Peter Zijlstra
2020-06-30 15:29 ` Liang, Kan
2020-06-26 18:20 ` [PATCH V2 10/23] perf/x86/intel/lbr: Support LBR_CTL kan.liang
2020-06-26 18:20 ` [PATCH V2 11/23] perf/x86/intel/lbr: Unify the stored format of LBR information kan.liang
2020-06-26 18:20 ` [PATCH V2 12/23] perf/x86/intel/lbr: Factor out rdlbr_all() and wrlbr_all() kan.liang
2020-06-26 18:20 ` [PATCH V2 13/23] perf/x86/intel/lbr: Factor out intel_pmu_store_lbr kan.liang
2020-06-30 15:43 ` Peter Zijlstra
2020-06-26 18:20 ` [PATCH V2 14/23] perf/x86/intel/lbr: Support Architectural LBR kan.liang
2020-06-30 15:49 ` Peter Zijlstra
2020-06-30 16:17 ` Liang, Kan
2020-06-30 16:42 ` Peter Zijlstra
2020-06-26 18:20 ` [PATCH V2 15/23] perf/core: Factor out functions to allocate/free the task_ctx_data kan.liang
2020-06-26 18:20 ` [PATCH V2 16/23] perf/core: Use kmem_cache to allocate the PMU specific data kan.liang
2020-06-26 18:20 ` [PATCH V2 17/23] perf/x86/intel/lbr: Create kmem_cache for the LBR context data kan.liang
2020-06-26 18:20 ` [PATCH V2 18/23] perf/x86: Remove task_ctx_size kan.liang
2020-06-26 18:20 ` [PATCH V2 19/23] x86/fpu: Use proper mask to replace full instruction mask kan.liang
2020-06-26 18:20 ` [PATCH V2 20/23] x86/fpu/xstate: Support dynamic supervisor feature for LBR kan.liang
2020-06-26 18:20 ` [PATCH V2 21/23] x86/fpu/xstate: Add helpers for LBR dynamic supervisor feature kan.liang
2020-06-26 18:20 ` [PATCH V2 22/23] perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switch kan.liang
2020-06-26 18:20 ` [PATCH V2 23/23] perf/x86/intel/lbr: Support XSAVES for arch LBR read kan.liang
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