[GIT PULL] RISC-V updates for v6.19-rc7

[GIT PULL] RISC-V updates for v6.19-rc7

[Paul Walmsley]

Linus,

Please pull these RISC-V fixes for v6.19-rc7.  

The notable changes here are the three RISC-V timer compare register 
update sequence patches.  These only apply to RV32 systems and are related 
to the 64-bit timer compare value being split across two separate 32-bit 
registers.  We weren't using the appropriate three-write sequence, 
documented in the RISC-V ISA specifications, to avoid spurious timer 
interrupts during the update sequence; so, these patches now use the 
recommended sequence.  This doesn't affect 64-bit RISC-V systems, since 
the timer compare value fits inside a single register and can be updated 
with a single write.

thanks,

- Paul


The following changes since commit 0f61b1860cc3f52aef9036d7235ed1f017632193:

  Linux 6.19-rc5 (2026-01-11 17:03:14 -1000)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux tags/riscv-for-linus-6.19-rc7

for you to fetch changes up to 841e47d56cef9b96fd2314220e3d0f1d92c719f4:

  riscv: Add intermediate cast to 'unsigned long' in __get_user_asm (2026-01-22 20:21:14 -0700)

----------------------------------------------------------------
RISC-V updates for v6.19-rc7

- Fix the RISC-V timer compare register update sequence on RV32
  systems to use the recommended sequence in the RISC-V ISA manual.
  This avoids spurious interrupts during updates

- Add a dependence on the new CONFIG_CACHEMAINT_FOR_DMA Kconfig symbol
  for Renesas and StarFive RISC-V SoCs

- Add a temporary workaround for a Clang compiler bug caused by using
  asm_goto_output for get_user()

- Clarify our documentation around to specifically state a particular
  ISA specification version for a chapter number reference

----------------------------------------------------------------
Guodong Xu (1):
      Documentation: riscv: uabi: Clarify ISA spec version for canonical order

Jonathan Cameron (2):
      riscv: ERRATA_STARFIVE_JH7100: Fix missing dependency on new CONFIG_CACHEMAINT_FOR_DMA
      soc: renesas: Fix missing dependency on new CONFIG_CACHEMAINT_FOR_DMA

Naohiko Shimizu (3):
      riscv: clocksource: Fix stimecmp update hazard on RV32
      riscv: kvm: Fix vstimecmp update hazard on RV32
      riscv: suspend: Fix stimecmp update hazard on RV32

Nathan Chancellor (2):
      riscv: Use 64-bit variable for output in __get_user_asm
      riscv: Add intermediate cast to 'unsigned long' in __get_user_asm

 Documentation/arch/riscv/uabi.rst |  4 +++-
 arch/riscv/Kconfig.errata         |  1 +
 arch/riscv/include/asm/uaccess.h  | 14 ++++++++++++--
 arch/riscv/kernel/suspend.c       |  3 ++-
 arch/riscv/kvm/vcpu_timer.c       |  6 ++++--
 drivers/clocksource/timer-riscv.c |  3 ++-
 drivers/soc/renesas/Kconfig       |  1 +
 7 files changed, 25 insertions(+), 7 deletions(-)

Re: [GIT PULL] RISC-V updates for v6.19-rc7

[pr-tracker-bot]

The pull request you sent on Sat, 24 Jan 2026 16:21:29 -0700 (MST):

> git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux tags/riscv-for-linus-6.19-rc7

has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/d91a46d6805af41e7f2286e0fc22d498f45a682b

Thank you!

-- 
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Re: [GIT PULL] RISC-V updates for v6.19-rc7

[patchwork-bot+linux-riscv]

Hello:

This pull request was applied to riscv/linux.git (fixes)
by Linus Torvalds <torvalds@linux-foundation.org>:

On Sat, 24 Jan 2026 16:21:29 -0700 (MST) you wrote:
> Linus,
> 
> Please pull these RISC-V fixes for v6.19-rc7.
> 
> The notable changes here are the three RISC-V timer compare register
> update sequence patches.  These only apply to RV32 systems and are related
> to the 64-bit timer compare value being split across two separate 32-bit
> registers.  We weren't using the appropriate three-write sequence,
> documented in the RISC-V ISA specifications, to avoid spurious timer
> interrupts during the update sequence; so, these patches now use the
> recommended sequence.  This doesn't affect 64-bit RISC-V systems, since
> the timer compare value fits inside a single register and can be updated
> with a single write.
> 
> [...]

Here is the summary with links:
  - [GIT,PULL] RISC-V updates for v6.19-rc7
    https://git.kernel.org/riscv/c/d91a46d6805a

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html

Re: [GIT PULL] RISC-V updates for v6.19-rc7

[patchwork-bot+linux-riscv]

Hello:

This pull request was applied to riscv/linux.git (for-next)
by Linus Torvalds <torvalds@linux-foundation.org>:

On Sat, 24 Jan 2026 16:21:29 -0700 (MST) you wrote:
> Linus,
> 
> Please pull these RISC-V fixes for v6.19-rc7.
> 
> The notable changes here are the three RISC-V timer compare register
> update sequence patches.  These only apply to RV32 systems and are related
> to the 64-bit timer compare value being split across two separate 32-bit
> registers.  We weren't using the appropriate three-write sequence,
> documented in the RISC-V ISA specifications, to avoid spurious timer
> interrupts during the update sequence; so, these patches now use the
> recommended sequence.  This doesn't affect 64-bit RISC-V systems, since
> the timer compare value fits inside a single register and can be updated
> with a single write.
> 
> [...]

Here is the summary with links:
  - [GIT,PULL] RISC-V updates for v6.19-rc7
    https://git.kernel.org/riscv/c/d91a46d6805a

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html