From: Xin Li <xin@zytor.com>
To: Sean Christopherson <seanjc@google.com>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com,
pbonzini@redhat.com, peterz@infradead.org, sohil.mehta@intel.com,
brgerst@gmail.com, tony.luck@intel.com, fenghuay@nvidia.com
Subject: Re: [PATCH v2 2/2] x86/traps: Initialize DR7 by writing its architectural reset value
Date: Tue, 17 Jun 2025 17:15:18 -0700 [thread overview]
Message-ID: <1b8095a8-1e65-4508-b874-fa2fce1b00ee@zytor.com> (raw)
In-Reply-To: <9720c605-c542-4969-b7f0-b4477bc2ab1e@zytor.com>
On 6/17/2025 4:08 PM, Xin Li wrote:
>
> I hope the bit will be kept reserved to 1 *forever*, because inverted
> polarity seems causing confusing and complicated code only.
BTW, FRED flipped BLD and RTM polarities in its event data:
The event data is not exactly the same as that which will be in DR6
following delivery of the #DB. The polarity of bit 11 (BLD) and bit 16
(RTM) is inverted in DR6.
I.e., BLD and RTM are active high in FRED event data.
next prev parent reply other threads:[~2025-06-18 0:15 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-17 7:32 [PATCH v2 0/2] x86/traps: Fix DR6/DR7 initialization Xin Li (Intel)
2025-06-17 7:32 ` [PATCH v2 1/2] x86/traps: Initialize DR6 by writing its architectural reset value Xin Li (Intel)
2025-06-17 9:03 ` Peter Zijlstra
2025-06-17 22:49 ` Xin Li
2025-06-17 18:23 ` Sohil Mehta
2025-06-17 20:47 ` Sean Christopherson
2025-06-17 23:10 ` Sohil Mehta
2025-06-18 0:42 ` Xin Li
2025-06-17 23:57 ` Xin Li
2025-06-18 21:24 ` Sean Christopherson
2025-06-18 21:55 ` Xin Li
2025-06-19 5:16 ` Maciej W. Rozycki
2025-06-17 7:32 ` [PATCH v2 2/2] x86/traps: Initialize DR7 " Xin Li (Intel)
2025-06-17 13:35 ` Sean Christopherson
2025-06-17 23:08 ` Xin Li
2025-06-18 0:15 ` Xin Li [this message]
2025-06-18 3:34 ` H. Peter Anvin
2025-06-17 23:10 ` Sohil Mehta
2025-06-18 0:44 ` Xin Li
2025-06-17 9:05 ` [PATCH v2 0/2] x86/traps: Fix DR6/DR7 initialization Peter Zijlstra
2025-06-17 17:55 ` Sohil Mehta
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