From: Srirangan Madhavan <smadhavan@nvidia.com>
To: "Cheatham, Benjamin" <benjamin.cheatham@amd.com>,
Alison Schofield <alison.schofield@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <jic23@kernel.org>,
Vishal Verma <vishal.l.verma@intel.com>,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Alex Williamson <alex.williamson@redhat.com>,
vsethi@nvidia.com, alwilliamson@nvidia.com,
Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
Vishal Aslot <vaslot@nvidia.com>,
Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
Richard Cheng <icheng@nvidia.com>,
linux-tegra@vger.kernel.org
Subject: Re: [PATCH v13 10/15] cxl: Add CXL Device Reset sequencing
Date: Thu, 1 Oct 2026 16:36:48 -0700 [thread overview]
Message-ID: <1c623643-6e28-4d25-8249-d005d2813b6f@nvidia.com> (raw)
In-Reply-To: <cd752641-4563-40d0-a53c-b7a85d396097@amd.com>
On 9/23/26 2:40 PM, Cheatham, Benjamin wrote:
> External email: Use caution opening links or attachments
>> +
>> + for (;;) {
>> + rc = pci_read_config_word(pdev, dvsec + PCI_DVSEC_CXL_STATUS2,
>> + &status2);
>> + if (rc || status2 == U16_MAX)
>> + goto not_ready;
>> + if (status2 & PCI_DVSEC_CXL_RST_ERR)
>> + return -EIO;
>> + if (status2 & PCI_DVSEC_CXL_RST_DONE)
>> + return 0;
>> +
>> +not_ready:
>> + if (time_after_eq(jiffies, deadline))
>> + return -ETIMEDOUT;
>> +
>> + msleep(CXL_RESET_STATUS_POLL_MS);
>
> The goto here isn't necessary, I think this is functionally equivalent:
>
> if ((rc || status2 == U16_MAX) && time_after_eq(jiffies, deadline))
> return -ETIMEDOUT;
> else if (status2 & PCI_DVSEC_CXL_RST_ERR)
> return -EIO;
> else if (status2 & PCI_DVSEC_CXL_RST_DONE)
> return 0;
>
> msleep(CXL_RESET_STATUS_POLL_MS);
>
> Sashiko also brought it up, but the timeout is probably too long. I'd pick something like 20s
> instead. That's probably still too conservative, but I don't know enough to suggest a more practical
> value.
V14 removes the goto, caps the timeout at 20 seconds, and allows one
poll after the 100 ms quiet period. A config read error now returns
immediately.
>> + /*
>> + * DISABLE_CACHING was the first preparation step. Restore the original
>> + * cache policy last, after reset exclusion has ended.
>> + */
>> + rc2 = cxl_reset_update_ctrl2_no_replay(
>> + pdev, dvsec, 0, PCI_DVSEC_CXL_DISABLE_CACHING);
>> + if (rc2)
>> + pci_err(pdev, "failed to re-enable CXL caching: %d\n", rc2);
>> + rc = rc ?: rc2;
>> +
>> + return rc;
>> +}
>
> This is pretty messy, I think it would be cleaner if you split this into several functions:
>
> static int __cxl_reset_execute(...)
> {
> int rc;
>
> rc = cxl_reset_disable_cache(...);
> if (rc)
> return rc;
>
> rc = cxl_clear_memory(...); // could be open coded, made a function for brevity
> if (!rc)
> rc = cxl_reset_wait_done(...);
>
> rc = rc ?: cxl_clear_memory(...); // This one doesn't have the INIT_CXL_RST flag
>
> pci_dev_reset_iommu_done(pdev);
>
> return rc;
> }
>
> static int cxl_reset_execute(...)
> {
> int rc;
>
> rc = __cxl_reset_execute(..);
> if (rc)
> // log error
>
> return rc ?: cxl_enable_cache(...);
> }
>
> Hopefully what goes where makes sense just based on the names. I'm also not convinced you
> need to preserve the original error code throughout the function since it's essentially
> the same error conditions for all these functions AFAICT.
>
Done in v14. I split the reset execution and Memory Clear handling into
smaller helpers, following your suggested structure.
--
Regards,
Srirangan
next prev parent reply other threads:[~2026-10-01 23:36 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-22 8:39 [PATCH v13 00/15] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-09-22 8:39 ` [PATCH v13 01/15] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-09-24 1:16 ` Jonathan Cameron
2026-09-24 16:23 ` Dave Jiang
2026-09-22 8:39 ` [PATCH v13 02/15] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-09-23 21:39 ` Cheatham, Benjamin
2026-09-24 1:21 ` Jonathan Cameron
2026-09-24 16:55 ` Dave Jiang
2026-10-01 22:33 ` Srirangan Madhavan
2026-09-24 1:22 ` Jonathan Cameron
2026-10-01 22:28 ` Srirangan Madhavan
2026-09-24 17:01 ` Dave Jiang
2026-09-22 8:39 ` [PATCH v13 03/15] cxl: Move HDM decoder programming helpers Srirangan Madhavan
2026-09-24 1:29 ` Jonathan Cameron
2026-10-01 23:40 ` Srirangan Madhavan
2026-09-24 17:02 ` Dave Jiang
2026-09-22 8:39 ` [PATCH v13 04/15] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-09-24 1:31 ` Jonathan Cameron
2026-09-24 17:03 ` Dave Jiang
2026-09-22 8:39 ` [PATCH v13 05/15] cxl: Introduce reusable HDM decoder settings Srirangan Madhavan
2026-09-23 21:39 ` Cheatham, Benjamin
2026-09-24 1:35 ` Jonathan Cameron
2026-10-01 22:43 ` Srirangan Madhavan
2026-09-24 2:45 ` Jonathan Cameron
2026-10-01 23:42 ` Srirangan Madhavan
2026-09-22 8:39 ` [PATCH v13 06/15] cxl: Make HDM reset helpers available to built-in PCI code Srirangan Madhavan
2026-09-23 21:40 ` Cheatham, Benjamin
2026-09-24 2:49 ` Jonathan Cameron
2026-10-01 22:46 ` Srirangan Madhavan
2026-09-22 8:39 ` [PATCH v13 07/15] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-09-24 3:05 ` Jonathan Cameron
2026-10-01 23:52 ` Srirangan Madhavan
2026-09-22 8:39 ` [PATCH v13 08/15] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-09-23 21:40 ` Cheatham, Benjamin
2026-10-01 22:58 ` Srirangan Madhavan
2026-09-24 3:08 ` Jonathan Cameron
2026-09-22 8:39 ` [PATCH v13 09/15] cxl: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-09-23 21:40 ` Cheatham, Benjamin
2026-10-01 23:14 ` Srirangan Madhavan
2026-09-24 3:36 ` Jonathan Cameron
2026-10-01 23:55 ` Srirangan Madhavan
2026-09-22 8:39 ` [PATCH v13 10/15] cxl: Add CXL Device Reset sequencing Srirangan Madhavan
2026-09-23 21:40 ` Cheatham, Benjamin
2026-09-24 17:29 ` Dave Jiang
2026-10-01 23:36 ` Srirangan Madhavan [this message]
2026-09-22 8:39 ` [PATCH v13 11/15] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-09-23 21:40 ` Cheatham, Benjamin
2026-10-01 23:25 ` Srirangan Madhavan
2026-09-22 8:39 ` [PATCH v13 12/15] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-09-23 21:41 ` Cheatham, Benjamin
2026-09-24 17:33 ` Dave Jiang
2026-09-22 8:39 ` [PATCH v13 13/15] cxl: Restore CXL state after PCI reset Srirangan Madhavan
2026-09-24 3:50 ` Jonathan Cameron
2026-10-01 23:58 ` Srirangan Madhavan
2026-09-22 8:39 ` [PATCH v13 14/15] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-09-22 8:39 ` [PATCH v13 15/15] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
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