From: Srirangan Madhavan <smadhavan@nvidia.com>
To: Jonathan Cameron <jic23@kernel.org>
Cc: Alison Schofield <alison.schofield@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Ira Weiny <ira.weiny@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org,
Alex Williamson <alex.williamson@redhat.com>,
vsethi@nvidia.com, alwilliamson@nvidia.com,
Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
Vishal Aslot <vaslot@nvidia.com>,
Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
Richard Cheng <icheng@nvidia.com>,
linux-tegra@vger.kernel.org
Subject: Re: [PATCH v13 07/15] cxl: Share HDM decoder register unpacking
Date: Thu, 1 Oct 2026 16:52:58 -0700 [thread overview]
Message-ID: <e56fcdb4-85c5-4559-b2ef-bb1a3eaf14f2@nvidia.com> (raw)
In-Reply-To: <20260924040534.4eae3107@jic23-hlaptop>
On 9/23/26 8:05 PM, Jonathan Cameron wrote:
> External email: Use caution opening links or attachments
>> - };
>> + if (!cxled && cxld->interleave_ways > 8) {
>
> Why does this check make sense now when we didn't have it before
> (that I can find anyway)? If it isn't tightly coupled to this
> patch and instead is providing some extra checks that are worthwhile
> I'd break it out as a separate patch where that usecase can be
> well described.
>
I dropped the new > 8 check from v14 patch 7. It was not present in the
original code, and this patch is intended to only share the existing
unpacking behavior.
>> +
>> + if (!committed)
>> + size = 0;
>> + if (base == U64_MAX || size == U64_MAX ||
>> + (size && base > U64_MAX - (size - 1)))
>> + return -ENXIO;
>
> This second block looks like new defences which is fine but I'm not sure
> it makes sense in here. Also given we are just checking overflow
> doesn't happen maybe use check_add_overflow(). Saves us thinking too
> much the maths.
>
Agreed. V14 puts the overflow check in a separate patch, 8/16, and uses
check_add_overflow().
>> +
>> + hpa_range = (struct range) {
>> + .start = base,
>> + .end = base + size - 1,
>> + };
>> + target_type = FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl) ?
>> + CXL_DECODER_HOSTONLYMEM : CXL_DECODER_DEVMEM;
>
> Maybe stick to the if / else of the original? I think that is more readable for
> an extra couple of lines.
> Also blank line here to give visual separation before the conditional that
> follows.
Ack. V14 keeps the original if/else.
>
> It's a functional change to move the target_type selection out of the
> committed check. I'd like to see some discussion of why that is fine to
> do which probably means a separate little patch that has that description
> on its own.
Ack. V14 selects the target type only when the decoder is committed,
preserving the existing behavior.
--
Regards,
Srirangan
next prev parent reply other threads:[~2026-10-01 23:53 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-22 8:39 [PATCH v13 00/15] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-09-22 8:39 ` [PATCH v13 01/15] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-09-24 1:16 ` Jonathan Cameron
2026-09-24 16:23 ` Dave Jiang
2026-09-22 8:39 ` [PATCH v13 02/15] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-09-23 21:39 ` Cheatham, Benjamin
2026-09-24 1:21 ` Jonathan Cameron
2026-09-24 16:55 ` Dave Jiang
2026-10-01 22:33 ` Srirangan Madhavan
2026-09-24 1:22 ` Jonathan Cameron
2026-10-01 22:28 ` Srirangan Madhavan
2026-09-24 17:01 ` Dave Jiang
2026-09-22 8:39 ` [PATCH v13 03/15] cxl: Move HDM decoder programming helpers Srirangan Madhavan
2026-09-24 1:29 ` Jonathan Cameron
2026-10-01 23:40 ` Srirangan Madhavan
2026-09-24 17:02 ` Dave Jiang
2026-09-22 8:39 ` [PATCH v13 04/15] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-09-24 1:31 ` Jonathan Cameron
2026-09-24 17:03 ` Dave Jiang
2026-09-22 8:39 ` [PATCH v13 05/15] cxl: Introduce reusable HDM decoder settings Srirangan Madhavan
2026-09-23 21:39 ` Cheatham, Benjamin
2026-09-24 1:35 ` Jonathan Cameron
2026-10-01 22:43 ` Srirangan Madhavan
2026-09-24 2:45 ` Jonathan Cameron
2026-10-01 23:42 ` Srirangan Madhavan
2026-09-22 8:39 ` [PATCH v13 06/15] cxl: Make HDM reset helpers available to built-in PCI code Srirangan Madhavan
2026-09-23 21:40 ` Cheatham, Benjamin
2026-09-24 2:49 ` Jonathan Cameron
2026-10-01 22:46 ` Srirangan Madhavan
2026-09-22 8:39 ` [PATCH v13 07/15] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-09-24 3:05 ` Jonathan Cameron
2026-10-01 23:52 ` Srirangan Madhavan [this message]
2026-09-22 8:39 ` [PATCH v13 08/15] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-09-23 21:40 ` Cheatham, Benjamin
2026-10-01 22:58 ` Srirangan Madhavan
2026-09-24 3:08 ` Jonathan Cameron
2026-09-22 8:39 ` [PATCH v13 09/15] cxl: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-09-23 21:40 ` Cheatham, Benjamin
2026-10-01 23:14 ` Srirangan Madhavan
2026-09-24 3:36 ` Jonathan Cameron
2026-10-01 23:55 ` Srirangan Madhavan
2026-09-22 8:39 ` [PATCH v13 10/15] cxl: Add CXL Device Reset sequencing Srirangan Madhavan
2026-09-23 21:40 ` Cheatham, Benjamin
2026-09-24 17:29 ` Dave Jiang
2026-10-01 23:36 ` Srirangan Madhavan
2026-09-22 8:39 ` [PATCH v13 11/15] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-09-23 21:40 ` Cheatham, Benjamin
2026-10-01 23:25 ` Srirangan Madhavan
2026-09-22 8:39 ` [PATCH v13 12/15] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-09-23 21:41 ` Cheatham, Benjamin
2026-09-24 17:33 ` Dave Jiang
2026-09-22 8:39 ` [PATCH v13 13/15] cxl: Restore CXL state after PCI reset Srirangan Madhavan
2026-09-24 3:50 ` Jonathan Cameron
2026-10-01 23:58 ` Srirangan Madhavan
2026-09-22 8:39 ` [PATCH v13 14/15] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-09-22 8:39 ` [PATCH v13 15/15] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
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