From: David Howells <dhowells@redhat.com>
To: linux-am33-list@redhat.com
Cc: linux-kernel@vger.kernel.org,
Akira Takeuchi <takeuchi.akr@jp.panasonic.com>,
Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Subject: [PATCH 11/43] MN10300: Move DMA engine control reg defs to MN103E010 processor directory
Date: Tue, 26 Oct 2010 03:54:00 +0100 [thread overview]
Message-ID: <20101026025400.23512.37567.stgit@warthog.procyon.org.uk> (raw)
In-Reply-To: <20101026025301.23512.24525.stgit@warthog.procyon.org.uk>
From: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Move the DMA engine control register definitions to the MN103E010 processor
directory so that the MN2WS0050 processor can have its own.
Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>
---
arch/mn10300/include/asm/dmactl-regs.h | 87 -----------------
.../proc-mn103e010/include/proc/dmactl-regs.h | 102 ++++++++++++++++++++
2 files changed, 103 insertions(+), 86 deletions(-)
create mode 100644 arch/mn10300/proc-mn103e010/include/proc/dmactl-regs.h
diff --git a/arch/mn10300/include/asm/dmactl-regs.h b/arch/mn10300/include/asm/dmactl-regs.h
index 58a199d..80337b3 100644
--- a/arch/mn10300/include/asm/dmactl-regs.h
+++ b/arch/mn10300/include/asm/dmactl-regs.h
@@ -11,91 +11,6 @@
#ifndef _ASM_DMACTL_REGS_H
#define _ASM_DMACTL_REGS_H
-#include <asm/cpu-regs.h>
-
-#ifdef __KERNEL__
-
-/* DMA registers */
-#define DMxCTR(N) __SYSREG(0xd2000000 + ((N) * 0x100), u32) /* control reg */
-#define DMxCTR_BG 0x0000001f /* transfer request source */
-#define DMxCTR_BG_SOFT 0x00000000 /* - software source */
-#define DMxCTR_BG_SC0TX 0x00000002 /* - serial port 0 transmission */
-#define DMxCTR_BG_SC0RX 0x00000003 /* - serial port 0 reception */
-#define DMxCTR_BG_SC1TX 0x00000004 /* - serial port 1 transmission */
-#define DMxCTR_BG_SC1RX 0x00000005 /* - serial port 1 reception */
-#define DMxCTR_BG_SC2TX 0x00000006 /* - serial port 2 transmission */
-#define DMxCTR_BG_SC2RX 0x00000007 /* - serial port 2 reception */
-#define DMxCTR_BG_TM0UFLOW 0x00000008 /* - timer 0 underflow */
-#define DMxCTR_BG_TM1UFLOW 0x00000009 /* - timer 1 underflow */
-#define DMxCTR_BG_TM2UFLOW 0x0000000a /* - timer 2 underflow */
-#define DMxCTR_BG_TM3UFLOW 0x0000000b /* - timer 3 underflow */
-#define DMxCTR_BG_TM6ACMPCAP 0x0000000c /* - timer 6A compare/capture */
-#define DMxCTR_BG_AFE 0x0000000d /* - analogue front-end interrupt source */
-#define DMxCTR_BG_ADC 0x0000000e /* - A/D conversion end interrupt source */
-#define DMxCTR_BG_IRDA 0x0000000f /* - IrDA interrupt source */
-#define DMxCTR_BG_RTC 0x00000010 /* - RTC interrupt source */
-#define DMxCTR_BG_XIRQ0 0x00000011 /* - XIRQ0 pin interrupt source */
-#define DMxCTR_BG_XIRQ1 0x00000012 /* - XIRQ1 pin interrupt source */
-#define DMxCTR_BG_XDMR0 0x00000013 /* - external request 0 source (XDMR0 pin) */
-#define DMxCTR_BG_XDMR1 0x00000014 /* - external request 1 source (XDMR1 pin) */
-#define DMxCTR_SAM 0x000000e0 /* DMA transfer src addr mode */
-#define DMxCTR_SAM_INCR 0x00000000 /* - increment */
-#define DMxCTR_SAM_DECR 0x00000020 /* - decrement */
-#define DMxCTR_SAM_FIXED 0x00000040 /* - fixed */
-#define DMxCTR_DAM 0x00000000 /* DMA transfer dest addr mode */
-#define DMxCTR_DAM_INCR 0x00000000 /* - increment */
-#define DMxCTR_DAM_DECR 0x00000100 /* - decrement */
-#define DMxCTR_DAM_FIXED 0x00000200 /* - fixed */
-#define DMxCTR_TM 0x00001800 /* DMA transfer mode */
-#define DMxCTR_TM_BATCH 0x00000000 /* - batch transfer */
-#define DMxCTR_TM_INTERM 0x00001000 /* - intermittent transfer */
-#define DMxCTR_UT 0x00006000 /* DMA transfer unit */
-#define DMxCTR_UT_1 0x00000000 /* - 1 byte */
-#define DMxCTR_UT_2 0x00002000 /* - 2 byte */
-#define DMxCTR_UT_4 0x00004000 /* - 4 byte */
-#define DMxCTR_UT_16 0x00006000 /* - 16 byte */
-#define DMxCTR_TEN 0x00010000 /* DMA channel transfer enable */
-#define DMxCTR_RQM 0x00060000 /* external request input source mode */
-#define DMxCTR_RQM_FALLEDGE 0x00000000 /* - falling edge */
-#define DMxCTR_RQM_RISEEDGE 0x00020000 /* - rising edge */
-#define DMxCTR_RQM_LOLEVEL 0x00040000 /* - low level */
-#define DMxCTR_RQM_HILEVEL 0x00060000 /* - high level */
-#define DMxCTR_RQF 0x01000000 /* DMA transfer request flag */
-#define DMxCTR_XEND 0x80000000 /* DMA transfer end flag */
-
-#define DMxSRC(N) __SYSREG(0xd2000004 + ((N) * 0x100), u32) /* control reg */
-
-#define DMxDST(N) __SYSREG(0xd2000008 + ((N) * 0x100), u32) /* src addr reg */
-
-#define DMxSIZ(N) __SYSREG(0xd200000c + ((N) * 0x100), u32) /* dest addr reg */
-#define DMxSIZ_CT 0x000fffff /* number of bytes to transfer */
-
-#define DMxCYC(N) __SYSREG(0xd2000010 + ((N) * 0x100), u32) /* intermittent
- * size reg */
-#define DMxCYC_CYC 0x000000ff /* number of interrmittent transfers -1 */
-
-#define DM0IRQ 16 /* DMA channel 0 complete IRQ */
-#define DM1IRQ 17 /* DMA channel 1 complete IRQ */
-#define DM2IRQ 18 /* DMA channel 2 complete IRQ */
-#define DM3IRQ 19 /* DMA channel 3 complete IRQ */
-
-#define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */
-#define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */
-#define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */
-#define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */
-
-#ifndef __ASSEMBLY__
-
-struct mn10300_dmactl_regs {
- u32 ctr;
- const void *src;
- void *dst;
- u32 siz;
- u32 cyc;
-} __attribute__((aligned(0x100)));
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
+#include <proc/dmactl-regs.h>
#endif /* _ASM_DMACTL_REGS_H */
diff --git a/arch/mn10300/proc-mn103e010/include/proc/dmactl-regs.h b/arch/mn10300/proc-mn103e010/include/proc/dmactl-regs.h
new file mode 100644
index 0000000..d72d328
--- /dev/null
+++ b/arch/mn10300/proc-mn103e010/include/proc/dmactl-regs.h
@@ -0,0 +1,102 @@
+/* MN103E010 on-board DMA controller registers
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_PROC_DMACTL_REGS_H
+#define _ASM_PROC_DMACTL_REGS_H
+
+#include <asm/cpu-regs.h>
+
+#ifdef __KERNEL__
+
+/* DMA registers */
+#define DMxCTR(N) __SYSREG(0xd2000000 + ((N) * 0x100), u32) /* control reg */
+#define DMxCTR_BG 0x0000001f /* transfer request source */
+#define DMxCTR_BG_SOFT 0x00000000 /* - software source */
+#define DMxCTR_BG_SC0TX 0x00000002 /* - serial port 0 transmission */
+#define DMxCTR_BG_SC0RX 0x00000003 /* - serial port 0 reception */
+#define DMxCTR_BG_SC1TX 0x00000004 /* - serial port 1 transmission */
+#define DMxCTR_BG_SC1RX 0x00000005 /* - serial port 1 reception */
+#define DMxCTR_BG_SC2TX 0x00000006 /* - serial port 2 transmission */
+#define DMxCTR_BG_SC2RX 0x00000007 /* - serial port 2 reception */
+#define DMxCTR_BG_TM0UFLOW 0x00000008 /* - timer 0 underflow */
+#define DMxCTR_BG_TM1UFLOW 0x00000009 /* - timer 1 underflow */
+#define DMxCTR_BG_TM2UFLOW 0x0000000a /* - timer 2 underflow */
+#define DMxCTR_BG_TM3UFLOW 0x0000000b /* - timer 3 underflow */
+#define DMxCTR_BG_TM6ACMPCAP 0x0000000c /* - timer 6A compare/capture */
+#define DMxCTR_BG_AFE 0x0000000d /* - analogue front-end interrupt source */
+#define DMxCTR_BG_ADC 0x0000000e /* - A/D conversion end interrupt source */
+#define DMxCTR_BG_IRDA 0x0000000f /* - IrDA interrupt source */
+#define DMxCTR_BG_RTC 0x00000010 /* - RTC interrupt source */
+#define DMxCTR_BG_XIRQ0 0x00000011 /* - XIRQ0 pin interrupt source */
+#define DMxCTR_BG_XIRQ1 0x00000012 /* - XIRQ1 pin interrupt source */
+#define DMxCTR_BG_XDMR0 0x00000013 /* - external request 0 source (XDMR0 pin) */
+#define DMxCTR_BG_XDMR1 0x00000014 /* - external request 1 source (XDMR1 pin) */
+#define DMxCTR_SAM 0x000000e0 /* DMA transfer src addr mode */
+#define DMxCTR_SAM_INCR 0x00000000 /* - increment */
+#define DMxCTR_SAM_DECR 0x00000020 /* - decrement */
+#define DMxCTR_SAM_FIXED 0x00000040 /* - fixed */
+#define DMxCTR_DAM 0x00000000 /* DMA transfer dest addr mode */
+#define DMxCTR_DAM_INCR 0x00000000 /* - increment */
+#define DMxCTR_DAM_DECR 0x00000100 /* - decrement */
+#define DMxCTR_DAM_FIXED 0x00000200 /* - fixed */
+#define DMxCTR_TM 0x00001800 /* DMA transfer mode */
+#define DMxCTR_TM_BATCH 0x00000000 /* - batch transfer */
+#define DMxCTR_TM_INTERM 0x00001000 /* - intermittent transfer */
+#define DMxCTR_UT 0x00006000 /* DMA transfer unit */
+#define DMxCTR_UT_1 0x00000000 /* - 1 byte */
+#define DMxCTR_UT_2 0x00002000 /* - 2 byte */
+#define DMxCTR_UT_4 0x00004000 /* - 4 byte */
+#define DMxCTR_UT_16 0x00006000 /* - 16 byte */
+#define DMxCTR_TEN 0x00010000 /* DMA channel transfer enable */
+#define DMxCTR_RQM 0x00060000 /* external request input source mode */
+#define DMxCTR_RQM_FALLEDGE 0x00000000 /* - falling edge */
+#define DMxCTR_RQM_RISEEDGE 0x00020000 /* - rising edge */
+#define DMxCTR_RQM_LOLEVEL 0x00040000 /* - low level */
+#define DMxCTR_RQM_HILEVEL 0x00060000 /* - high level */
+#define DMxCTR_RQF 0x01000000 /* DMA transfer request flag */
+#define DMxCTR_XEND 0x80000000 /* DMA transfer end flag */
+
+#define DMxSRC(N) __SYSREG(0xd2000004 + ((N) * 0x100), u32) /* control reg */
+
+#define DMxDST(N) __SYSREG(0xd2000008 + ((N) * 0x100), u32) /* src addr reg */
+
+#define DMxSIZ(N) __SYSREG(0xd200000c + ((N) * 0x100), u32) /* dest addr reg */
+#define DMxSIZ_CT 0x000fffff /* number of bytes to transfer */
+
+#define DMxCYC(N) __SYSREG(0xd2000010 + ((N) * 0x100), u32) /* intermittent
+ * size reg */
+#define DMxCYC_CYC 0x000000ff /* number of interrmittent transfers -1 */
+
+#define DM0IRQ 16 /* DMA channel 0 complete IRQ */
+#define DM1IRQ 17 /* DMA channel 1 complete IRQ */
+#define DM2IRQ 18 /* DMA channel 2 complete IRQ */
+#define DM3IRQ 19 /* DMA channel 3 complete IRQ */
+
+#define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */
+#define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */
+#define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */
+#define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */
+
+#ifndef __ASSEMBLY__
+
+struct mn10300_dmactl_regs {
+ u32 ctr;
+ const void *src;
+ void *dst;
+ u32 siz;
+ u32 cyc;
+} __attribute__((aligned(0x100)));
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_PROC_DMACTL_REGS_H */
next prev parent reply other threads:[~2010-10-26 2:54 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-10-26 2:53 [PATCH 00/43] MN10300: Add SMP support and AM34 CPU core support David Howells
2010-10-26 2:53 ` [PATCH 01/43] Partially revert patch that encloses asm-offset.h numbers in brackets David Howells
2010-10-26 2:53 ` [PATCH 02/43] MN10300: BUG to BUG_ON changes David Howells
2010-10-26 2:53 ` [PATCH 03/43] bitops: Change the bitmap index from int to unsigned long [mn10300] David Howells
2010-10-26 2:53 ` [PATCH 04/43] mn10300: Use pci_claim_resource David Howells
2010-10-26 2:53 ` [PATCH 05/43] MN10300: Prevent cnt32_to_63() from being preempted in sched_clock() David Howells
2010-10-26 2:53 ` [PATCH 06/43] Typedef SMP call function pointer David Howells
2010-10-26 2:53 ` [PATCH 07/43] MN10300: Don't cast away the volatile in test_bit() David Howells
2010-10-26 2:53 ` [PATCH 08/43] MN10300: Add reads[bwl]() and writes[bwl]() David Howells
2010-10-26 2:53 ` [PATCH 09/43] MN10300: Provide the functions to fully disable maskable interrupts David Howells
2010-10-26 2:53 ` [PATCH 10/43] MN10300: Differentiate AM33_2 and AM33_3 in config David Howells
2010-10-26 2:54 ` David Howells [this message]
2010-10-26 2:54 ` [PATCH 12/43] MN10300: Don't hard code the cacheline size in register defs David Howells
2010-10-26 2:54 ` [PATCH 13/43] MN10300: Add CPU register bits for AM34 David Howells
2010-10-26 2:54 ` [PATCH 14/43] MN10300: Remove monitor/JTAG functions David Howells
2010-10-26 2:54 ` [PATCH 15/43] MN10300: Cache: Split cache bits out of arch Kconfig David Howells
2010-10-26 2:54 ` [PATCH 16/43] MN10300: Provide a MN10300_CACHE_ENABLED config option David Howells
2010-10-26 2:54 ` [PATCH 17/43] MN10300: Reorder asm/cacheflush.h to put primitives first David Howells
2010-10-26 2:54 ` [PATCH 18/43] MN10300: AM34: The current cacheflush routines operate by controlling tag regs David Howells
2010-10-26 2:54 ` [PATCH 19/43] MN10300: Cacheflush functions should take unsigned long addresses David Howells
2010-10-26 2:54 ` [PATCH 20/43] MN10300: SMP: Differentiate local cache flushing David Howells
2010-10-26 2:54 ` [PATCH 21/43] MN10300: AM34: Add cacheflushing by using the AM34 purge registers David Howells
2010-10-26 2:54 ` [PATCH 22/43] MN10300: Allow some cacheflushes to be avoided if cache snooping is available David Howells
2010-10-26 2:55 ` [PATCH 23/43] MN10300: Cache: Implement SMP global cache flushing David Howells
2010-10-26 2:55 ` [PATCH 24/43] MN10300: Make the boot wrapper able to use writeback caching David Howells
2010-10-26 2:55 ` [PATCH 25/43] MN10300: AM34 erratum requires MMUCTR read and write on exception entry David Howells
2010-10-26 2:55 ` [PATCH 26/43] MN10300: Rename __flush_tlb*() to local_flush_tlb*() David Howells
2010-10-26 2:55 ` [PATCH 27/43] MN10300: Make the use of PIDR to mark TLB entries controllable David Howells
2010-10-26 2:55 ` [PATCH 28/43] MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control David Howells
2010-10-26 2:55 ` [PATCH 29/43] MN10300: SMP TLB flushing David Howells
2010-10-26 2:55 ` [PATCH 30/43] MN10300: Make the FPU operate in non-lazy mode under SMP David Howells
2010-10-26 2:55 ` [PATCH 31/43] MN10300: Implement atomic ops using atomic ops unit David Howells
2010-10-26 2:55 ` [PATCH 32/43] MN10300: Optimise do_csum() David Howells
2010-10-26 2:55 ` [PATCH 33/43] MN10300: Make various interrupt priority settings configurable David Howells
2010-10-26 2:56 ` [PATCH 34/43] MN10300: Delete idle_timestamp from irq_cpustat_t David Howells
2010-10-26 2:56 ` [PATCH 35/43] MN10300: And Panasonic AM34 subarch and implement SMP David Howells
2010-10-27 13:31 ` [Linux-am33-list] " Suzuki Takashi
2010-10-27 14:33 ` David Howells
2010-10-26 2:56 ` [PATCH 36/43] MN10300: ASB2364: Add support for SMSC911X and SMC911X David Howells
2010-10-26 2:56 ` [PATCH 37/43] MN10300: Map userspace atomic op regs as a vmalloc page David Howells
2010-10-26 2:56 ` [PATCH 38/43] MN10300: Specify an ELF HWCAP flag for MN10300 Atomic Operations Unit support David Howells
2010-10-26 2:56 ` [PATCH 39/43] MN10300: Generic time support David Howells
2010-10-26 2:56 ` [PATCH 40/43] MN10300: Update the ASB2303 defconfig David Howells
2010-10-26 2:56 ` [PATCH 41/43] MN10300: Create a defconfig for the ASB2364 board David Howells
2010-10-26 2:56 ` [PATCH 42/43] MN10300: Change "Matsushita" to "Panasonic" David Howells
2010-10-26 2:56 ` [PATCH 43/43] MN10300: Save frame pointer in thread_info struct rather than global var David Howells
2010-10-26 3:07 ` [PATCH 00/43] MN10300: Add SMP support and AM34 CPU core support David Howells
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20101026025400.23512.37567.stgit@warthog.procyon.org.uk \
--to=dhowells@redhat.com \
--cc=linux-am33-list@redhat.com \
--cc=linux-kernel@vger.kernel.org \
--cc=owada.kiyoshi@jp.panasonic.com \
--cc=takeuchi.akr@jp.panasonic.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®