From: David Howells <dhowells@redhat.com>
To: linux-am33-list@redhat.com
Cc: linux-kernel@vger.kernel.org,
Akira Takeuchi <takeuchi.akr@jp.panasonic.com>,
Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Subject: [PATCH 28/43] MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control
Date: Tue, 26 Oct 2010 03:55:31 +0100 [thread overview]
Message-ID: <20101026025531.23512.84445.stgit@warthog.procyon.org.uk> (raw)
In-Reply-To: <20101026025301.23512.24525.stgit@warthog.procyon.org.uk>
From: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control as the bits
are a more suitable layout.
Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: David Howells <dhowells@redhat.com>
---
arch/mn10300/include/asm/cpu-regs.h | 19 +++++-----
arch/mn10300/include/asm/pgtable.h | 66 +++++++++++++++++++----------------
arch/mn10300/mm/tlb-mn10300.S | 27 ++++++++++----
3 files changed, 65 insertions(+), 47 deletions(-)
diff --git a/arch/mn10300/include/asm/cpu-regs.h b/arch/mn10300/include/asm/cpu-regs.h
index 00e306c..90ed4a3 100644
--- a/arch/mn10300/include/asm/cpu-regs.h
+++ b/arch/mn10300/include/asm/cpu-regs.h
@@ -252,14 +252,6 @@ asm(" .am33_2\n");
#define xPTEL_PS_4Mb 0x00000c00 /* - 4Mb page */
#define xPTEL_PPN 0xfffff006 /* physical page number */
-#define xPTEL_V_BIT 0 /* bit numbers corresponding to above masks */
-#define xPTEL_UNUSED1_BIT 1
-#define xPTEL_UNUSED2_BIT 2
-#define xPTEL_C_BIT 3
-#define xPTEL_PV_BIT 4
-#define xPTEL_D_BIT 5
-#define xPTEL_G_BIT 9
-
#define IPTEU __SYSREG(0xc00000a4, u32) /* instruction TLB virtual addr */
#define DPTEU __SYSREG(0xc00000b4, u32) /* data TLB virtual addr */
#define xPTEU_VPN 0xfffffc00 /* virtual page number */
@@ -283,7 +275,16 @@ asm(" .am33_2\n");
#define xPTEL2_PS_128Kb 0x00000100 /* - 128Kb page */
#define xPTEL2_PS_1Kb 0x00000200 /* - 1Kb page */
#define xPTEL2_PS_4Mb 0x00000300 /* - 4Mb page */
-#define xPTEL2_PPN 0xfffffc00 /* physical page number */
+#define xPTEL2_CWT 0x00000400 /* cacheable write-through */
+#define xPTEL2_UNUSED1 0x00000800 /* unused bit (broadcast mask) */
+#define xPTEL2_PPN 0xfffff000 /* physical page number */
+
+#define xPTEL2_V_BIT 0 /* bit numbers corresponding to above masks */
+#define xPTEL2_C_BIT 1
+#define xPTEL2_PV_BIT 2
+#define xPTEL2_D_BIT 3
+#define xPTEL2_G_BIT 7
+#define xPTEL2_UNUSED1_BIT 11
#define MMUFCR __SYSREGC(0xc000009c, u32) /* MMU exception cause */
#define MMUFCR_IFC __SYSREGC(0xc000009c, u16) /* MMU instruction excep cause */
diff --git a/arch/mn10300/include/asm/pgtable.h b/arch/mn10300/include/asm/pgtable.h
index 16d8857..93c3294 100644
--- a/arch/mn10300/include/asm/pgtable.h
+++ b/arch/mn10300/include/asm/pgtable.h
@@ -98,38 +98,44 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
extern pte_t kernel_vmalloc_ptes[(VMALLOC_END - VMALLOC_START) / PAGE_SIZE];
#endif
-/* IPTEL/DPTEL bit assignments */
-#define _PAGE_BIT_VALID xPTEL_V_BIT
-#define _PAGE_BIT_ACCESSED xPTEL_UNUSED1_BIT /* mustn't be loaded into IPTEL/DPTEL */
-#define _PAGE_BIT_NX xPTEL_UNUSED2_BIT /* mustn't be loaded into IPTEL/DPTEL */
-#define _PAGE_BIT_CACHE xPTEL_C_BIT
-#define _PAGE_BIT_PRESENT xPTEL_PV_BIT
-#define _PAGE_BIT_DIRTY xPTEL_D_BIT
-#define _PAGE_BIT_GLOBAL xPTEL_G_BIT
-
-#define _PAGE_VALID xPTEL_V
-#define _PAGE_ACCESSED xPTEL_UNUSED1
-#define _PAGE_NX xPTEL_UNUSED2 /* no-execute bit */
-#define _PAGE_CACHE xPTEL_C
-#define _PAGE_PRESENT xPTEL_PV
-#define _PAGE_DIRTY xPTEL_D
-#define _PAGE_PROT xPTEL_PR
-#define _PAGE_PROT_RKNU xPTEL_PR_ROK
-#define _PAGE_PROT_WKNU xPTEL_PR_RWK
-#define _PAGE_PROT_RKRU xPTEL_PR_ROK_ROU
-#define _PAGE_PROT_WKRU xPTEL_PR_RWK_ROU
-#define _PAGE_PROT_WKWU xPTEL_PR_RWK_RWU
-#define _PAGE_GLOBAL xPTEL_G
-#define _PAGE_PSE xPTEL_PS_4Mb /* 4MB page */
-
-#define _PAGE_FILE xPTEL_UNUSED1_BIT /* set:pagecache unset:swap */
-
-#define __PAGE_PROT_UWAUX 0x040
-#define __PAGE_PROT_USER 0x080
-#define __PAGE_PROT_WRITE 0x100
+/* IPTEL2/DPTEL2 bit assignments */
+#define _PAGE_BIT_VALID xPTEL2_V_BIT
+#define _PAGE_BIT_CACHE xPTEL2_C_BIT
+#define _PAGE_BIT_PRESENT xPTEL2_PV_BIT
+#define _PAGE_BIT_DIRTY xPTEL2_D_BIT
+#define _PAGE_BIT_GLOBAL xPTEL2_G_BIT
+#define _PAGE_BIT_ACCESSED xPTEL2_UNUSED1_BIT /* mustn't be loaded into IPTEL2/DPTEL2 */
+
+#define _PAGE_VALID xPTEL2_V
+#define _PAGE_CACHE xPTEL2_C
+#define _PAGE_PRESENT xPTEL2_PV
+#define _PAGE_DIRTY xPTEL2_D
+#define _PAGE_PROT xPTEL2_PR
+#define _PAGE_PROT_RKNU xPTEL2_PR_ROK
+#define _PAGE_PROT_WKNU xPTEL2_PR_RWK
+#define _PAGE_PROT_RKRU xPTEL2_PR_ROK_ROU
+#define _PAGE_PROT_WKRU xPTEL2_PR_RWK_ROU
+#define _PAGE_PROT_WKWU xPTEL2_PR_RWK_RWU
+#define _PAGE_GLOBAL xPTEL2_G
+#define _PAGE_PS_MASK xPTEL2_PS
+#define _PAGE_PS_4Kb xPTEL2_PS_4Kb
+#define _PAGE_PS_128Kb xPTEL2_PS_128Kb
+#define _PAGE_PS_1Kb xPTEL2_PS_1Kb
+#define _PAGE_PS_4Mb xPTEL2_PS_4Mb
+#define _PAGE_PSE xPTEL2_PS_4Mb /* 4MB page */
+#define _PAGE_CACHE_WT xPTEL2_CWT
+#define _PAGE_ACCESSED xPTEL2_UNUSED1
+#define _PAGE_NX 0 /* no-execute bit */
+
+/* If _PAGE_VALID is clear, we use these: */
+#define _PAGE_FILE xPTEL2_C /* set:pagecache unset:swap */
+#define _PAGE_PROTNONE 0x000 /* If not present */
+
+#define __PAGE_PROT_UWAUX 0x010
+#define __PAGE_PROT_USER 0x020
+#define __PAGE_PROT_WRITE 0x040
#define _PAGE_PRESENTV (_PAGE_PRESENT|_PAGE_VALID)
-#define _PAGE_PROTNONE 0x000 /* If not present */
#ifndef __ASSEMBLY__
diff --git a/arch/mn10300/mm/tlb-mn10300.S b/arch/mn10300/mm/tlb-mn10300.S
index ccf6229..b994017 100644
--- a/arch/mn10300/mm/tlb-mn10300.S
+++ b/arch/mn10300/mm/tlb-mn10300.S
@@ -61,10 +61,16 @@ ENTRY(itlb_miss)
btst _PAGE_VALID,d2
beq itlb_miss_fault # jump if doesn't point to a page
# (might be a swap id)
+#if ((_PAGE_ACCESSED & 0xffffff00) == 0)
bset _PAGE_ACCESSED,(0,a2)
- and ~(xPTEL_UNUSED1|xPTEL_UNUSED2),d2
+#elif ((_PAGE_ACCESSED & 0xffff00ff) == 0)
+ bset +(_PAGE_ACCESSED >> 8),(1,a2)
+#else
+#error "_PAGE_ACCESSED value is out of range"
+#endif
+ and ~xPTEL2_UNUSED1,d2
itlb_miss_set:
- mov d2,(IPTEL) # change the TLB
+ mov d2,(IPTEL2) # change the TLB
#ifdef CONFIG_GDBSTUB
movm (sp),[d2,d3,a2]
#endif
@@ -118,10 +124,16 @@ ENTRY(dtlb_miss)
btst _PAGE_VALID,d2
beq dtlb_miss_fault # jump if doesn't point to a page
# (might be a swap id)
+#if ((_PAGE_ACCESSED & 0xffffff00) == 0)
bset _PAGE_ACCESSED,(0,a2)
- and ~(xPTEL_UNUSED1|xPTEL_UNUSED2),d2
+#elif ((_PAGE_ACCESSED & 0xffff00ff) == 0)
+ bset +(_PAGE_ACCESSED >> 8),(1,a2)
+#else
+#error "_PAGE_ACCESSED value is out of range"
+#endif
+ and ~xPTEL2_UNUSED1,d2
dtlb_miss_set:
- mov d2,(DPTEL) # change the TLB
+ mov d2,(DPTEL2) # change the TLB
#ifdef CONFIG_GDBSTUB
movm (sp),[d2,d3,a2]
#endif
@@ -156,13 +168,12 @@ ENTRY(itlb_aerror)
or 0x00010000,d1 # it's an instruction fetch
# determine the page address
- mov (IPTEU),a2
- mov a2,d0
+ mov (IPTEU),d0
and PAGE_MASK,d0
mov d0,(12,sp)
clr d0
- mov d0,(IPTEL)
+ mov d0,(IPTEL2)
or EPSW_IE,epsw
mov fp,d0
@@ -199,7 +210,7 @@ ENTRY(dtlb_aerror)
mov d0,(12,sp)
clr d0
- mov d0,(DPTEL)
+ mov d0,(DPTEL2)
or EPSW_IE,epsw
mov fp,d0
next prev parent reply other threads:[~2010-10-26 2:55 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-10-26 2:53 [PATCH 00/43] MN10300: Add SMP support and AM34 CPU core support David Howells
2010-10-26 2:53 ` [PATCH 01/43] Partially revert patch that encloses asm-offset.h numbers in brackets David Howells
2010-10-26 2:53 ` [PATCH 02/43] MN10300: BUG to BUG_ON changes David Howells
2010-10-26 2:53 ` [PATCH 03/43] bitops: Change the bitmap index from int to unsigned long [mn10300] David Howells
2010-10-26 2:53 ` [PATCH 04/43] mn10300: Use pci_claim_resource David Howells
2010-10-26 2:53 ` [PATCH 05/43] MN10300: Prevent cnt32_to_63() from being preempted in sched_clock() David Howells
2010-10-26 2:53 ` [PATCH 06/43] Typedef SMP call function pointer David Howells
2010-10-26 2:53 ` [PATCH 07/43] MN10300: Don't cast away the volatile in test_bit() David Howells
2010-10-26 2:53 ` [PATCH 08/43] MN10300: Add reads[bwl]() and writes[bwl]() David Howells
2010-10-26 2:53 ` [PATCH 09/43] MN10300: Provide the functions to fully disable maskable interrupts David Howells
2010-10-26 2:53 ` [PATCH 10/43] MN10300: Differentiate AM33_2 and AM33_3 in config David Howells
2010-10-26 2:54 ` [PATCH 11/43] MN10300: Move DMA engine control reg defs to MN103E010 processor directory David Howells
2010-10-26 2:54 ` [PATCH 12/43] MN10300: Don't hard code the cacheline size in register defs David Howells
2010-10-26 2:54 ` [PATCH 13/43] MN10300: Add CPU register bits for AM34 David Howells
2010-10-26 2:54 ` [PATCH 14/43] MN10300: Remove monitor/JTAG functions David Howells
2010-10-26 2:54 ` [PATCH 15/43] MN10300: Cache: Split cache bits out of arch Kconfig David Howells
2010-10-26 2:54 ` [PATCH 16/43] MN10300: Provide a MN10300_CACHE_ENABLED config option David Howells
2010-10-26 2:54 ` [PATCH 17/43] MN10300: Reorder asm/cacheflush.h to put primitives first David Howells
2010-10-26 2:54 ` [PATCH 18/43] MN10300: AM34: The current cacheflush routines operate by controlling tag regs David Howells
2010-10-26 2:54 ` [PATCH 19/43] MN10300: Cacheflush functions should take unsigned long addresses David Howells
2010-10-26 2:54 ` [PATCH 20/43] MN10300: SMP: Differentiate local cache flushing David Howells
2010-10-26 2:54 ` [PATCH 21/43] MN10300: AM34: Add cacheflushing by using the AM34 purge registers David Howells
2010-10-26 2:54 ` [PATCH 22/43] MN10300: Allow some cacheflushes to be avoided if cache snooping is available David Howells
2010-10-26 2:55 ` [PATCH 23/43] MN10300: Cache: Implement SMP global cache flushing David Howells
2010-10-26 2:55 ` [PATCH 24/43] MN10300: Make the boot wrapper able to use writeback caching David Howells
2010-10-26 2:55 ` [PATCH 25/43] MN10300: AM34 erratum requires MMUCTR read and write on exception entry David Howells
2010-10-26 2:55 ` [PATCH 26/43] MN10300: Rename __flush_tlb*() to local_flush_tlb*() David Howells
2010-10-26 2:55 ` [PATCH 27/43] MN10300: Make the use of PIDR to mark TLB entries controllable David Howells
2010-10-26 2:55 ` David Howells [this message]
2010-10-26 2:55 ` [PATCH 29/43] MN10300: SMP TLB flushing David Howells
2010-10-26 2:55 ` [PATCH 30/43] MN10300: Make the FPU operate in non-lazy mode under SMP David Howells
2010-10-26 2:55 ` [PATCH 31/43] MN10300: Implement atomic ops using atomic ops unit David Howells
2010-10-26 2:55 ` [PATCH 32/43] MN10300: Optimise do_csum() David Howells
2010-10-26 2:55 ` [PATCH 33/43] MN10300: Make various interrupt priority settings configurable David Howells
2010-10-26 2:56 ` [PATCH 34/43] MN10300: Delete idle_timestamp from irq_cpustat_t David Howells
2010-10-26 2:56 ` [PATCH 35/43] MN10300: And Panasonic AM34 subarch and implement SMP David Howells
2010-10-27 13:31 ` [Linux-am33-list] " Suzuki Takashi
2010-10-27 14:33 ` David Howells
2010-10-26 2:56 ` [PATCH 36/43] MN10300: ASB2364: Add support for SMSC911X and SMC911X David Howells
2010-10-26 2:56 ` [PATCH 37/43] MN10300: Map userspace atomic op regs as a vmalloc page David Howells
2010-10-26 2:56 ` [PATCH 38/43] MN10300: Specify an ELF HWCAP flag for MN10300 Atomic Operations Unit support David Howells
2010-10-26 2:56 ` [PATCH 39/43] MN10300: Generic time support David Howells
2010-10-26 2:56 ` [PATCH 40/43] MN10300: Update the ASB2303 defconfig David Howells
2010-10-26 2:56 ` [PATCH 41/43] MN10300: Create a defconfig for the ASB2364 board David Howells
2010-10-26 2:56 ` [PATCH 42/43] MN10300: Change "Matsushita" to "Panasonic" David Howells
2010-10-26 2:56 ` [PATCH 43/43] MN10300: Save frame pointer in thread_info struct rather than global var David Howells
2010-10-26 3:07 ` [PATCH 00/43] MN10300: Add SMP support and AM34 CPU core support David Howells
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