From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
To: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org
Cc: sathyanarayanan.kuppuswamy@linux.intel.com, aarcange@redhat.com,
ak@linux.intel.com, dan.j.williams@intel.com, david@redhat.com,
hpa@zytor.com, jgross@suse.com, jmattson@google.com,
joro@8bytes.org, jpoimboe@redhat.com, knsathya@kernel.org,
pbonzini@redhat.com, sdeep@vmware.com, seanjc@google.com,
tony.luck@intel.com, vkuznets@redhat.com, wanpengli@tencent.com,
x86@kernel.org, linux-kernel@vger.kernel.org,
"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Subject: [PATCHv3 12/32] x86/tdx: Handle in-kernel MMIO
Date: Fri, 18 Feb 2022 19:16:58 +0300 [thread overview]
Message-ID: <20220218161718.67148-13-kirill.shutemov@linux.intel.com> (raw)
In-Reply-To: <20220218161718.67148-1-kirill.shutemov@linux.intel.com>
In non-TDX VMs, MMIO is implemented by providing the guest a mapping
which will cause a VMEXIT on access and then the VMM emulating the
instruction that caused the VMEXIT. That's not possible for TDX VM.
To emulate an instruction an emulator needs two things:
- R/W access to the register file to read/modify instruction arguments
and see RIP of the faulted instruction.
- Read access to memory where instruction is placed to see what to
emulate. In this case it is guest kernel text.
Both of them are not available to VMM in TDX environment:
- Register file is never exposed to VMM. When a TD exits to the module,
it saves registers into the state-save area allocated for that TD.
The module then scrubs these registers before returning execution
control to the VMM, to help prevent leakage of TD state.
- Memory is encrypted a TD-private key. The CPU disallows software
other than the TDX module and TDs from making memory accesses using
the private key.
In TDX the MMIO regions are instead configured to trigger a #VE
exception in the guest. The guest #VE handler then emulates the MMIO
instruction inside the guest and converts it into a controlled hypercall
to the host.
MMIO addresses can be used with any CPU instruction that accesses
memory. Address only MMIO accesses done via io.h helpers, such as
'readl()' or 'writeq()'.
readX()/writeX() helpers limit the range of instructions which can trigger
MMIO. It makes MMIO instruction emulation feasible. Raw access to a MMIO
region allows the compiler to generate whatever instruction it wants.
Supporting all possible instructions is a task of a different scope.
MMIO access with anything other than helpers from io.h may result in
MMIO_DECODE_FAILED and an oops.
AMD SEV has the same limitations to MMIO handling.
=== Potential alternative approaches ===
== Paravirtualizing all MMIO ==
An alternative to letting MMIO induce a #VE exception is to avoid
the #VE in the first place. Similar to the port I/O case, it is
theoretically possible to paravirtualize MMIO accesses.
Like the exception-based approach offered here, a fully paravirtualized
approach would be limited to MMIO users that leverage common
infrastructure like the io.h macros.
However, any paravirtual approach would be patching approximately
120k call sites. With a conservative overhead estimation of 5 bytes per
call site (CALL instruction), it leads to bloating code by 600k.
Many drivers will never be used in the TDX environment and the bloat
cannot be justified.
== Patching TDX drivers ==
Rather than touching the entire kernel, it might also be possible to
just go after drivers that use MMIO in TDX guests. Right now, that's
limited only to virtio and some x86-specific drivers.
All virtio MMIO appears to be done through a single function, which
makes virtio eminently easy to patch. This will be implemented in the
future, removing the bulk of MMIO #VEs.
Co-developed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
---
arch/x86/coco/tdx.c | 110 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 110 insertions(+)
diff --git a/arch/x86/coco/tdx.c b/arch/x86/coco/tdx.c
index 83cbc94b30d0..74ab7c5a767d 100644
--- a/arch/x86/coco/tdx.c
+++ b/arch/x86/coco/tdx.c
@@ -8,11 +8,17 @@
#include <asm/coco.h>
#include <asm/tdx.h>
#include <asm/vmx.h>
+#include <asm/insn.h>
+#include <asm/insn-eval.h>
/* TDX module Call Leaf IDs */
#define TDX_GET_INFO 1
#define TDX_GET_VEINFO 3
+/* MMIO direction */
+#define EPT_READ 0
+#define EPT_WRITE 1
+
static struct {
unsigned int gpa_width;
unsigned long attributes;
@@ -184,6 +190,108 @@ static bool handle_cpuid(struct pt_regs *regs)
return true;
}
+static bool mmio_read(int size, unsigned long addr, unsigned long *val)
+{
+ struct tdx_hypercall_args args = {
+ .r10 = TDX_HYPERCALL_STANDARD,
+ .r11 = EXIT_REASON_EPT_VIOLATION,
+ .r12 = size,
+ .r13 = EPT_READ,
+ .r14 = addr,
+ .r15 = *val,
+ };
+
+ if (__tdx_hypercall(&args, TDX_HCALL_HAS_OUTPUT))
+ return false;
+ *val = args.r11;
+ return true;
+}
+
+static bool mmio_write(int size, unsigned long addr, unsigned long val)
+{
+ return !_tdx_hypercall(EXIT_REASON_EPT_VIOLATION, size, EPT_WRITE,
+ addr, val);
+}
+
+static bool handle_mmio(struct pt_regs *regs, struct ve_info *ve)
+{
+ char buffer[MAX_INSN_SIZE];
+ unsigned long *reg, val;
+ struct insn insn = {};
+ enum mmio_type mmio;
+ int size, extend_size;
+ u8 extend_val = 0;
+
+ if (copy_from_kernel_nofault(buffer, (void *)regs->ip, MAX_INSN_SIZE))
+ return false;
+
+ if (insn_decode(&insn, buffer, MAX_INSN_SIZE, INSN_MODE_64))
+ return false;
+
+ mmio = insn_decode_mmio(&insn, &size);
+ if (WARN_ON_ONCE(mmio == MMIO_DECODE_FAILED))
+ return false;
+
+ if (mmio != MMIO_WRITE_IMM && mmio != MMIO_MOVS) {
+ reg = insn_get_modrm_reg_ptr(&insn, regs);
+ if (!reg)
+ return false;
+ }
+
+ ve->instr_len = insn.length;
+
+ switch (mmio) {
+ case MMIO_WRITE:
+ memcpy(&val, reg, size);
+ return mmio_write(size, ve->gpa, val);
+ case MMIO_WRITE_IMM:
+ val = insn.immediate.value;
+ return mmio_write(size, ve->gpa, val);
+ case MMIO_READ:
+ case MMIO_READ_ZERO_EXTEND:
+ case MMIO_READ_SIGN_EXTEND:
+ break;
+ case MMIO_MOVS:
+ case MMIO_DECODE_FAILED:
+ return false;
+ default:
+ BUG();
+ }
+
+ /* Handle reads */
+ if (!mmio_read(size, ve->gpa, &val))
+ return false;
+
+ switch (mmio) {
+ case MMIO_READ:
+ /* Zero-extend for 32-bit operation */
+ extend_size = size == 4 ? sizeof(*reg) : 0;
+ break;
+ case MMIO_READ_ZERO_EXTEND:
+ /* Zero extend based on operand size */
+ extend_size = insn.opnd_bytes;
+ break;
+ case MMIO_READ_SIGN_EXTEND:
+ /* Sign extend based on operand size */
+ extend_size = insn.opnd_bytes;
+ if (size == 1 && val & BIT(7))
+ extend_val = 0xFF;
+ else if (size > 1 && val & BIT(15))
+ extend_val = 0xFF;
+ break;
+ case MMIO_MOVS:
+ case MMIO_DECODE_FAILED:
+ return false;
+ default:
+ BUG();
+ }
+
+ if (extend_size)
+ memset(reg, extend_val, extend_size);
+ memcpy(reg, &val, size);
+ return true;
+}
+
void tdx_get_ve_info(struct ve_info *ve)
{
struct tdx_module_output out;
@@ -237,6 +345,8 @@ static bool virt_exception_kernel(struct pt_regs *regs, struct ve_info *ve)
return write_msr(regs);
case EXIT_REASON_CPUID:
return handle_cpuid(regs);
+ case EXIT_REASON_EPT_VIOLATION:
+ return handle_mmio(regs, ve);
default:
pr_warn("Unexpected #VE: %lld\n", ve->exit_reason);
return false;
--
2.34.1
next prev parent reply other threads:[~2022-02-18 16:17 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-18 16:16 [PATCHv3 00/32] TDX Guest: TDX core support Kirill A. Shutemov
2022-02-18 16:16 ` [PATCHv3 01/32] x86/mm: Fix warning on build with X86_MEM_ENCRYPT=y Kirill A. Shutemov
2022-02-18 19:39 ` Dave Hansen
2022-02-18 16:16 ` [PATCHv3 02/32] x86/coco: Add API to handle encryption mask Kirill A. Shutemov
2022-02-18 20:36 ` Dave Hansen
2022-02-18 21:33 ` Kirill A. Shutemov
2022-02-18 21:58 ` Borislav Petkov
2022-02-19 0:13 ` [PATCHv3.1 2/32] x86/coco: Explicitly declare type of confidential computing platform Kirill A. Shutemov
2022-02-19 0:13 ` [PATCHv3.1 2.1/2] x86/coco: Add API to handle encryption mask Kirill A. Shutemov
2022-02-21 18:31 ` Tom Lendacky
2022-02-21 22:14 ` Kirill A. Shutemov
2022-02-21 21:05 ` Borislav Petkov
2022-02-21 22:10 ` Kirill A. Shutemov
2022-02-21 22:36 ` Borislav Petkov
2022-02-21 23:25 ` Kirill A. Shutemov
2022-02-22 13:31 ` Borislav Petkov
2022-02-21 11:07 ` [PATCHv3.1 2/32] x86/coco: Explicitly declare type of confidential computing platform Borislav Petkov
2022-02-21 11:44 ` Kirill A. Shutemov
2022-02-21 12:05 ` Borislav Petkov
2022-02-21 13:52 ` Wei Liu
2022-02-21 20:20 ` Borislav Petkov
2022-02-21 19:28 ` [PATCHv3 02/32] x86/coco: Add API to handle encryption mask Dave Hansen
2022-02-21 19:49 ` Borislav Petkov
2022-02-21 22:21 ` Kirill A. Shutemov
2022-02-21 22:56 ` Borislav Petkov
2022-02-21 23:18 ` Kirill A. Shutemov
2022-02-22 13:28 ` Borislav Petkov
2022-02-21 22:28 ` Kirill A. Shutemov
2022-02-22 11:03 ` Kirill A. Shutemov
2022-02-22 13:37 ` Borislav Petkov
2022-02-22 13:52 ` Kirill A. Shutemov
2022-02-18 16:16 ` [PATCHv3 03/32] x86/tdx: Detect running as a TDX guest in early boot Kirill A. Shutemov
2022-02-18 21:07 ` Dave Hansen
2022-02-20 15:01 ` Kirill A. Shutemov
2022-02-18 16:16 ` [PATCHv3 04/32] x86/tdx: Provide common base for SEAMCALL and TDCALL C wrappers Kirill A. Shutemov
2022-02-18 16:16 ` [PATCHv3 05/32] x86/tdx: Add __tdx_module_call() and __tdx_hypercall() helper functions Kirill A. Shutemov
2022-02-18 16:16 ` [PATCHv3 06/32] x86/tdx: Extend the confidential computing API to support TDX guests Kirill A. Shutemov
2022-02-18 16:16 ` [PATCHv3 07/32] x86/tdx: Exclude shared bit from __PHYSICAL_MASK Kirill A. Shutemov
2022-02-18 16:16 ` [PATCHv3 08/32] x86/traps: Add #VE support for TDX guest Kirill A. Shutemov
2022-02-22 7:19 ` Dingji Li
2022-02-22 11:11 ` Kirill A. Shutemov
2022-02-18 16:16 ` [PATCHv3 09/32] x86/tdx: Add HLT support for TDX guests Kirill A. Shutemov
2022-02-18 16:16 ` [PATCHv3 10/32] x86/tdx: Add MSR " Kirill A. Shutemov
2022-02-18 16:16 ` [PATCHv3 11/32] x86/tdx: Handle CPUID via #VE Kirill A. Shutemov
2022-02-18 16:16 ` Kirill A. Shutemov [this message]
2022-02-18 16:16 ` [PATCHv3 13/32] x86/tdx: Detect TDX at early kernel decompression time Kirill A. Shutemov
2022-02-21 11:37 ` Cyrill Gorcunov
2022-02-21 13:53 ` Kirill A. Shutemov
2022-02-18 16:17 ` [PATCHv3 14/32] x86: Adjust types used in port I/O helpers Kirill A. Shutemov
2022-02-18 16:17 ` [PATCHv3 15/32] x86: Consolidate " Kirill A. Shutemov
2022-02-18 16:17 ` [PATCHv3 16/32] x86/boot: Allow to hook up alternative " Kirill A. Shutemov
2022-02-21 20:04 ` Tom Lendacky
2022-02-21 22:02 ` Kirill A. Shutemov
2022-02-22 1:25 ` Josh Poimboeuf
2022-02-18 16:17 ` [PATCHv3 17/32] x86/boot/compressed: Support TDX guest port I/O at decompression time Kirill A. Shutemov
2022-02-18 16:17 ` [PATCHv3 18/32] x86/tdx: Add port I/O emulation Kirill A. Shutemov
2022-02-18 16:17 ` [PATCHv3 19/32] x86/tdx: Handle early boot port I/O Kirill A. Shutemov
2022-02-18 16:17 ` [PATCHv3 20/32] x86/tdx: Wire up KVM hypercalls Kirill A. Shutemov
2022-02-18 16:17 ` [PATCHv3 21/32] x86/boot: Add a trampoline for booting APs via firmware handoff Kirill A. Shutemov
2022-02-18 16:17 ` [PATCHv3 22/32] x86/acpi, x86/boot: Add multiprocessor wake-up support Kirill A. Shutemov
2022-02-18 16:17 ` [PATCHv3 23/32] x86/boot: Set CR0.NE early and keep it set during the boot Kirill A. Shutemov
2022-02-18 16:17 ` [PATCHv3 24/32] x86/boot: Avoid #VE during boot for TDX platforms Kirill A. Shutemov
2022-02-18 16:17 ` [PATCHv3 25/32] x86/topology: Disable CPU online/offline control for TDX guests Kirill A. Shutemov
2022-02-18 16:17 ` [PATCHv3 26/32] x86/tdx: Make pages shared in ioremap() Kirill A. Shutemov
2022-02-18 16:17 ` [PATCHv3 27/32] x86/mm/cpa: Generailize __set_memory_enc_pgtable() Kirill A. Shutemov
2022-02-21 15:46 ` Brijesh Singh
2022-02-18 16:17 ` [PATCHv3 28/32] x86/mm/cpa: Add support for TDX shared memory Kirill A. Shutemov
2022-02-18 16:17 ` [PATCHv3 29/32] x86/kvm: Use bounce buffers for TD guest Kirill A. Shutemov
2022-02-18 16:17 ` [PATCHv3 30/32] x86/tdx: ioapic: Add shared bit for IOAPIC base address Kirill A. Shutemov
2022-02-18 16:17 ` [PATCHv3 31/32] ACPICA: Avoid cache flush on TDX guest Kirill A. Shutemov
2022-02-18 16:17 ` [PATCHv3 32/32] Documentation/x86: Document TDX kernel architecture Kirill A. Shutemov
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