[RFC PATCH] x86/cpu: Update Intel model naming rule

[RFC PATCH] x86/cpu: Update Intel model naming rule

[kan.liang]

From: Kan Liang <kan.liang@linux.intel.com>

The Intel model naming rule doesn't reflect the current Intel model
names. For example, the code name of processors is actually used for
hybrid products and the latest Atom and big core products.

The patch is to add the code name of processors into the Intel model
naming rule. Because
- For the hybrid processors, it's impossible to use the code name of
the micro-architecture. A processor has multiple micro-architectures.
- For the big core, the code name of processors is already used for the
products after Sky Lake. Before Sky Lake, it seems the code name of
the micro-architecture is the same as the code name of the processor.
- For the Atom, the processor name is used since Sierra Forest and
Grand Ridge. Both server products have the e-cores with the exact same
micro-architecture. Using the code name of processors should be a better
choice to distinguish them.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
 arch/x86/include/asm/intel-family.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index b3af2d45bbbb..d79447749b82 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -10,13 +10,18 @@
  * that group keep the CPUID for the variants sorted by model number.
  *
  * The defined symbol names have the following form:
+ *	# For old atom platforms before Sierra Forest
  *	INTEL_FAM6{OPTFAMILY}_{MICROARCH}{OPTDIFF}
+ *	OR
+ *	# For big core, new atom after Sierra Forest, and hybrid
+ *	INTEL_FAM6{OPTFAMILY}_{PROCESSOR}{OPTDIFF}
  * where:
  * OPTFAMILY	Describes the family of CPUs that this belongs to. Default
  *		is assumed to be "_CORE" (and should be omitted). Other values
  *		currently in use are _ATOM and _XEON_PHI
  * MICROARCH	Is the code name for the micro-architecture for this core.
  *		N.B. Not the platform name.
+ * PROCESSOR	Is the code name for the processor
  * OPTDIFF	If needed, a short string to differentiate by market segment.
  *
  *		Common OPTDIFFs:
@@ -112,6 +117,8 @@
 #define INTEL_FAM6_GRANITERAPIDS_X	0xAD
 #define INTEL_FAM6_GRANITERAPIDS_D	0xAE
 
+/* "Hybrid core" Processors */
+
 #define INTEL_FAM6_ALDERLAKE		0x97	/* Golden Cove / Gracemont */
 #define INTEL_FAM6_ALDERLAKE_L		0x9A	/* Golden Cove / Gracemont */
 #define INTEL_FAM6_ALDERLAKE_N		0xBE
-- 
2.35.1

Re: [RFC PATCH] x86/cpu: Update Intel model naming rule

[Dave Hansen]

On 6/6/23 10:02, kan.liang@linux.intel.com wrote:
>   * MICROARCH	Is the code name for the micro-architecture for this core.
>   *		N.B. Not the platform name.
> + * PROCESSOR	Is the code name for the processor

I think we should refine the definition of "MICROARCH" here.  We want it
to refer to the combination of cores, not just "this core".

ALDERLAKE is a fine name to refer to a processor that has a mix of
"Golden Cove / Gracemont" cores.  Let's just have it say:

   * MICROARCH	Is the code name for the collection of micro-
		architectures for this processor.  N.B. Not the
		platform name.

Re: [RFC PATCH] x86/cpu: Update Intel model naming rule

[Liang, Kan]

On 2023-06-06 1:28 p.m., Dave Hansen wrote:
> On 6/6/23 10:02, kan.liang@linux.intel.com wrote:
>>   * MICROARCH	Is the code name for the micro-architecture for this core.
>>   *		N.B. Not the platform name.
>> + * PROCESSOR	Is the code name for the processor
> 
> I think we should refine the definition of "MICROARCH" here.  We want it
> to refer to the combination of cores, not just "this core".
> 
> ALDERLAKE is a fine name to refer to a processor that has a mix of
> "Golden Cove / Gracemont" cores.  Let's just have it say:
> 
>    * MICROARCH	Is the code name for the collection of micro-
> 		architectures for this processor.  N.B. Not the
> 		platform name.
> 

OK. It should address the issue for hybrid.

But for the non-hybrid, it may not work by only redefining the
"MICROARCH". They usually have different code name for microarchitecture
and processor. For example, the Sapphire Rapids should be the code name
of the processor, while the Golden Cove is the code name of the
microarchitecture.

The other option is to still only use the microarch name. Then we have
to change all the big core names at least since Ice Lake and the latest
Atom names. All the names below will be changed. We also need to change
all the places where using them. It could be a big change.

#define INTEL_FAM6_ICELAKE_X		0x6A	/* Sunny Cove */
#define INTEL_FAM6_ICELAKE_D		0x6C	/* Sunny Cove */
#define INTEL_FAM6_ICELAKE		0x7D	/* Sunny Cove */
#define INTEL_FAM6_ICELAKE_L		0x7E	/* Sunny Cove */
#define INTEL_FAM6_ICELAKE_NNPI		0x9D	/* Sunny Cove */

#define INTEL_FAM6_ROCKETLAKE		0xA7	/* Cypress Cove */

#define INTEL_FAM6_TIGERLAKE_L		0x8C	/* Willow Cove */
#define INTEL_FAM6_TIGERLAKE		0x8D	/* Willow Cove */

#define INTEL_FAM6_SAPPHIRERAPIDS_X	0x8F	/* Golden Cove */

#define INTEL_FAM6_EMERALDRAPIDS_X	0xCF

#define INTEL_FAM6_GRANITERAPIDS_X	0xAD
#define INTEL_FAM6_GRANITERAPIDS_D	0xAE

#define INTEL_FAM6_SIERRAFOREST_X	0xAF

#define INTEL_FAM6_GRANDRIDGE		0xB6

Thanks,
Kan