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From: Leo Yan <leo.yan@arm.com>
To: James Clark <james.clark@linaro.org>
Cc: Jie Gan <quic_jiegan@quicinc.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Mike Leach <mike.leach@linaro.org>,
	Anshuman Khandual <anshuman.khandual@arm.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Maxime Coquelin <mcoquelin.stm32@gmail.com>,
	Alexandre Torgue <alexandre.torgue@foss.st.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	linux-stm32@st-md-mailman.stormreply.com
Subject: Re: [PATCH v1 9/9] coresight: Consolidate clock enabling
Date: Tue, 1 Apr 2025 16:29:45 +0100	[thread overview]
Message-ID: <20250401152945.GE115840@e132581.arm.com> (raw)
In-Reply-To: <b9046586-c884-484f-a308-9f256d3d99f5@linaro.org>

On Tue, Apr 01, 2025 at 03:58:42PM +0100, James Clark wrote:

[...]

> >   /*
> > - * Attempt to find and enable "APB clock" for the given device
> > + * Attempt to find and enable programming clock (pclk) and trace clock (atclk)
> > + * for the given device.
> >    *
> > - * Returns:
> > + * The AMBA bus driver will cover the pclk, to avoid duplicate operations,
> > + * skip to get and enable the pclk for an AMBA device.
> >    *
> > - * clk   - Clock is found and enabled
> > - * NULL  - Clock is not needed as it is managed by the AMBA bus driver
> > - * ERROR - Clock is found but failed to enable
> > + * atclk is an optional clock, it will be only enabled when it is existed.
> > + * Otherwise, a NULL pointer will be returned to caller.
> > + *
> > + * Returns: '0' on Success; Error code otherwise.
> >    */
> > -static inline struct clk *coresight_get_enable_apb_pclk(struct device *dev)
> > +static inline int coresight_get_enable_clocks(struct device *dev,
> > +					      struct clk **pclk,
> > +					      struct clk **atclk)
> 
> This function has grown a bit now, probably best to remove it from the
> header and export it instead.

Sure.  I can move this function into coresight-core.c file.

> >   {
> > -	struct clk *pclk = NULL;
> > +	WARN_ON(!pclk);
> >   	if (!dev_is_amba(dev)) {
> > -		pclk = devm_clk_get_enabled(dev, "apb_pclk");
> > -		if (IS_ERR(pclk))
> > -			pclk = devm_clk_get_enabled(dev, "apb");
> > +		*pclk = devm_clk_get_enabled(dev, "apb_pclk");
> > +		if (IS_ERR(*pclk))
> > +			*pclk = devm_clk_get_enabled(dev, "apb");
> > +		if (IS_ERR(*pclk))
> > +			return PTR_ERR(*pclk);
> > +	} else {
> > +		/* Don't enable pclk for an AMBA device */
> > +		*pclk = NULL;
> 
> Now the "apb" clock won't be enabled for amba devices. I'm assuming that's
> fine if the clock was always called "apb_pclk" for them, but the commit that
> added the new clock name didn't specify any special casing either.

> Can we have a comment that says it's deliberate? But the more I think about
> it the more I'm confused why CTCU needed a different clock name to be
> defined, when all the other Coresight devices use "apb_pclk".

Yes, seems to me, "apb" clock is the same thing with "apb_pclk".  As
CTCU DT binding has been merged, for backward compatible, we cannot
remove it now.

CTCU driver only supports static probe, it is never probed by AMBA bus
driver.  I think this is another reason that "apb_pclk" is not used in
CTCU driver.  I can add a comment like:

  "apb_pclk" is the default clock name used by the AMBA bus driver,
  while "apb" is used only by the CTCU driver.  A CoreSight driver
  should use "apb_pclk" as its programming clock name.

Thanks,
Leo

> >   	}
> > -	return pclk;
> > +	if (atclk) {
> > +		*atclk = devm_clk_get_optional_enabled(dev, "atclk");
> > +		if (IS_ERR(*atclk))
> > +			return PTR_ERR(*atclk);
> > +	}
> > +
> > +	return 0;
> >   }
> >   #define CORESIGHT_PIDRn(i)	(0xFE0 + ((i) * 4))
> 

  reply	other threads:[~2025-04-01 15:29 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-27 11:37 [PATCH v1 0/9] coresight: Fix and improve clock usage Leo Yan
2025-03-27 11:37 ` [PATCH v1 1/9] coresight: tmc: Support atclk Leo Yan
2025-04-03  5:50   ` Anshuman Khandual
2025-04-22  8:21     ` Leo Yan
2025-03-27 11:37 ` [PATCH v1 2/9] coresight: catu: " Leo Yan
2025-04-03  6:02   ` Anshuman Khandual
2025-03-27 11:37 ` [PATCH v1 3/9] coresight: etm4x: " Leo Yan
2025-04-03  6:23   ` Anshuman Khandual
2025-03-27 11:37 ` [PATCH v1 4/9] coresight: Disable programming clock properly Leo Yan
2025-03-27 11:37 ` [PATCH v1 5/9] coresight: Avoid enable programming clock duplicately Leo Yan
2025-04-03  6:48   ` Anshuman Khandual
2025-04-22 12:24     ` Leo Yan
2025-03-27 11:38 ` [PATCH v1 6/9] coresight: Disable trace bus clock properly Leo Yan
2025-04-03  7:25   ` Anshuman Khandual
2025-04-22 12:29     ` Leo Yan
2025-03-27 11:38 ` [PATCH v1 7/9] coresight: Make clock sequence consistent Leo Yan
2025-04-03  7:10   ` Anshuman Khandual
2025-04-22  9:21     ` Leo Yan
2025-03-27 11:38 ` [PATCH v1 8/9] coresight: Refactor runtime PM Leo Yan
2025-03-27 11:38 ` [PATCH v1 9/9] coresight: Consolidate clock enabling Leo Yan
2025-04-01 14:58   ` James Clark
2025-04-01 15:29     ` Leo Yan [this message]
2025-04-02  0:55     ` Jie Gan
2025-04-02  9:01       ` Leo Yan
2025-04-03  0:29         ` Jie Gan

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