From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Leo Yan <leo.yan@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com
Subject: Re: [PATCH v1 7/9] coresight: Make clock sequence consistent
Date: Thu, 3 Apr 2025 12:40:39 +0530 [thread overview]
Message-ID: <d94c6f97-4ca8-4a3a-ae8a-8e872eaa8d3b@arm.com> (raw)
In-Reply-To: <20250327113803.1452108-8-leo.yan@arm.com>
On 3/27/25 17:08, Leo Yan wrote:
> Since atclk is enabled after pclk during the probe phase, this commit
> maintains the same sequence for the runtime resume flow.
>
> Signed-off-by: Leo Yan <leo.yan@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-funnel.c | 6 +++---
> drivers/hwtracing/coresight/coresight-replicator.c | 6 +++---
> drivers/hwtracing/coresight/coresight-stm.c | 6 +++---
> drivers/hwtracing/coresight/coresight-tpiu.c | 6 +++---
> 4 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c
> index ec6d3e656548..e378c2fffca9 100644
> --- a/drivers/hwtracing/coresight/coresight-funnel.c
> +++ b/drivers/hwtracing/coresight/coresight-funnel.c
> @@ -299,11 +299,11 @@ static int funnel_runtime_resume(struct device *dev)
> {
> struct funnel_drvdata *drvdata = dev_get_drvdata(dev);
>
> - if (drvdata && !IS_ERR(drvdata->atclk))
> - clk_prepare_enable(drvdata->atclk);
> -
> if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
> clk_prepare_enable(drvdata->pclk);
> +
> + if (drvdata && !IS_ERR(drvdata->atclk))
> + clk_prepare_enable(drvdata->atclk);
> return 0;
> }
funnel_probe() enables pclk after atclk though - which needs to be
reversed as well ?
static int funnel_probe(struct device *dev, struct resource *res)
{
..................
drvdata->atclk = devm_clk_get_optional_enabled(dev, "atclk");
if (IS_ERR(drvdata->atclk))
return PTR_ERR(drvdata->atclk);
drvdata->pclk = coresight_get_enable_apb_pclk(dev);
if (IS_ERR(drvdata->pclk))
return PTR_ERR(drvdata->pclk);
> #endif
> diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c
> index 460af0f7b537..78854f586e89 100644
> --- a/drivers/hwtracing/coresight/coresight-replicator.c
> +++ b/drivers/hwtracing/coresight/coresight-replicator.c
> @@ -337,11 +337,11 @@ static int replicator_runtime_resume(struct device *dev)
> {
> struct replicator_drvdata *drvdata = dev_get_drvdata(dev);
>
> - if (drvdata && !IS_ERR(drvdata->atclk))
> - clk_prepare_enable(drvdata->atclk);
> -
> if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
> clk_prepare_enable(drvdata->pclk);
> +
> + if (drvdata && !IS_ERR(drvdata->atclk))
> + clk_prepare_enable(drvdata->atclk);
> return 0;
> }
replicator_probe() enables pclk after atclk though - which needs to be
reversed as well ?
static int replicator_probe(struct device *dev, struct resource *res)
{
..................
drvdata->atclk = devm_clk_get_optional_enabled(dev, "atclk");
if (IS_ERR(drvdata->atclk))
return PTR_ERR(drvdata->atclk);
drvdata->pclk = coresight_get_enable_apb_pclk(dev);
if (IS_ERR(drvdata->pclk))
return PTR_ERR(drvdata->pclk);
> #endif
> diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c
> index f13fbab4d7a2..ddb4f6678efd 100644
> --- a/drivers/hwtracing/coresight/coresight-stm.c
> +++ b/drivers/hwtracing/coresight/coresight-stm.c
> @@ -972,11 +972,11 @@ static int stm_runtime_resume(struct device *dev)
> {
> struct stm_drvdata *drvdata = dev_get_drvdata(dev);
>
> - if (drvdata && !IS_ERR(drvdata->atclk))
> - clk_prepare_enable(drvdata->atclk);
> -
> if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
> clk_prepare_enable(drvdata->pclk);
> +
> + if (drvdata && !IS_ERR(drvdata->atclk))
> + clk_prepare_enable(drvdata->atclk);
> return 0;
> }
> #endif
same here as well.
> diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c
> index cac1b5bba086..8212959f60d4 100644
> --- a/drivers/hwtracing/coresight/coresight-tpiu.c
> +++ b/drivers/hwtracing/coresight/coresight-tpiu.c
> @@ -220,11 +220,11 @@ static int tpiu_runtime_resume(struct device *dev)
> {
> struct tpiu_drvdata *drvdata = dev_get_drvdata(dev);
>
> - if (drvdata && !IS_ERR(drvdata->atclk))
> - clk_prepare_enable(drvdata->atclk);
> -
> if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
> clk_prepare_enable(drvdata->pclk);
> +
> + if (drvdata && !IS_ERR(drvdata->atclk))
> + clk_prepare_enable(drvdata->atclk);
> return 0;
> }
> #endif
same here as well.
I assume this patch is trying to have the same clock sequence enablement
during original probe and resume path and then just the reverse sequence
during suspend path.
next prev parent reply other threads:[~2025-04-03 7:10 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-27 11:37 [PATCH v1 0/9] coresight: Fix and improve clock usage Leo Yan
2025-03-27 11:37 ` [PATCH v1 1/9] coresight: tmc: Support atclk Leo Yan
2025-04-03 5:50 ` Anshuman Khandual
2025-04-22 8:21 ` Leo Yan
2025-03-27 11:37 ` [PATCH v1 2/9] coresight: catu: " Leo Yan
2025-04-03 6:02 ` Anshuman Khandual
2025-03-27 11:37 ` [PATCH v1 3/9] coresight: etm4x: " Leo Yan
2025-04-03 6:23 ` Anshuman Khandual
2025-03-27 11:37 ` [PATCH v1 4/9] coresight: Disable programming clock properly Leo Yan
2025-03-27 11:37 ` [PATCH v1 5/9] coresight: Avoid enable programming clock duplicately Leo Yan
2025-04-03 6:48 ` Anshuman Khandual
2025-04-22 12:24 ` Leo Yan
2025-03-27 11:38 ` [PATCH v1 6/9] coresight: Disable trace bus clock properly Leo Yan
2025-04-03 7:25 ` Anshuman Khandual
2025-04-22 12:29 ` Leo Yan
2025-03-27 11:38 ` [PATCH v1 7/9] coresight: Make clock sequence consistent Leo Yan
2025-04-03 7:10 ` Anshuman Khandual [this message]
2025-04-22 9:21 ` Leo Yan
2025-03-27 11:38 ` [PATCH v1 8/9] coresight: Refactor runtime PM Leo Yan
2025-03-27 11:38 ` [PATCH v1 9/9] coresight: Consolidate clock enabling Leo Yan
2025-04-01 14:58 ` James Clark
2025-04-01 15:29 ` Leo Yan
2025-04-02 0:55 ` Jie Gan
2025-04-02 9:01 ` Leo Yan
2025-04-03 0:29 ` Jie Gan
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