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From: Ard Biesheuvel <ardb+git@google.com>
To: linux-kernel@vger.kernel.org
Cc: x86@kernel.org, Ard Biesheuvel <ardb@kernel.org>,
	Ingo Molnar <mingo@kernel.org>,
	 Linus Torvalds <torvalds@linux-foundation.org>,
	Brian Gerst <brgerst@gmail.com>
Subject: [PATCH v3 7/7] x86/cpu: Make CPU capability overrides __ro_after_init
Date: Wed, 14 May 2025 12:42:50 +0200	[thread overview]
Message-ID: <20250514104242.1275040-16-ardb+git@google.com> (raw)
In-Reply-To: <20250514104242.1275040-9-ardb+git@google.com>

From: Ard Biesheuvel <ardb@kernel.org>

CPU capabilities are set at init time so they can be made R/O once the
boot completes.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
 arch/x86/kernel/cpu/common.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 08a586606e24..19b310bd55ae 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -702,8 +702,8 @@ static const char *table_lookup_model(struct cpuinfo_x86 *c)
 }
 
 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
-__u32 __read_mostly cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
-__u32 __read_mostly cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
+__u32 __ro_after_init cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
+__u32 __ro_after_init cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
 
 #ifdef CONFIG_X86_32
 /* The 32-bit entry code needs to find cpu_entry_area. */
-- 
2.49.0.1101.gccaa498523-goog


      parent reply	other threads:[~2025-05-14 10:43 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-14 10:42 [PATCH v3 0/7] x86: Robustify pgtable_l5_enabled() Ard Biesheuvel
2025-05-14 10:42 ` [PATCH v3 1/7] x86/cpu: Use a new feature flag for 5 level paging Ard Biesheuvel
2025-05-15  7:06   ` Ingo Molnar
2025-05-15  7:45   ` Ingo Molnar
2025-05-15  8:07     ` Kirill A. Shutemov
2025-05-15  8:22       ` Ingo Molnar
2025-05-15 10:12     ` Ard Biesheuvel
2025-05-15 23:24       ` Sean Christopherson
2025-05-16  8:31         ` Ard Biesheuvel
2025-05-15  9:51   ` Borislav Petkov
2025-05-15 10:17     ` Ard Biesheuvel
2025-05-15 10:39       ` Borislav Petkov
2025-05-15 10:57         ` Ard Biesheuvel
2025-05-15 13:11   ` Borislav Petkov
2025-05-15 13:33     ` Ard Biesheuvel
2025-05-17 16:59       ` David Laight
2025-05-15 18:20     ` Shivank Garg
2025-05-15 19:11       ` Borislav Petkov
2025-05-16  9:17         ` Kirill A. Shutemov
2025-05-14 10:42 ` [PATCH v3 2/7] x86/cpu: Allow caps to be set arbitrarily early Ard Biesheuvel
2025-05-15  6:56   ` Ingo Molnar
2025-05-15  7:50     ` Ingo Molnar
2025-05-15  7:55     ` Kirill A. Shutemov
2025-05-15  8:18       ` Ingo Molnar
2025-05-15  9:45         ` Ard Biesheuvel
2025-05-15 12:08           ` Ingo Molnar
2025-05-14 10:42 ` [PATCH v3 3/7] x86/asm-offsets: Export struct cpuinfo_x86 layout for asm use Ard Biesheuvel
2025-05-15  7:10   ` Ingo Molnar
2025-05-15  7:58   ` [tip: x86/core] x86/asm-offsets: Export certain 'struct cpuinfo_x86' fields for 64-bit asm use too tip-bot2 for Ard Biesheuvel
2025-05-14 10:42 ` [PATCH v3 4/7] x86/boot: Set 5-level paging CPU cap before entering C code Ard Biesheuvel
2025-05-15  8:00   ` Kirill A. Shutemov
2025-05-15  9:43     ` Ard Biesheuvel
2025-05-15 11:05       ` Kirill A. Shutemov
2025-05-14 10:42 ` [PATCH v3 5/7] x86/boot: Drop the early variant of pgtable_l5_enabled() Ard Biesheuvel
2025-05-14 10:42 ` [PATCH v3 6/7] x86/boot: Drop 5-level paging related variables and early updates Ard Biesheuvel
2025-05-14 10:42 ` Ard Biesheuvel [this message]

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