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From: Ingo Molnar <mingo@kernel.org>
To: Ard Biesheuvel <ardb+git@google.com>
Cc: linux-kernel@vger.kernel.org, x86@kernel.org,
	Ard Biesheuvel <ardb@kernel.org>,
	Linus Torvalds <torvalds@linux-foundation.org>,
	Brian Gerst <brgerst@gmail.com>
Subject: Re: [PATCH v3 2/7] x86/cpu: Allow caps to be set arbitrarily early
Date: Thu, 15 May 2025 08:56:59 +0200	[thread overview]
Message-ID: <aCWQOzCla7i__iEl@gmail.com> (raw)
In-Reply-To: <20250514104242.1275040-11-ardb+git@google.com>


* Ard Biesheuvel <ardb+git@google.com> wrote:

> From: Ard Biesheuvel <ardb@kernel.org>
> 
> cpu_feature_enabled() uses a ternary alternative, where the late variant
> is based on code patching and the early variant accesses the capability
> field in boot_cpu_data directly.
> 
> This allows cpu_feature_enabled() to be called quite early, but it still
> requires that the CPU feature detection code runs before being able to
> rely on the return value of cpu_feature_enabled().
> 
> This is a problem for the implementation of pgtable_l5_enabled(), which
> is based on cpu_feature_enabled(X86_FEATURE_5LEVEL_PAGING), and may be
> called extremely early. Currently, there is a hacky workaround where
> some source files that may execute before (but also after) CPU feature
> detection have a different version of pgtable_l5_enabled(), based on the
> USE_EARLY_PGTABLE_L5 preprocessor macro.
> 
> Instead, let's make it possible to set CPU feature arbitrarily early, so
> that the X86_FEATURE_5LEVEL_PAGING capability can be set before even
> entering C code.
> 
> This involves relying on static initialization of boot_cpu_data and the
> cpu_caps_set/cpu_caps_cleared arrays, so they all need to reside in
> .data. This ensures that they won't be cleared along with the rest of
> BSS.
> 
> Note that forcing a capability involves setting it in both
> boot_cpu_data.x86_capability[] and cpu_caps_set[].
> 
> Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
> ---
>  arch/x86/kernel/cpu/common.c | 9 +++------
>  1 file changed, 3 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> index 6f7827015834..f6f206743d6a 100644
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -704,8 +704,8 @@ static const char *table_lookup_model(struct cpuinfo_x86 *c)
>  }
>  
>  /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
> -__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
> -__u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
> +__u32 __read_mostly cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
> +__u32 __read_mostly cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));

This change is not mentioned in the changelog AFAICS, but it should be 
in a separate patch anyway.

Thanks,

	Ingo

  reply	other threads:[~2025-05-15  6:57 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-14 10:42 [PATCH v3 0/7] x86: Robustify pgtable_l5_enabled() Ard Biesheuvel
2025-05-14 10:42 ` [PATCH v3 1/7] x86/cpu: Use a new feature flag for 5 level paging Ard Biesheuvel
2025-05-15  7:06   ` Ingo Molnar
2025-05-15  7:45   ` Ingo Molnar
2025-05-15  8:07     ` Kirill A. Shutemov
2025-05-15  8:22       ` Ingo Molnar
2025-05-15 10:12     ` Ard Biesheuvel
2025-05-15 23:24       ` Sean Christopherson
2025-05-16  8:31         ` Ard Biesheuvel
2025-05-15  9:51   ` Borislav Petkov
2025-05-15 10:17     ` Ard Biesheuvel
2025-05-15 10:39       ` Borislav Petkov
2025-05-15 10:57         ` Ard Biesheuvel
2025-05-15 13:11   ` Borislav Petkov
2025-05-15 13:33     ` Ard Biesheuvel
2025-05-17 16:59       ` David Laight
2025-05-15 18:20     ` Shivank Garg
2025-05-15 19:11       ` Borislav Petkov
2025-05-16  9:17         ` Kirill A. Shutemov
2025-05-14 10:42 ` [PATCH v3 2/7] x86/cpu: Allow caps to be set arbitrarily early Ard Biesheuvel
2025-05-15  6:56   ` Ingo Molnar [this message]
2025-05-15  7:50     ` Ingo Molnar
2025-05-15  7:55     ` Kirill A. Shutemov
2025-05-15  8:18       ` Ingo Molnar
2025-05-15  9:45         ` Ard Biesheuvel
2025-05-15 12:08           ` Ingo Molnar
2025-05-14 10:42 ` [PATCH v3 3/7] x86/asm-offsets: Export struct cpuinfo_x86 layout for asm use Ard Biesheuvel
2025-05-15  7:10   ` Ingo Molnar
2025-05-15  7:58   ` [tip: x86/core] x86/asm-offsets: Export certain 'struct cpuinfo_x86' fields for 64-bit asm use too tip-bot2 for Ard Biesheuvel
2025-05-14 10:42 ` [PATCH v3 4/7] x86/boot: Set 5-level paging CPU cap before entering C code Ard Biesheuvel
2025-05-15  8:00   ` Kirill A. Shutemov
2025-05-15  9:43     ` Ard Biesheuvel
2025-05-15 11:05       ` Kirill A. Shutemov
2025-05-14 10:42 ` [PATCH v3 5/7] x86/boot: Drop the early variant of pgtable_l5_enabled() Ard Biesheuvel
2025-05-14 10:42 ` [PATCH v3 6/7] x86/boot: Drop 5-level paging related variables and early updates Ard Biesheuvel
2025-05-14 10:42 ` [PATCH v3 7/7] x86/cpu: Make CPU capability overrides __ro_after_init Ard Biesheuvel

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