From: Ingo Molnar <mingo@kernel.org>
To: Ard Biesheuvel <ardb+git@google.com>
Cc: linux-kernel@vger.kernel.org, x86@kernel.org,
Ard Biesheuvel <ardb@kernel.org>,
Linus Torvalds <torvalds@linux-foundation.org>,
Brian Gerst <brgerst@gmail.com>
Subject: Re: [PATCH v3 1/7] x86/cpu: Use a new feature flag for 5 level paging
Date: Thu, 15 May 2025 09:06:47 +0200 [thread overview]
Message-ID: <aCWSh3P3RgoEkhqO@gmail.com> (raw)
In-Reply-To: <20250514104242.1275040-10-ardb+git@google.com>
* Ard Biesheuvel <ardb+git@google.com> wrote:
> From: Ard Biesheuvel <ardb@kernel.org>
>
> Currently, the LA57 CPU feature flag is taken to mean two different
> things at once:
> - whether the CPU implements the LA57 extension, and is therefore
> capable of supporting 5 level paging;
> - whether 5 level paging is currently in use.
>
> This means the LA57 capability of the hardware is hidden when a LA57
> capable CPU is forced to run with 4 levels of paging. It also means the
> the ordinary CPU capability detection code will happily set the LA57
> capability and it needs to be cleared explicitly afterwards to avoid
> inconsistencies.
>
> Separate the two so that the CPU hardware capability can be identified
> unambigously in all cases.
>
> To avoid breaking existing users that might assume that 5 level paging
> is being used when the "la57" string is visible in /proc/cpuinfo,
> repurpose that string to mean that 5-level paging is in use, and add a
> new string la57_capable to indicate that the CPU feature is implemented
> by the hardware.
So the new string ended up being "la57_hw", not "la57_capable". :-)
> -#define X86_FEATURE_LA57 (16*32+16) /* "la57" 5-level page tables */
> +#define X86_FEATURE_LA57 (16*32+16) /* "la57_hw" 5-level page tables */
I fixed the changelog and kept la57_hw.
BTW., I too was considering these variants for the new flag:
la57_support
la57_cap
la57_capable
- These are easy to confuse with 5-level paging software
support in the kernel, ie. the name doesn't sufficiently
disambiguate that this flag is about hardware support.
la57_cpu
- While this makes it clear that it's about the CPU, the _cpu
postfix often denotes something related to a specific CPU,
so it's a tiny bit confusing in this context.
... and each had disadvantages, as listed, and "la57_hw" seemed the
least ambiguous in this context.
Thanks,
Ingo
next prev parent reply other threads:[~2025-05-15 7:06 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-14 10:42 [PATCH v3 0/7] x86: Robustify pgtable_l5_enabled() Ard Biesheuvel
2025-05-14 10:42 ` [PATCH v3 1/7] x86/cpu: Use a new feature flag for 5 level paging Ard Biesheuvel
2025-05-15 7:06 ` Ingo Molnar [this message]
2025-05-15 7:45 ` Ingo Molnar
2025-05-15 8:07 ` Kirill A. Shutemov
2025-05-15 8:22 ` Ingo Molnar
2025-05-15 10:12 ` Ard Biesheuvel
2025-05-15 23:24 ` Sean Christopherson
2025-05-16 8:31 ` Ard Biesheuvel
2025-05-15 9:51 ` Borislav Petkov
2025-05-15 10:17 ` Ard Biesheuvel
2025-05-15 10:39 ` Borislav Petkov
2025-05-15 10:57 ` Ard Biesheuvel
2025-05-15 13:11 ` Borislav Petkov
2025-05-15 13:33 ` Ard Biesheuvel
2025-05-17 16:59 ` David Laight
2025-05-15 18:20 ` Shivank Garg
2025-05-15 19:11 ` Borislav Petkov
2025-05-16 9:17 ` Kirill A. Shutemov
2025-05-14 10:42 ` [PATCH v3 2/7] x86/cpu: Allow caps to be set arbitrarily early Ard Biesheuvel
2025-05-15 6:56 ` Ingo Molnar
2025-05-15 7:50 ` Ingo Molnar
2025-05-15 7:55 ` Kirill A. Shutemov
2025-05-15 8:18 ` Ingo Molnar
2025-05-15 9:45 ` Ard Biesheuvel
2025-05-15 12:08 ` Ingo Molnar
2025-05-14 10:42 ` [PATCH v3 3/7] x86/asm-offsets: Export struct cpuinfo_x86 layout for asm use Ard Biesheuvel
2025-05-15 7:10 ` Ingo Molnar
2025-05-15 7:58 ` [tip: x86/core] x86/asm-offsets: Export certain 'struct cpuinfo_x86' fields for 64-bit asm use too tip-bot2 for Ard Biesheuvel
2025-05-14 10:42 ` [PATCH v3 4/7] x86/boot: Set 5-level paging CPU cap before entering C code Ard Biesheuvel
2025-05-15 8:00 ` Kirill A. Shutemov
2025-05-15 9:43 ` Ard Biesheuvel
2025-05-15 11:05 ` Kirill A. Shutemov
2025-05-14 10:42 ` [PATCH v3 5/7] x86/boot: Drop the early variant of pgtable_l5_enabled() Ard Biesheuvel
2025-05-14 10:42 ` [PATCH v3 6/7] x86/boot: Drop 5-level paging related variables and early updates Ard Biesheuvel
2025-05-14 10:42 ` [PATCH v3 7/7] x86/cpu: Make CPU capability overrides __ro_after_init Ard Biesheuvel
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