Re: [PATCH v3 1/7] x86/cpu: Use a new feature flag for 5 level paging

[Borislav Petkov <bp@alien8.de>]

On Thu, May 15, 2025 at 11:50:17PM +0530, Shivank Garg wrote:
> I've re-tested the performance concerns we discussed earlier regarding 5-level paging.
> Recent tests on a current kernel don't show any performance issues:
> 
> AMD EPYC Zen 5 (SMT enabled).
> Linux HEAD 6.15.0-rc6+ 088d13246a46
> 
> lmbench/lat_pagefault:
> numactl --membind=1 --cpunodebind=1 bin/x86_64-linux-gnu/lat_pagefault -N 100 1GB_randomfile
> 
> Output values (50 runs, Mean, 2.5 percentile and 97.5 percentile, in microseconds):
> 
> 4-level (no5lvl option)
> Mean: 0.138876
>      2.5%     97.5%
> 0.1384988 0.1392532
> 
> 4-level (CONFIG_X86_5LEVEL=n)
> Mean: 0.137958
>      2.5%     97.5%
> 0.1376473 0.1382687
> 
> 5-level
> Mean: 0.138904
>      2.5%     97.5%
> 0.1384789 0.1393291
> 
> After repeating the experiments a few times, the observed difference(~1%) in mean values
> is under noise levels.
> I think these results address the performance concerns previously raised[1]. I don't
> foresee any issues in proceeding with the 5-level paging implementation
> simplification efforts[2].
> 
> [1] https://lore.kernel.org/all/80734605-1926-4ac7-9c63-006fe3ea6b6a@amd.com
> [2] https://lore.kernel.org/all/20240621164406.256314-1-kirill.shutemov@linux.intel.com

I guess Kirill could dust off his patchset from [2] and that would get rid of
CONFIG_X86_5LEVEL and likely simplify that aspect considerably...

I'd say.

And then Ard's patches would get even simpler...

Thx.

-- 
Regards/Gruss,
    Boris.

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