From: Terry Bowman <terry.bowman@amd.com>
To: <PradeepVineshReddy.Kodamati@amd.com>, <dave@stgolabs.net>,
<jonathan.cameron@huawei.com>, <dave.jiang@intel.com>,
<alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <dan.j.williams@intel.com>,
<bhelgaas@google.com>, <bp@alien8.de>, <ming.li@zohomail.com>,
<shiju.jose@huawei.com>, <dan.carpenter@linaro.org>,
<Smita.KoralahalliChannabasappa@amd.com>,
<kobayashi.da-06@fujitsu.com>, <terry.bowman@amd.com>,
<yanfei.xu@intel.com>, <rrichter@amd.com>, <peterz@infradead.org>,
<colyli@suse.de>, <uaisheng.ye@intel.com>,
<fabio.m.de.francesco@linux.intel.com>,
<ilpo.jarvinen@linux.intel.com>, <yazen.ghannam@amd.com>,
<linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-pci@vger.kernel.org>
Subject: [PATCH v9 02/16] PCI/AER: Report CXL or PCIe bus error type in trace logging
Date: Tue, 3 Jun 2025 12:22:25 -0500 [thread overview]
Message-ID: <20250603172239.159260-3-terry.bowman@amd.com> (raw)
In-Reply-To: <20250603172239.159260-1-terry.bowman@amd.com>
The AER service driver and aer_event tracing currently log 'PCIe Bus Type'
for all errors. Update the driver and aer_event tracing to log 'CXL Bus
Type' for CXL device errors.
This requires the AER can identify and distinguish between PCIe errors and
CXL errors.
Introduce boolean 'is_cxl' to 'struct aer_err_info'. Add assignment in
aer_get_device_error_info() and pci_print_aer().
Update the aer_event trace routine to accept a bus type string parameter.
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
---
drivers/pci/pci.h | 6 ++++++
drivers/pci/pcie/aer.c | 18 ++++++++++++------
include/ras/ras_event.h | 9 ++++++---
3 files changed, 24 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index b81e99cd4b62..d6296500b004 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -588,6 +588,7 @@ static inline bool pci_dev_test_and_set_removed(struct pci_dev *dev)
struct aer_err_info {
struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
int error_dev_num;
+ bool is_cxl;
unsigned int id:16;
@@ -604,6 +605,11 @@ struct aer_err_info {
struct pcie_tlp_log tlp; /* TLP Header */
};
+static inline const char *aer_err_bus(struct aer_err_info *info)
+{
+ return info->is_cxl ? "CXL" : "PCIe";
+}
+
int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index a1cf8c7ef628..adb4b1123b9b 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -698,13 +698,14 @@ static void __aer_print_error(struct pci_dev *dev,
void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
{
+ const char *bus_type = aer_err_bus(info);
int layer, agent;
int id = pci_dev_id(dev);
const char *level;
if (!info->status) {
- pci_err(dev, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n",
- aer_error_severity_string[info->severity]);
+ pci_err(dev, "%s Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n",
+ bus_type, aer_error_severity_string[info->severity]);
goto out;
}
@@ -713,8 +714,8 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
level = (info->severity == AER_CORRECTABLE) ? KERN_WARNING : KERN_ERR;
- aer_printk(level, dev, "PCIe Bus Error: severity=%s, type=%s, (%s)\n",
- aer_error_severity_string[info->severity],
+ aer_printk(level, dev, "%s Bus Error: severity=%s, type=%s, (%s)\n",
+ bus_type, aer_error_severity_string[info->severity],
aer_error_layer[layer], aer_agent_string[agent]);
aer_printk(level, dev, " device [%04x:%04x] error status/mask=%08x/%08x\n",
@@ -729,7 +730,7 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
if (info->id && info->error_dev_num > 1 && info->id == id)
pci_err(dev, " Error of this Agent is reported first\n");
- trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask),
+ trace_aer_event(dev_name(&dev->dev), bus_type, (info->status & ~info->mask),
info->severity, info->tlp_header_valid, &info->tlp);
}
@@ -763,6 +764,7 @@ EXPORT_SYMBOL_GPL(cper_severity_to_aer);
void pci_print_aer(struct pci_dev *dev, int aer_severity,
struct aer_capability_regs *aer)
{
+ const char *bus_type;
int layer, agent, tlp_header_valid = 0;
u32 status, mask;
struct aer_err_info info;
@@ -784,6 +786,9 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity,
info.status = status;
info.mask = mask;
info.first_error = PCI_ERR_CAP_FEP(aer->cap_control);
+ info.is_cxl = pcie_is_cxl(dev);
+
+ bus_type = aer_err_bus(&info);
pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask);
__aer_print_error(dev, &info);
@@ -797,7 +802,7 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity,
if (tlp_header_valid)
pcie_print_tlp_log(dev, &aer->header_log, dev_fmt(" "));
- trace_aer_event(dev_name(&dev->dev), (status & ~mask),
+ trace_aer_event(dev_name(&dev->dev), bus_type, (status & ~mask),
aer_severity, tlp_header_valid, &aer->header_log);
}
EXPORT_SYMBOL_NS_GPL(pci_print_aer, "CXL");
@@ -1215,6 +1220,7 @@ int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info)
/* Must reset in this function */
info->status = 0;
info->tlp_header_valid = 0;
+ info->is_cxl = pcie_is_cxl(dev);
/* The device might not support AER */
if (!aer)
diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h
index 14c9f943d53f..080829d59c36 100644
--- a/include/ras/ras_event.h
+++ b/include/ras/ras_event.h
@@ -297,15 +297,17 @@ TRACE_EVENT(non_standard_event,
TRACE_EVENT(aer_event,
TP_PROTO(const char *dev_name,
+ const char *bus_type,
const u32 status,
const u8 severity,
const u8 tlp_header_valid,
struct pcie_tlp_log *tlp),
- TP_ARGS(dev_name, status, severity, tlp_header_valid, tlp),
+ TP_ARGS(dev_name, bus_type, status, severity, tlp_header_valid, tlp),
TP_STRUCT__entry(
__string( dev_name, dev_name )
+ __string( bus_type, bus_type )
__field( u32, status )
__field( u8, severity )
__field( u8, tlp_header_valid)
@@ -314,6 +316,7 @@ TRACE_EVENT(aer_event,
TP_fast_assign(
__assign_str(dev_name);
+ __assign_str(bus_type);
__entry->status = status;
__entry->severity = severity;
__entry->tlp_header_valid = tlp_header_valid;
@@ -325,8 +328,8 @@ TRACE_EVENT(aer_event,
}
),
- TP_printk("%s PCIe Bus Error: severity=%s, %s, TLP Header=%s\n",
- __get_str(dev_name),
+ TP_printk("%s %s Bus Error: severity=%s, %s, TLP Header=%s\n",
+ __get_str(dev_name), __get_str(bus_type),
__entry->severity == AER_CORRECTABLE ? "Corrected" :
__entry->severity == AER_FATAL ?
"Fatal" : "Uncorrected, non-fatal",
--
2.34.1
next prev parent reply other threads:[~2025-06-03 17:23 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-03 17:22 [PATCH v9 00/16] Enable CXL PCIe port protocol error handling and logging Terry Bowman
2025-06-03 17:22 ` [PATCH v9 01/16] PCI/CXL: Add pcie_is_cxl() Terry Bowman
2025-06-04 19:06 ` Sathyanarayanan Kuppuswamy
2025-06-04 19:18 ` Bowman, Terry
2025-06-05 23:24 ` Dave Jiang
2025-06-03 17:22 ` Terry Bowman [this message]
2025-06-03 22:02 ` [PATCH v9 02/16] PCI/AER: Report CXL or PCIe bus error type in trace logging Sathyanarayanan Kuppuswamy
2025-06-04 14:32 ` Bowman, Terry
2025-06-04 19:24 ` Sathyanarayanan Kuppuswamy
2025-06-04 21:30 ` Bowman, Terry
2025-06-05 23:28 ` Dave Jiang
2025-06-03 17:22 ` [PATCH v9 03/16] CXL/AER: Introduce kfifo for forwarding CXL errors Terry Bowman
2025-06-04 6:01 ` Dan Carpenter
2025-06-04 14:37 ` Bowman, Terry
2025-06-04 17:24 ` Dan Carpenter
2025-06-04 19:21 ` Bowman, Terry
2025-06-04 22:50 ` Sathyanarayanan Kuppuswamy
2025-06-05 14:04 ` Bowman, Terry
2025-06-06 0:27 ` Dave Jiang
2025-06-06 14:27 ` Bowman, Terry
2025-06-06 14:36 ` Dave Jiang
2025-06-12 11:04 ` Jonathan Cameron
2025-06-12 14:29 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 04/16] PCI/AER: Dequeue forwarded CXL error Terry Bowman
2025-06-04 6:05 ` Dan Carpenter
2025-06-04 14:38 ` Bowman, Terry
2025-06-04 23:58 ` Sathyanarayanan Kuppuswamy
2025-06-06 15:57 ` Dave Jiang
2025-06-06 18:14 ` Bowman, Terry
2025-06-06 22:43 ` Dave Jiang
2025-06-09 19:57 ` Bowman, Terry
2025-06-09 20:34 ` Dave Jiang
2025-06-12 11:17 ` Jonathan Cameron
2025-06-06 21:08 ` Bowman, Terry
2025-06-06 23:15 ` Bowman, Terry
2025-06-09 20:17 ` Dave Jiang
2025-06-10 4:15 ` Lukas Wunner
2025-06-10 18:07 ` Bowman, Terry
2025-06-10 21:20 ` Bowman, Terry
2025-06-11 4:38 ` Lukas Wunner
2025-06-17 16:08 ` Dave Jiang
2025-06-17 18:20 ` Robert Richter
2025-06-12 11:36 ` Jonathan Cameron
2025-06-12 18:35 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 05/16] CXL/PCI: Introduce CXL uncorrectable protocol error recovery Terry Bowman
2025-06-05 15:14 ` Sathyanarayanan Kuppuswamy
2025-06-05 16:01 ` Bowman, Terry
2025-06-06 16:45 ` Dave Jiang
2025-06-06 18:16 ` Bowman, Terry
2025-06-12 16:06 ` Jonathan Cameron
2025-06-12 16:29 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 06/16] cxl/pci: Move RAS initialization to cxl_port driver Terry Bowman
2025-06-06 17:04 ` Dave Jiang
2025-06-06 18:17 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 07/16] cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers Terry Bowman
2025-06-03 17:22 ` [PATCH v9 08/16] cxl/pci: Update RAS handler interfaces to also support CXL Ports Terry Bowman
2025-06-05 16:42 ` Sathyanarayanan Kuppuswamy
2025-06-03 17:22 ` [PATCH v9 09/16] cxl/pci: Log message if RAS registers are unmapped Terry Bowman
2025-06-05 16:42 ` Sathyanarayanan Kuppuswamy
2025-06-06 17:27 ` Dave Jiang
2025-06-03 17:22 ` [PATCH v9 10/16] cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports Terry Bowman
2025-06-05 16:49 ` Sathyanarayanan Kuppuswamy
2025-06-06 9:08 ` Shiju Jose
2025-06-06 14:41 ` Bowman, Terry
2025-06-06 15:24 ` Bowman, Terry
2025-06-12 16:25 ` Jonathan Cameron
2025-06-03 17:22 ` [PATCH v9 11/16] cxl/pci: Update __cxl_handle_cor_ras() to return early if no RAS errors Terry Bowman
2025-06-05 18:37 ` Sathyanarayanan Kuppuswamy
2025-06-06 20:30 ` Dave Jiang
2025-06-06 20:55 ` Bowman, Terry
2025-06-06 22:38 ` Dave Jiang
2025-06-12 16:46 ` Jonathan Cameron
2025-06-16 20:30 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 12/16] cxl/pci: Introduce CXL Endpoint protocol error handlers Terry Bowman
2025-06-06 0:22 ` Sathyanarayanan Kuppuswamy
2025-06-12 16:55 ` Jonathan Cameron
2025-06-03 17:22 ` [PATCH v9 13/16] cxl/pci: Introduce CXL Port " Terry Bowman
2025-06-06 0:50 ` Sathyanarayanan Kuppuswamy
2025-06-12 17:14 ` Jonathan Cameron
2025-06-16 22:17 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 14/16] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Terry Bowman
2025-06-06 0:50 ` Sathyanarayanan Kuppuswamy
2025-06-12 17:16 ` Jonathan Cameron
2025-06-03 17:22 ` [PATCH v9 15/16] CXL/PCI: Enable CXL protocol errors during CXL Port probe Terry Bowman
2025-06-06 0:51 ` Sathyanarayanan Kuppuswamy
2025-06-03 17:22 ` [PATCH v9 16/16] CXL/PCI: Disable CXL protocol error interrupts during CXL Port cleanup Terry Bowman
2025-06-06 0:52 ` Sathyanarayanan Kuppuswamy
2025-06-06 13:51 ` Bowman, Terry
2025-06-06 22:59 ` Dave Jiang
2025-06-12 17:19 ` Jonathan Cameron
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