From: "Bowman, Terry" <terry.bowman@amd.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: PradeepVineshReddy.Kodamati@amd.com, dave@stgolabs.net,
dave.jiang@intel.com, alison.schofield@intel.com,
vishal.l.verma@intel.com, ira.weiny@intel.com,
dan.j.williams@intel.com, bhelgaas@google.com, bp@alien8.de,
ming.li@zohomail.com, shiju.jose@huawei.com,
dan.carpenter@linaro.org, Smita.KoralahalliChannabasappa@amd.com,
kobayashi.da-06@fujitsu.com, rrichter@amd.com,
peterz@infradead.org, fabio.m.de.francesco@linux.intel.com,
ilpo.jarvinen@linux.intel.com, yazen.ghannam@amd.com,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: Re: [PATCH v9 04/16] PCI/AER: Dequeue forwarded CXL error
Date: Thu, 12 Jun 2025 13:35:53 -0500 [thread overview]
Message-ID: <c4c29333-989b-4fe6-93fa-3f880d3e9b1c@amd.com> (raw)
In-Reply-To: <20250612123650.0000321b@huawei.com>
On 6/12/2025 6:36 AM, Jonathan Cameron wrote:
> On Tue, 3 Jun 2025 12:22:27 -0500
> Terry Bowman <terry.bowman@amd.com> wrote:
>
>> The AER driver is now designed to forward CXL protocol errors to the CXL
>> driver. Update the CXL driver with functionality to dequeue the forwarded
>> CXL error from the kfifo. Also, update the CXL driver to begin the protocol
>> error handling processing using the work received from the FIFO.
>>
>> Introduce function cxl_prot_err_work_fn() to dequeue work forwarded by the
>> AER service driver. This will begin the CXL protocol error processing
>> with a call to cxl_handle_prot_error().
>>
>> Update cxl/core/ras.c by adding cxl_rch_handle_error_iter() that was
>> previously in the AER driver.
>>
>> Introduce sbdf_to_pci() to take the SBDF values from 'struct cxl_prot_error_info'
>> and use in discovering the erring PCI device. Make scope based reference
>> increments/decrements for the discovered PCI device and the associated
>> CXL device.
>>
>> Implement cxl_handle_prot_error() to differentiate between Restricted CXL
>> Host (RCH) protocol errors and CXL virtual host (VH) protocol errors.
>> RCH errors will be processed with a call to walk the associated Root
>> Complex Event Collector's (RCEC) secondary bus looking for the Root Complex
>> Integrated Endpoint (RCiEP) to handle the RCH error. Export pcie_walk_rcec()
>> so the CXL driver can walk the RCEC's downstream bus, searching for
>> the RCiEP.
>>
>> VH correctable error (CE) processing will call the CXL CE handler. VH
>> uncorrectable errors (UCE) will call cxl_do_recovery(), implemented as a
>> stub for now and to be updated in future patch. Export pci_aer_clean_fatal_status()
>> and pci_clean_device_status() used to clean up AER status after handling.
>>
>> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Hopefully I haven't duplicated existing feedback. A few more minor things
> inline.
>
>> +
>> +static struct pci_dev *sbdf_to_pci(struct cxl_prot_error_info *err_info)
> That's an odd function name as the sbdf is buried.
> Unless it's going to get a lot of use, I'd just put the lookup
> inline and not have a 'hard to name' function. With other suggested
> changes you only need (at where this is currently called)
> struct pci_dev *pdev __free(pci_dev_put) =
> pci_get_domain_bus_and_slot(err_info->segment, err_info->bus,
> err_info->devfn);
Ok. I'll remove the helper and add inline.
>> +{
>> + unsigned int devfn = PCI_DEVFN(err_info->device,
>> + err_info->function);
> This makes me wonder if you should have just use devfn inside the err_info.
> Is there a good reason to split them up before storing them?
>
> IIRC ARI makes a mess anyway of their meaning when separate.
Agreed. I'll keep devfn together.
>> + struct pci_dev *pdev __free(pci_dev_put) =
>> + pci_get_domain_bus_and_slot(err_info->segment,
>> + err_info->bus,
>> + devfn);
>> + return pdev;
>> +}
>> +
>> +static void cxl_handle_prot_error(struct cxl_prot_error_info *err_info)
>> +{
>> + struct pci_dev *pdev __free(pci_dev_put) = pci_dev_get(sbdf_to_pci(err_info));
>> +
>> + if (!pdev) {
>> + pr_err("Failed to find the CXL device\n");
>> + return;
>> + }
>> +
>> + /*
>> + * Internal errors of an RCEC indicate an AER error in an
>> + * RCH's downstream port. Check and handle them in the CXL.mem
>> + * device driver.
>> + */
>> + if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_EC)
>> + return pcie_walk_rcec(pdev, cxl_rch_handle_error_iter, err_info);
>> +
>> + if (err_info->severity == AER_CORRECTABLE) {
>> + int aer = pdev->aer_cap;
>> + struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
>> + struct device *dev __free(put_device) = get_device(&cxlds->cxlmd->dev);
>> +
>> + if (aer)
>> + pci_clear_and_set_config_dword(pdev,
>> + aer + PCI_ERR_COR_STATUS,
>> + 0, PCI_ERR_COR_INTERNAL);
>> +
>> + cxl_cor_error_detected(pdev);
>> +
>> + pcie_clear_device_status(pdev);
>> + } else {
>> + cxl_do_recovery(pdev);
>> + }
>> +}
>> +
>> static void cxl_prot_err_work_fn(struct work_struct *work)
>> {
>> + struct cxl_prot_err_work_data wd;
>> +
>> + while (cxl_prot_err_kfifo_get(&wd)) {
>> + struct cxl_prot_error_info *err_info = &wd.err_info;
>> +
>> + cxl_handle_prot_error(err_info);
> I'm not seeing value in the local variable.
> Ignore if this code changes later and that makes more sense!
It can be removed and simplified.
Thanks for reviewing.
-Terry
>> + }
>> }
>>
>> #else
next prev parent reply other threads:[~2025-06-12 18:36 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-03 17:22 [PATCH v9 00/16] Enable CXL PCIe port protocol error handling and logging Terry Bowman
2025-06-03 17:22 ` [PATCH v9 01/16] PCI/CXL: Add pcie_is_cxl() Terry Bowman
2025-06-04 19:06 ` Sathyanarayanan Kuppuswamy
2025-06-04 19:18 ` Bowman, Terry
2025-06-05 23:24 ` Dave Jiang
2025-06-03 17:22 ` [PATCH v9 02/16] PCI/AER: Report CXL or PCIe bus error type in trace logging Terry Bowman
2025-06-03 22:02 ` Sathyanarayanan Kuppuswamy
2025-06-04 14:32 ` Bowman, Terry
2025-06-04 19:24 ` Sathyanarayanan Kuppuswamy
2025-06-04 21:30 ` Bowman, Terry
2025-06-05 23:28 ` Dave Jiang
2025-06-03 17:22 ` [PATCH v9 03/16] CXL/AER: Introduce kfifo for forwarding CXL errors Terry Bowman
2025-06-04 6:01 ` Dan Carpenter
2025-06-04 14:37 ` Bowman, Terry
2025-06-04 17:24 ` Dan Carpenter
2025-06-04 19:21 ` Bowman, Terry
2025-06-04 22:50 ` Sathyanarayanan Kuppuswamy
2025-06-05 14:04 ` Bowman, Terry
2025-06-06 0:27 ` Dave Jiang
2025-06-06 14:27 ` Bowman, Terry
2025-06-06 14:36 ` Dave Jiang
2025-06-12 11:04 ` Jonathan Cameron
2025-06-12 14:29 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 04/16] PCI/AER: Dequeue forwarded CXL error Terry Bowman
2025-06-04 6:05 ` Dan Carpenter
2025-06-04 14:38 ` Bowman, Terry
2025-06-04 23:58 ` Sathyanarayanan Kuppuswamy
2025-06-06 15:57 ` Dave Jiang
2025-06-06 18:14 ` Bowman, Terry
2025-06-06 22:43 ` Dave Jiang
2025-06-09 19:57 ` Bowman, Terry
2025-06-09 20:34 ` Dave Jiang
2025-06-12 11:17 ` Jonathan Cameron
2025-06-06 21:08 ` Bowman, Terry
2025-06-06 23:15 ` Bowman, Terry
2025-06-09 20:17 ` Dave Jiang
2025-06-10 4:15 ` Lukas Wunner
2025-06-10 18:07 ` Bowman, Terry
2025-06-10 21:20 ` Bowman, Terry
2025-06-11 4:38 ` Lukas Wunner
2025-06-17 16:08 ` Dave Jiang
2025-06-17 18:20 ` Robert Richter
2025-06-12 11:36 ` Jonathan Cameron
2025-06-12 18:35 ` Bowman, Terry [this message]
2025-06-03 17:22 ` [PATCH v9 05/16] CXL/PCI: Introduce CXL uncorrectable protocol error recovery Terry Bowman
2025-06-05 15:14 ` Sathyanarayanan Kuppuswamy
2025-06-05 16:01 ` Bowman, Terry
2025-06-06 16:45 ` Dave Jiang
2025-06-06 18:16 ` Bowman, Terry
2025-06-12 16:06 ` Jonathan Cameron
2025-06-12 16:29 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 06/16] cxl/pci: Move RAS initialization to cxl_port driver Terry Bowman
2025-06-06 17:04 ` Dave Jiang
2025-06-06 18:17 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 07/16] cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers Terry Bowman
2025-06-03 17:22 ` [PATCH v9 08/16] cxl/pci: Update RAS handler interfaces to also support CXL Ports Terry Bowman
2025-06-05 16:42 ` Sathyanarayanan Kuppuswamy
2025-06-03 17:22 ` [PATCH v9 09/16] cxl/pci: Log message if RAS registers are unmapped Terry Bowman
2025-06-05 16:42 ` Sathyanarayanan Kuppuswamy
2025-06-06 17:27 ` Dave Jiang
2025-06-03 17:22 ` [PATCH v9 10/16] cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports Terry Bowman
2025-06-05 16:49 ` Sathyanarayanan Kuppuswamy
2025-06-06 9:08 ` Shiju Jose
2025-06-06 14:41 ` Bowman, Terry
2025-06-06 15:24 ` Bowman, Terry
2025-06-12 16:25 ` Jonathan Cameron
2025-06-03 17:22 ` [PATCH v9 11/16] cxl/pci: Update __cxl_handle_cor_ras() to return early if no RAS errors Terry Bowman
2025-06-05 18:37 ` Sathyanarayanan Kuppuswamy
2025-06-06 20:30 ` Dave Jiang
2025-06-06 20:55 ` Bowman, Terry
2025-06-06 22:38 ` Dave Jiang
2025-06-12 16:46 ` Jonathan Cameron
2025-06-16 20:30 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 12/16] cxl/pci: Introduce CXL Endpoint protocol error handlers Terry Bowman
2025-06-06 0:22 ` Sathyanarayanan Kuppuswamy
2025-06-12 16:55 ` Jonathan Cameron
2025-06-03 17:22 ` [PATCH v9 13/16] cxl/pci: Introduce CXL Port " Terry Bowman
2025-06-06 0:50 ` Sathyanarayanan Kuppuswamy
2025-06-12 17:14 ` Jonathan Cameron
2025-06-16 22:17 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 14/16] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Terry Bowman
2025-06-06 0:50 ` Sathyanarayanan Kuppuswamy
2025-06-12 17:16 ` Jonathan Cameron
2025-06-03 17:22 ` [PATCH v9 15/16] CXL/PCI: Enable CXL protocol errors during CXL Port probe Terry Bowman
2025-06-06 0:51 ` Sathyanarayanan Kuppuswamy
2025-06-03 17:22 ` [PATCH v9 16/16] CXL/PCI: Disable CXL protocol error interrupts during CXL Port cleanup Terry Bowman
2025-06-06 0:52 ` Sathyanarayanan Kuppuswamy
2025-06-06 13:51 ` Bowman, Terry
2025-06-06 22:59 ` Dave Jiang
2025-06-12 17:19 ` Jonathan Cameron
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=c4c29333-989b-4fe6-93fa-3f880d3e9b1c@amd.com \
--to=terry.bowman@amd.com \
--cc=Jonathan.Cameron@huawei.com \
--cc=PradeepVineshReddy.Kodamati@amd.com \
--cc=Smita.KoralahalliChannabasappa@amd.com \
--cc=alison.schofield@intel.com \
--cc=bhelgaas@google.com \
--cc=bp@alien8.de \
--cc=dan.carpenter@linaro.org \
--cc=dan.j.williams@intel.com \
--cc=dave.jiang@intel.com \
--cc=dave@stgolabs.net \
--cc=fabio.m.de.francesco@linux.intel.com \
--cc=ilpo.jarvinen@linux.intel.com \
--cc=ira.weiny@intel.com \
--cc=kobayashi.da-06@fujitsu.com \
--cc=linux-cxl@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=ming.li@zohomail.com \
--cc=peterz@infradead.org \
--cc=rrichter@amd.com \
--cc=shiju.jose@huawei.com \
--cc=vishal.l.verma@intel.com \
--cc=yazen.ghannam@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®