From: "Bowman, Terry" <terry.bowman@amd.com>
To: Shiju Jose <shiju.jose@huawei.com>,
"PradeepVineshReddy.Kodamati@amd.com"
<PradeepVineshReddy.Kodamati@amd.com>,
"dave@stgolabs.net" <dave@stgolabs.net>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
"dave.jiang@intel.com" <dave.jiang@intel.com>,
"alison.schofield@intel.com" <alison.schofield@intel.com>,
"vishal.l.verma@intel.com" <vishal.l.verma@intel.com>,
"ira.weiny@intel.com" <ira.weiny@intel.com>,
"dan.j.williams@intel.com" <dan.j.williams@intel.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"bp@alien8.de" <bp@alien8.de>,
"ming.li@zohomail.com" <ming.li@zohomail.com>,
"dan.carpenter@linaro.org" <dan.carpenter@linaro.org>,
"Smita.KoralahalliChannabasappa@amd.com"
<Smita.KoralahalliChannabasappa@amd.com>,
"kobayashi.da-06@fujitsu.com" <kobayashi.da-06@fujitsu.com>,
"yanfei.xu@intel.com" <yanfei.xu@intel.com>,
"rrichter@amd.com" <rrichter@amd.com>,
"peterz@infradead.org" <peterz@infradead.org>,
"colyli@suse.de" <colyli@suse.de>,
"uaisheng.ye@intel.com" <uaisheng.ye@intel.com>,
"fabio.m.de.francesco@linux.intel.com"
<fabio.m.de.francesco@linux.intel.com>,
"ilpo.jarvinen@linux.intel.com" <ilpo.jarvinen@linux.intel.com>,
"yazen.ghannam@amd.com" <yazen.ghannam@amd.com>,
"linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>
Subject: Re: [PATCH v9 10/16] cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports
Date: Fri, 6 Jun 2025 10:24:25 -0500 [thread overview]
Message-ID: <e319c9b2-742d-4fbf-8092-90a4f96d7980@amd.com> (raw)
In-Reply-To: <3e022f34-ad65-4caa-9321-c181bb8ae676@amd.com>
On 6/6/2025 9:41 AM, Bowman, Terry wrote:
>
> On 6/6/2025 4:08 AM, Shiju Jose wrote:
>>> -----Original Message-----
>>> From: Terry Bowman <terry.bowman@amd.com>
>>> Sent: 03 June 2025 18:23
>>> To: PradeepVineshReddy.Kodamati@amd.com; dave@stgolabs.net; Jonathan
>>> Cameron <jonathan.cameron@huawei.com>; dave.jiang@intel.com;
>>> alison.schofield@intel.com; vishal.l.verma@intel.com; ira.weiny@intel.com;
>>> dan.j.williams@intel.com; bhelgaas@google.com; bp@alien8.de;
>>> ming.li@zohomail.com; Shiju Jose <shiju.jose@huawei.com>;
>>> dan.carpenter@linaro.org; Smita.KoralahalliChannabasappa@amd.com;
>>> kobayashi.da-06@fujitsu.com; terry.bowman@amd.com; yanfei.xu@intel.com;
>>> rrichter@amd.com; peterz@infradead.org; colyli@suse.de;
>>> uaisheng.ye@intel.com; fabio.m.de.francesco@linux.intel.com;
>>> ilpo.jarvinen@linux.intel.com; yazen.ghannam@amd.com; linux-
>>> cxl@vger.kernel.org; linux-kernel@vger.kernel.org; linux-pci@vger.kernel.org
>>> Subject: [PATCH v9 10/16] cxl/pci: Unify CXL trace logging for CXL Endpoints and
>>> CXL Ports
>>>
>>> CXL currently has separate trace routines for CXL Port errors and CXL Endpoint
>>> errors. This is inconvenient for the user because they must enable
>>> 2 sets of trace routines. Make updates to the trace logging such that a single
>>> trace routine logs both CXL Endpoint and CXL Port protocol errors.
>>>
>>> Rename the 'host' field from the CXL Endpoint trace to 'parent' in the unified
>>> trace routines. 'host' does not correctly apply to CXL Port devices. Parent is more
>>> general and applies to CXL Port devices and CXL Endpoints.
>>>
>>> Add serial number parameter to the trace logging. This is used for EPs and 0 is
>>> provided for CXL port devices without a serial number.
>>>
>>> Below is output of correctable and uncorrectable protocol error logging.
>>> CXL Root Port and CXL Endpoint examples are included below.
>>>
>>> Root Port:
>>> cxl_aer_correctable_error: device=0000:0c:00.0 parent=pci0000:0c serial: 0
>>> status='CRC Threshold Hit'
>>> cxl_aer_uncorrectable_error: device=0000:0c:00.0 parent=pci0000:0c serial: 0
>>> status: 'Cache Byte Enable Parity Error' first_error: 'Cache Byte Enable Parity
>>> Error'
>>>
>>> Endpoint:
>>> cxl_aer_correctable_error: device=mem3 parent=0000:0f:00.0 serial=0
>>> status='CRC Threshold Hit'
>>> cxl_aer_uncorrectable_error: device=mem3 parent=0000:0f:00.0 serial: 0
>>> status: 'Cache Byte Enable Parity Error' first_error: 'Cache Byte Enable Parity
>>> Error'
>>>
>>> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
>>> ---
>>> drivers/cxl/core/pci.c | 18 +++++----
>>> drivers/cxl/core/ras.c | 14 ++++---
>>> drivers/cxl/core/trace.h | 84 +++++++++-------------------------------
>>> 3 files changed, 37 insertions(+), 79 deletions(-)
>>>
>>> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index
>>> 186a5a20b951..0f4c07fd64a5 100644
>>> --- a/drivers/cxl/core/pci.c
>>> +++ b/drivers/cxl/core/pci.c
>>> @@ -664,7 +664,7 @@ void read_cdat_data(struct cxl_port *port) }
>>> EXPORT_SYMBOL_NS_GPL(read_cdat_data, "CXL");
>>>
>> [...]
>>> static void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data
>>> *data) diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h index
>>> 25ebfbc1616c..8c91b0f3d165 100644
>>> --- a/drivers/cxl/core/trace.h
>>> +++ b/drivers/cxl/core/trace.h
>>> @@ -48,49 +48,22 @@
>>> { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \
>>> )
>>>
>>> -TRACE_EVENT(cxl_port_aer_uncorrectable_error,
>>> - TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl),
>>> - TP_ARGS(dev, status, fe, hl),
>>> - TP_STRUCT__entry(
>>> - __string(device, dev_name(dev))
>>> - __string(host, dev_name(dev->parent))
>>> - __field(u32, status)
>>> - __field(u32, first_error)
>>> - __array(u32, header_log, CXL_HEADERLOG_SIZE_U32)
>>> - ),
>>> - TP_fast_assign(
>>> - __assign_str(device);
>>> - __assign_str(host);
>>> - __entry->status = status;
>>> - __entry->first_error = fe;
>>> - /*
>>> - * Embed the 512B headerlog data for user app retrieval and
>>> - * parsing, but no need to print this in the trace buffer.
>>> - */
>>> - memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);
>>> - ),
>>> - TP_printk("device=%s host=%s status: '%s' first_error: '%s'",
>>> - __get_str(device), __get_str(host),
>>> - show_uc_errs(__entry->status),
>>> - show_uc_errs(__entry->first_error)
>>> - )
>>> -);
>>> -
>>> TRACE_EVENT(cxl_aer_uncorrectable_error,
>>> - TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32
>>> *hl),
>>> - TP_ARGS(cxlmd, status, fe, hl),
>>> + TP_PROTO(struct device *dev, u64 serial, u32 status, u32 fe,
>>> + u32 *hl),
>>> + TP_ARGS(dev, serial, status, fe, hl),
>>> TP_STRUCT__entry(
>>> - __string(memdev, dev_name(&cxlmd->dev))
>>> - __string(host, dev_name(cxlmd->dev.parent))
>>> + __string(name, dev_name(dev))
>>> + __string(parent, dev_name(dev->parent))
>> Hi Terry,
>>
>> As we pointed out in v8, renaming the fields "memdev" to "name" and "host" to "parent"
>> causes issues and failures in userspace rasdaemon while parsing the trace event data.
>> Additionally, we can't rename these fields in rasdaemon due to backward compatibility.
> Yes, I remember but didn't understand why other SW couldn't be updated to handle. I will
> change as you request but many people will be confused why a port device's name is labeled
> as a memdev. memdev is only correct for EPs and does not correctly reflect *any* of the
> other CXL device types (RP, USP, DSP).
>
>>> __field(u64, serial)
>>> __field(u32, status)
>>> __field(u32, first_error)
>>> __array(u32, header_log, CXL_HEADERLOG_SIZE_U32)
>>> ),
>>> TP_fast_assign(
>>> - __assign_str(memdev);
>>> - __assign_str(host);
>>> - __entry->serial = cxlmd->cxlds->serial;
>>> + __assign_str(name);
>>> + __assign_str(parent);
>>> + __entry->serial = serial;
>>> __entry->status = status;
>>> __entry->first_error = fe;
>>> /*
>>> @@ -99,8 +72,8 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,
>>> */
>>> memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);
>>> ),
>>> - TP_printk("memdev=%s host=%s serial=%lld: status: '%s' first_error:
>>> '%s'",
>>> - __get_str(memdev), __get_str(host), __entry->serial,
>>> + TP_printk("device=%s parent=%s serial=%lld status='%s'
>>> first_error='%s'",
>>> + __get_str(name), __get_str(parent), __entry->serial,
>>> show_uc_errs(__entry->status),
>>> show_uc_errs(__entry->first_error)
>>> )
>>> @@ -124,42 +97,23 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,
>>> { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer"
>>> } \
>>> )
>>>
>>> -TRACE_EVENT(cxl_port_aer_correctable_error,
>>> - TP_PROTO(struct device *dev, u32 status),
>>> - TP_ARGS(dev, status),
>>> - TP_STRUCT__entry(
>>> - __string(device, dev_name(dev))
>>> - __string(host, dev_name(dev->parent))
>>> - __field(u32, status)
>>> - ),
>>> - TP_fast_assign(
>>> - __assign_str(device);
>>> - __assign_str(host);
>>> - __entry->status = status;
>>> - ),
>>> - TP_printk("device=%s host=%s status='%s'",
>>> - __get_str(device), __get_str(host),
>>> - show_ce_errs(__entry->status)
>>> - )
>>> -);
>>> -
>>> TRACE_EVENT(cxl_aer_correctable_error,
>>> - TP_PROTO(const struct cxl_memdev *cxlmd, u32 status),
>>> - TP_ARGS(cxlmd, status),
>>> + TP_PROTO(struct device *dev, u64 serial, u32 status),
>>> + TP_ARGS(dev, serial, status),
>>> TP_STRUCT__entry(
>>> - __string(memdev, dev_name(&cxlmd->dev))
>>> - __string(host, dev_name(cxlmd->dev.parent))
>>> + __string(name, dev_name(dev))
>>> + __string(parent, dev_name(dev->parent))
>> Renaming these fields is an issue for userspace as mentioned above
>> in cxl_aer_uncorrectable_error.
> I understand, I'll revert as you request.
>
> Terry
I'll update the commit message with explanation for leaving as-is.
Terry
>>> __field(u64, serial)
>>> __field(u32, status)
>>> ),
>>> TP_fast_assign(
>>> - __assign_str(memdev);
>>> - __assign_str(host);
>>> - __entry->serial = cxlmd->cxlds->serial;
>>> + __assign_str(name);
>>> + __assign_str(parent);
>>> + __entry->serial = serial;
>>> __entry->status = status;
>>> ),
>>> - TP_printk("memdev=%s host=%s serial=%lld: status: '%s'",
>>> - __get_str(memdev), __get_str(host), __entry->serial,
>>> + TP_printk("device=%s parent=%s serial=%lld status='%s'",
>>> + __get_str(name), __get_str(parent), __entry->serial,
>>> show_ce_errs(__entry->status)
>>> )
>>> );
>>> --
>>> 2.34.1
>> Thanks,
>> Shiju
next prev parent reply other threads:[~2025-06-06 15:24 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-03 17:22 [PATCH v9 00/16] Enable CXL PCIe port protocol error handling and logging Terry Bowman
2025-06-03 17:22 ` [PATCH v9 01/16] PCI/CXL: Add pcie_is_cxl() Terry Bowman
2025-06-04 19:06 ` Sathyanarayanan Kuppuswamy
2025-06-04 19:18 ` Bowman, Terry
2025-06-05 23:24 ` Dave Jiang
2025-06-03 17:22 ` [PATCH v9 02/16] PCI/AER: Report CXL or PCIe bus error type in trace logging Terry Bowman
2025-06-03 22:02 ` Sathyanarayanan Kuppuswamy
2025-06-04 14:32 ` Bowman, Terry
2025-06-04 19:24 ` Sathyanarayanan Kuppuswamy
2025-06-04 21:30 ` Bowman, Terry
2025-06-05 23:28 ` Dave Jiang
2025-06-03 17:22 ` [PATCH v9 03/16] CXL/AER: Introduce kfifo for forwarding CXL errors Terry Bowman
2025-06-04 6:01 ` Dan Carpenter
2025-06-04 14:37 ` Bowman, Terry
2025-06-04 17:24 ` Dan Carpenter
2025-06-04 19:21 ` Bowman, Terry
2025-06-04 22:50 ` Sathyanarayanan Kuppuswamy
2025-06-05 14:04 ` Bowman, Terry
2025-06-06 0:27 ` Dave Jiang
2025-06-06 14:27 ` Bowman, Terry
2025-06-06 14:36 ` Dave Jiang
2025-06-12 11:04 ` Jonathan Cameron
2025-06-12 14:29 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 04/16] PCI/AER: Dequeue forwarded CXL error Terry Bowman
2025-06-04 6:05 ` Dan Carpenter
2025-06-04 14:38 ` Bowman, Terry
2025-06-04 23:58 ` Sathyanarayanan Kuppuswamy
2025-06-06 15:57 ` Dave Jiang
2025-06-06 18:14 ` Bowman, Terry
2025-06-06 22:43 ` Dave Jiang
2025-06-09 19:57 ` Bowman, Terry
2025-06-09 20:34 ` Dave Jiang
2025-06-12 11:17 ` Jonathan Cameron
2025-06-06 21:08 ` Bowman, Terry
2025-06-06 23:15 ` Bowman, Terry
2025-06-09 20:17 ` Dave Jiang
2025-06-10 4:15 ` Lukas Wunner
2025-06-10 18:07 ` Bowman, Terry
2025-06-10 21:20 ` Bowman, Terry
2025-06-11 4:38 ` Lukas Wunner
2025-06-17 16:08 ` Dave Jiang
2025-06-17 18:20 ` Robert Richter
2025-06-12 11:36 ` Jonathan Cameron
2025-06-12 18:35 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 05/16] CXL/PCI: Introduce CXL uncorrectable protocol error recovery Terry Bowman
2025-06-05 15:14 ` Sathyanarayanan Kuppuswamy
2025-06-05 16:01 ` Bowman, Terry
2025-06-06 16:45 ` Dave Jiang
2025-06-06 18:16 ` Bowman, Terry
2025-06-12 16:06 ` Jonathan Cameron
2025-06-12 16:29 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 06/16] cxl/pci: Move RAS initialization to cxl_port driver Terry Bowman
2025-06-06 17:04 ` Dave Jiang
2025-06-06 18:17 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 07/16] cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers Terry Bowman
2025-06-03 17:22 ` [PATCH v9 08/16] cxl/pci: Update RAS handler interfaces to also support CXL Ports Terry Bowman
2025-06-05 16:42 ` Sathyanarayanan Kuppuswamy
2025-06-03 17:22 ` [PATCH v9 09/16] cxl/pci: Log message if RAS registers are unmapped Terry Bowman
2025-06-05 16:42 ` Sathyanarayanan Kuppuswamy
2025-06-06 17:27 ` Dave Jiang
2025-06-03 17:22 ` [PATCH v9 10/16] cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports Terry Bowman
2025-06-05 16:49 ` Sathyanarayanan Kuppuswamy
2025-06-06 9:08 ` Shiju Jose
2025-06-06 14:41 ` Bowman, Terry
2025-06-06 15:24 ` Bowman, Terry [this message]
2025-06-12 16:25 ` Jonathan Cameron
2025-06-03 17:22 ` [PATCH v9 11/16] cxl/pci: Update __cxl_handle_cor_ras() to return early if no RAS errors Terry Bowman
2025-06-05 18:37 ` Sathyanarayanan Kuppuswamy
2025-06-06 20:30 ` Dave Jiang
2025-06-06 20:55 ` Bowman, Terry
2025-06-06 22:38 ` Dave Jiang
2025-06-12 16:46 ` Jonathan Cameron
2025-06-16 20:30 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 12/16] cxl/pci: Introduce CXL Endpoint protocol error handlers Terry Bowman
2025-06-06 0:22 ` Sathyanarayanan Kuppuswamy
2025-06-12 16:55 ` Jonathan Cameron
2025-06-03 17:22 ` [PATCH v9 13/16] cxl/pci: Introduce CXL Port " Terry Bowman
2025-06-06 0:50 ` Sathyanarayanan Kuppuswamy
2025-06-12 17:14 ` Jonathan Cameron
2025-06-16 22:17 ` Bowman, Terry
2025-06-03 17:22 ` [PATCH v9 14/16] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Terry Bowman
2025-06-06 0:50 ` Sathyanarayanan Kuppuswamy
2025-06-12 17:16 ` Jonathan Cameron
2025-06-03 17:22 ` [PATCH v9 15/16] CXL/PCI: Enable CXL protocol errors during CXL Port probe Terry Bowman
2025-06-06 0:51 ` Sathyanarayanan Kuppuswamy
2025-06-03 17:22 ` [PATCH v9 16/16] CXL/PCI: Disable CXL protocol error interrupts during CXL Port cleanup Terry Bowman
2025-06-06 0:52 ` Sathyanarayanan Kuppuswamy
2025-06-06 13:51 ` Bowman, Terry
2025-06-06 22:59 ` Dave Jiang
2025-06-12 17:19 ` Jonathan Cameron
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