From: Jie Gan <jie.gan@oss.qualcomm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Tingwei Zhang <quic_tingweiz@quicinc.com>,
Yuanfang Zhang <quic_yuanfang@quicinc.com>,
Mao Jinlong <quic_jinlmao@quicinc.com>,
Jie Gan <quic_jiegan@quicinc.com>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Subject: [PATCH v3 RESEND 10/10] arm64: dts: qcom: sa8775p: Add interrupts to CTCU device
Date: Mon, 14 Jul 2025 14:31:09 +0800 [thread overview]
Message-ID: <20250714063109.591-11-jie.gan@oss.qualcomm.com> (raw)
In-Reply-To: <20250714063109.591-1-jie.gan@oss.qualcomm.com>
Add interrupts to enable byte-cntr function for TMC ETR devices.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index fed34717460f..44da72cebcf4 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -2762,6 +2762,11 @@ ctcu@4001000 {
clocks = <&aoss_qmp>;
clock-names = "apb";
+ interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "etr0",
+ "etr1";
+
in-ports {
#address-cells = <1>;
#size-cells = <0>;
--
2.34.1
next prev parent reply other threads:[~2025-07-14 6:32 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-14 6:30 [PATCH v3 RESEND 00/10] coresight: ctcu: Enable byte-cntr function for TMC ETR Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 01/10] coresight: core: Refactoring ctcu_get_active_port and make it generic Jie Gan
2025-07-16 10:20 ` Mike Leach
2025-07-17 0:55 ` Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 02/10] coresight: core: add a new API to retrieve the helper device Jie Gan
2025-07-18 8:37 ` Mike Leach
2025-07-18 9:36 ` Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 03/10] dt-bindings: arm: add an interrupt property for Coresight CTCU Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 04/10] coresight: ctcu: enable byte-cntr for TMC ETR devices Jie Gan
2025-07-22 15:23 ` Mike Leach
2025-07-23 1:15 ` Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 05/10] coresight: tmc: add etr_buf_list to store allocated etr_buf Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 06/10] coresight: tmc: add create/delete functions for etr_buf_node Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 07/10] coresight: tmc: add prepare/unprepare functions for byte-cntr Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 08/10] coresight: tmc: add a switch buffer function " Jie Gan
2025-07-22 14:09 ` Mike Leach
2025-07-23 3:29 ` Jie Gan
2025-07-23 5:10 ` Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 09/10] coresight: tmc: add read " Jie Gan
2025-07-22 15:01 ` Mike Leach
2025-07-23 3:24 ` Jie Gan
2025-07-14 6:31 ` Jie Gan [this message]
2025-07-22 15:09 ` [PATCH v3 RESEND 00/10] coresight: ctcu: Enable byte-cntr function for TMC ETR Mike Leach
2025-07-23 1:26 ` Jie Gan
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