From: Jie Gan <jie.gan@oss.qualcomm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Tingwei Zhang <quic_tingweiz@quicinc.com>,
Yuanfang Zhang <quic_yuanfang@quicinc.com>,
Mao Jinlong <quic_jinlmao@quicinc.com>,
Jie Gan <quic_jiegan@quicinc.com>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org
Subject: [PATCH v3 RESEND 07/10] coresight: tmc: add prepare/unprepare functions for byte-cntr
Date: Mon, 14 Jul 2025 14:31:06 +0800 [thread overview]
Message-ID: <20250714063109.591-8-jie.gan@oss.qualcomm.com> (raw)
In-Reply-To: <20250714063109.591-1-jie.gan@oss.qualcomm.com>
Prepare for byte-cntr reading. An additional sysfs_buf is required to
receive trace data, as byte-cntr always reads from the deactivated
and filled sysfs_buf.
The unprepare function releases the additional deactivated sysfs_buf
allocated during the prepare phase.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
.../hwtracing/coresight/coresight-tmc-core.c | 38 ++++++++-
.../hwtracing/coresight/coresight-tmc-etr.c | 79 +++++++++++++++++++
drivers/hwtracing/coresight/coresight-tmc.h | 7 ++
3 files changed, 120 insertions(+), 4 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
index 4d249af93097..354faeeddbb2 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-core.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
@@ -230,7 +230,11 @@ static int tmc_prepare_crashdata(struct tmc_drvdata *drvdata)
static int tmc_read_prepare(struct tmc_drvdata *drvdata)
{
- int ret = 0;
+ struct coresight_device *helper = coresight_get_helper(drvdata->csdev,
+ CORESIGHT_DEV_SUBTYPE_HELPER_CTCU);
+ struct ctcu_byte_cntr *byte_cntr_data = NULL;
+ struct ctcu_drvdata *ctcu_drvdata = NULL;
+ int port, ret = 0;
switch (drvdata->config_type) {
case TMC_CONFIG_TYPE_ETB:
@@ -238,7 +242,18 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdata)
ret = tmc_read_prepare_etb(drvdata);
break;
case TMC_CONFIG_TYPE_ETR:
- ret = tmc_read_prepare_etr(drvdata);
+ if (helper) {
+ port = coresight_get_port_helper(drvdata->csdev, helper);
+ if (port >= 0) {
+ ctcu_drvdata = dev_get_drvdata(helper->dev.parent);
+ byte_cntr_data = &ctcu_drvdata->byte_cntr_data[port];
+ }
+ }
+
+ if (byte_cntr_data && byte_cntr_data->thresh_val)
+ ret = tmc_read_prepare_byte_cntr(drvdata, byte_cntr_data);
+ else
+ ret = tmc_read_prepare_etr(drvdata);
break;
default:
ret = -EINVAL;
@@ -252,7 +267,11 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdata)
static int tmc_read_unprepare(struct tmc_drvdata *drvdata)
{
- int ret = 0;
+ struct coresight_device *helper = coresight_get_helper(drvdata->csdev,
+ CORESIGHT_DEV_SUBTYPE_HELPER_CTCU);
+ struct ctcu_byte_cntr *byte_cntr_data = NULL;
+ struct ctcu_drvdata *ctcu_drvdata = NULL;
+ int port, ret = 0;
switch (drvdata->config_type) {
case TMC_CONFIG_TYPE_ETB:
@@ -260,7 +279,18 @@ static int tmc_read_unprepare(struct tmc_drvdata *drvdata)
ret = tmc_read_unprepare_etb(drvdata);
break;
case TMC_CONFIG_TYPE_ETR:
- ret = tmc_read_unprepare_etr(drvdata);
+ if (helper) {
+ port = coresight_get_port_helper(drvdata->csdev, helper);
+ if (port >= 0) {
+ ctcu_drvdata = dev_get_drvdata(helper->dev.parent);
+ byte_cntr_data = &ctcu_drvdata->byte_cntr_data[port];
+ }
+ }
+
+ if (byte_cntr_data && byte_cntr_data->thresh_val)
+ ret = tmc_read_unprepare_byte_cntr(drvdata, byte_cntr_data);
+ else
+ ret = tmc_read_unprepare_etr(drvdata);
break;
default:
ret = -EINVAL;
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 4609df80ae38..2b73bd8074bb 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -2032,6 +2032,85 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata)
return 0;
}
+int tmc_read_prepare_byte_cntr(struct tmc_drvdata *drvdata,
+ struct ctcu_byte_cntr *byte_cntr_data)
+{
+ unsigned long flags;
+ int ret = 0;
+
+ /* config types are set a boot time and never change */
+ if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETR))
+ return -EINVAL;
+
+ if (coresight_get_mode(drvdata->csdev) != CS_MODE_SYSFS)
+ return -EINVAL;
+
+ /*
+ * The threshold value must not exceed the buffer size.
+ * A margin should be maintained between the two values to account
+ * for the time gap between the interrupt and buffer switching.
+ */
+ if (byte_cntr_data->thresh_val + SZ_16K >= drvdata->size) {
+ dev_err(&drvdata->csdev->dev, "The threshold value is too large\n");
+ return -EINVAL;
+ }
+
+ raw_spin_lock_irqsave(&drvdata->spinlock, flags);
+ if (byte_cntr_data->reading) {
+ ret = -EBUSY;
+ goto out_unlock;
+ }
+
+ byte_cntr_data->reading = true;
+ raw_spin_unlock_irqrestore(&drvdata->spinlock, flags);
+ /* Insert current sysfs_buf into the list */
+ ret = tmc_create_etr_buf_node(drvdata, drvdata->sysfs_buf);
+ if (!ret) {
+ /*
+ * Add one more sysfs_buf for byte-cntr function, byte-cntr always reads
+ * the data from the buffer which has been synced. Switch the buffer when
+ * the used buffer is nearly full. The used buffer will be synced and made
+ * available for reading before switch.
+ */
+ ret = tmc_create_etr_buf_node(drvdata, NULL);
+ if (ret) {
+ dev_err(&drvdata->csdev->dev, "Failed to create etr_buf_node\n");
+ tmc_delete_etr_buf_node(drvdata);
+ byte_cntr_data->reading = false;
+ goto out;
+ }
+ }
+
+ raw_spin_lock_irqsave(&drvdata->spinlock, flags);
+ atomic_set(&byte_cntr_data->irq_cnt, 0);
+ enable_irq(byte_cntr_data->byte_cntr_irq);
+ enable_irq_wake(byte_cntr_data->byte_cntr_irq);
+ byte_cntr_data->total_size = 0;
+ byte_cntr_data->irq_num = 0;
+
+out_unlock:
+ raw_spin_unlock_irqrestore(&drvdata->spinlock, flags);
+
+out:
+ return ret;
+}
+
+int tmc_read_unprepare_byte_cntr(struct tmc_drvdata *drvdata,
+ struct ctcu_byte_cntr *byte_cntr_data)
+{
+ struct device *dev = &drvdata->csdev->dev;
+
+ guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock);
+ disable_irq_wake(byte_cntr_data->byte_cntr_irq);
+ disable_irq(byte_cntr_data->byte_cntr_irq);
+ byte_cntr_data->reading = false;
+ tmc_delete_etr_buf_node(drvdata);
+ dev_dbg(dev, "send data total size:%llu bytes, irq_cnt:%d\n",
+ byte_cntr_data->total_size, byte_cntr_data->irq_num);
+
+ return 0;
+}
+
static const char *const buf_modes_str[] = {
[ETR_MODE_FLAT] = "flat",
[ETR_MODE_ETR_SG] = "tmc-sg",
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index f6b05639aeca..1dbba0bc50a3 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -14,6 +14,8 @@
#include <linux/refcount.h>
#include <linux/crc32.h>
+#include "coresight-ctcu.h"
+
#define TMC_RSZ 0x004
#define TMC_STS 0x00c
#define TMC_RRD 0x010
@@ -357,6 +359,11 @@ extern const struct coresight_ops tmc_etr_cs_ops;
ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata,
loff_t pos, size_t len, char **bufpp);
+/* Byte-cntr functions */
+int tmc_read_prepare_byte_cntr(struct tmc_drvdata *drvdata,
+ struct ctcu_byte_cntr *byte_cntr_data);
+int tmc_read_unprepare_byte_cntr(struct tmc_drvdata *drvdata,
+ struct ctcu_byte_cntr *byte_cntr_data);
#define TMC_REG_PAIR(name, lo_off, hi_off) \
static inline u64 \
--
2.34.1
next prev parent reply other threads:[~2025-07-14 6:31 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-14 6:30 [PATCH v3 RESEND 00/10] coresight: ctcu: Enable byte-cntr function for TMC ETR Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 01/10] coresight: core: Refactoring ctcu_get_active_port and make it generic Jie Gan
2025-07-16 10:20 ` Mike Leach
2025-07-17 0:55 ` Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 02/10] coresight: core: add a new API to retrieve the helper device Jie Gan
2025-07-18 8:37 ` Mike Leach
2025-07-18 9:36 ` Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 03/10] dt-bindings: arm: add an interrupt property for Coresight CTCU Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 04/10] coresight: ctcu: enable byte-cntr for TMC ETR devices Jie Gan
2025-07-22 15:23 ` Mike Leach
2025-07-23 1:15 ` Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 05/10] coresight: tmc: add etr_buf_list to store allocated etr_buf Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 06/10] coresight: tmc: add create/delete functions for etr_buf_node Jie Gan
2025-07-14 6:31 ` Jie Gan [this message]
2025-07-14 6:31 ` [PATCH v3 RESEND 08/10] coresight: tmc: add a switch buffer function for byte-cntr Jie Gan
2025-07-22 14:09 ` Mike Leach
2025-07-23 3:29 ` Jie Gan
2025-07-23 5:10 ` Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 09/10] coresight: tmc: add read " Jie Gan
2025-07-22 15:01 ` Mike Leach
2025-07-23 3:24 ` Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 10/10] arm64: dts: qcom: sa8775p: Add interrupts to CTCU device Jie Gan
2025-07-22 15:09 ` [PATCH v3 RESEND 00/10] coresight: ctcu: Enable byte-cntr function for TMC ETR Mike Leach
2025-07-23 1:26 ` Jie Gan
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