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From: Jie Gan <jie.gan@oss.qualcomm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
	Mike Leach <mike.leach@linaro.org>,
	James Clark <james.clark@linaro.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Tingwei Zhang <quic_tingweiz@quicinc.com>,
	Yuanfang Zhang <quic_yuanfang@quicinc.com>,
	Mao Jinlong <quic_jinlmao@quicinc.com>,
	Jie Gan <quic_jiegan@quicinc.com>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: [PATCH v3 RESEND 08/10] coresight: tmc: add a switch buffer function for byte-cntr
Date: Mon, 14 Jul 2025 14:31:07 +0800	[thread overview]
Message-ID: <20250714063109.591-9-jie.gan@oss.qualcomm.com> (raw)
In-Reply-To: <20250714063109.591-1-jie.gan@oss.qualcomm.com>

Switching the sysfs_buf when current buffer is full or the timeout is
triggered and resets rrp and rwp registers after switched the buffer.
Disable the ETR device if it cannot find an available buffer to switch.

Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
 .../hwtracing/coresight/coresight-tmc-etr.c   | 52 +++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 2b73bd8074bb..3e3e1b5e78ca 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1287,6 +1287,58 @@ static struct etr_buf *tmc_etr_get_sysfs_buffer(struct coresight_device *csdev)
 	return ret ? ERR_PTR(ret) : drvdata->sysfs_buf;
 }
 
+static bool tmc_byte_cntr_switch_buffer(struct tmc_drvdata *drvdata,
+					struct ctcu_byte_cntr *byte_cntr_data)
+{
+	struct etr_buf_node *nd, *next, *curr_node, *picked_node;
+	struct etr_buf *curr_buf = drvdata->sysfs_buf;
+	bool found_free_buf = false;
+
+	if (WARN_ON(!drvdata || !byte_cntr_data))
+		return found_free_buf;
+
+	/* Stop the ETR before we start the switching process */
+	if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS)
+		__tmc_etr_disable_hw(drvdata);
+
+	list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) {
+		/* curr_buf is free for next round */
+		if (nd->sysfs_buf == curr_buf) {
+			nd->is_free = true;
+			curr_node = nd;
+		}
+
+		if (!found_free_buf && nd->is_free && nd->sysfs_buf != curr_buf) {
+			if (nd->reading)
+				continue;
+
+			picked_node = nd;
+			found_free_buf = true;
+		}
+	}
+
+	if (found_free_buf) {
+		curr_node->reading = true;
+		curr_node->pos = 0;
+		drvdata->reading_node = curr_node;
+		drvdata->sysfs_buf = picked_node->sysfs_buf;
+		drvdata->etr_buf = picked_node->sysfs_buf;
+		picked_node->is_free = false;
+		/* Reset irq_cnt for next etr_buf */
+		atomic_set(&byte_cntr_data->irq_cnt, 0);
+		/* Reset rrp and rwp when the system has switched the buffer*/
+		CS_UNLOCK(drvdata->base);
+		tmc_write_rrp(drvdata, 0);
+		tmc_write_rwp(drvdata, 0);
+		CS_LOCK(drvdata->base);
+		/* Restart the ETR when we find a free buffer */
+		if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS)
+			__tmc_etr_enable_hw(drvdata);
+	}
+
+	return found_free_buf;
+}
+
 static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev)
 {
 	int ret = 0;
-- 
2.34.1


  parent reply	other threads:[~2025-07-14  6:31 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-14  6:30 [PATCH v3 RESEND 00/10] coresight: ctcu: Enable byte-cntr function for TMC ETR Jie Gan
2025-07-14  6:31 ` [PATCH v3 RESEND 01/10] coresight: core: Refactoring ctcu_get_active_port and make it generic Jie Gan
2025-07-16 10:20   ` Mike Leach
2025-07-17  0:55     ` Jie Gan
2025-07-14  6:31 ` [PATCH v3 RESEND 02/10] coresight: core: add a new API to retrieve the helper device Jie Gan
2025-07-18  8:37   ` Mike Leach
2025-07-18  9:36     ` Jie Gan
2025-07-14  6:31 ` [PATCH v3 RESEND 03/10] dt-bindings: arm: add an interrupt property for Coresight CTCU Jie Gan
2025-07-14  6:31 ` [PATCH v3 RESEND 04/10] coresight: ctcu: enable byte-cntr for TMC ETR devices Jie Gan
2025-07-22 15:23   ` Mike Leach
2025-07-23  1:15     ` Jie Gan
2025-07-14  6:31 ` [PATCH v3 RESEND 05/10] coresight: tmc: add etr_buf_list to store allocated etr_buf Jie Gan
2025-07-14  6:31 ` [PATCH v3 RESEND 06/10] coresight: tmc: add create/delete functions for etr_buf_node Jie Gan
2025-07-14  6:31 ` [PATCH v3 RESEND 07/10] coresight: tmc: add prepare/unprepare functions for byte-cntr Jie Gan
2025-07-14  6:31 ` Jie Gan [this message]
2025-07-22 14:09   ` [PATCH v3 RESEND 08/10] coresight: tmc: add a switch buffer function " Mike Leach
2025-07-23  3:29     ` Jie Gan
2025-07-23  5:10     ` Jie Gan
2025-07-14  6:31 ` [PATCH v3 RESEND 09/10] coresight: tmc: add read " Jie Gan
2025-07-22 15:01   ` Mike Leach
2025-07-23  3:24     ` Jie Gan
2025-07-14  6:31 ` [PATCH v3 RESEND 10/10] arm64: dts: qcom: sa8775p: Add interrupts to CTCU device Jie Gan
2025-07-22 15:09 ` [PATCH v3 RESEND 00/10] coresight: ctcu: Enable byte-cntr function for TMC ETR Mike Leach
2025-07-23  1:26   ` Jie Gan

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