From: Jie Gan <jie.gan@oss.qualcomm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Tingwei Zhang <quic_tingweiz@quicinc.com>,
Yuanfang Zhang <quic_yuanfang@quicinc.com>,
Mao Jinlong <quic_jinlmao@quicinc.com>,
Jie Gan <quic_jiegan@quicinc.com>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org
Subject: [PATCH v3 RESEND 06/10] coresight: tmc: add create/delete functions for etr_buf_node
Date: Mon, 14 Jul 2025 14:31:05 +0800 [thread overview]
Message-ID: <20250714063109.591-7-jie.gan@oss.qualcomm.com> (raw)
In-Reply-To: <20250714063109.591-1-jie.gan@oss.qualcomm.com>
Create and insert or remove the etr_buf_node to/from the etr_buf_list.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
.../hwtracing/coresight/coresight-tmc-etr.c | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index b07fcdb3fe1a..4609df80ae38 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1909,6 +1909,55 @@ const struct coresight_ops tmc_etr_cs_ops = {
.panic_ops = &tmc_etr_sync_ops,
};
+static void tmc_delete_etr_buf_node(struct tmc_drvdata *drvdata)
+{
+ struct etr_buf_node *nd, *next;
+
+ list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) {
+ if (nd->sysfs_buf == drvdata->sysfs_buf) {
+ list_del(&nd->node);
+ kfree(nd);
+ } else {
+ /* Free allocated buffers which are not utilized by ETR */
+ list_del(&nd->node);
+ tmc_free_etr_buf(nd->sysfs_buf);
+ nd->sysfs_buf = NULL;
+ kfree(nd);
+ }
+ }
+}
+
+static int tmc_create_etr_buf_node(struct tmc_drvdata *drvdata, struct etr_buf *alloc_buf)
+{
+ struct etr_buf_node *sysfs_buf_node;
+ struct etr_buf *sysfs_buf;
+
+ if (!alloc_buf) {
+ sysfs_buf = tmc_alloc_etr_buf(drvdata, drvdata->size, 0, cpu_to_node(0), NULL);
+ if (IS_ERR(sysfs_buf))
+ return PTR_ERR(sysfs_buf);
+ } else {
+ sysfs_buf = alloc_buf;
+ }
+
+ sysfs_buf_node = kzalloc(sizeof(struct etr_buf_node), GFP_KERNEL);
+ if (IS_ERR(sysfs_buf_node)) {
+ if (!alloc_buf)
+ tmc_free_etr_buf(sysfs_buf);
+ return PTR_ERR(sysfs_buf_node);
+ }
+
+ sysfs_buf_node->sysfs_buf = sysfs_buf;
+ sysfs_buf_node->reading = false;
+ if (!alloc_buf)
+ sysfs_buf_node->is_free = true;
+ else
+ sysfs_buf_node->is_free = false;
+ list_add(&sysfs_buf_node->node, &drvdata->etr_buf_list);
+
+ return 0;
+}
+
int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
{
int ret = 0;
--
2.34.1
next prev parent reply other threads:[~2025-07-14 6:31 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-14 6:30 [PATCH v3 RESEND 00/10] coresight: ctcu: Enable byte-cntr function for TMC ETR Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 01/10] coresight: core: Refactoring ctcu_get_active_port and make it generic Jie Gan
2025-07-16 10:20 ` Mike Leach
2025-07-17 0:55 ` Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 02/10] coresight: core: add a new API to retrieve the helper device Jie Gan
2025-07-18 8:37 ` Mike Leach
2025-07-18 9:36 ` Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 03/10] dt-bindings: arm: add an interrupt property for Coresight CTCU Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 04/10] coresight: ctcu: enable byte-cntr for TMC ETR devices Jie Gan
2025-07-22 15:23 ` Mike Leach
2025-07-23 1:15 ` Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 05/10] coresight: tmc: add etr_buf_list to store allocated etr_buf Jie Gan
2025-07-14 6:31 ` Jie Gan [this message]
2025-07-14 6:31 ` [PATCH v3 RESEND 07/10] coresight: tmc: add prepare/unprepare functions for byte-cntr Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 08/10] coresight: tmc: add a switch buffer function " Jie Gan
2025-07-22 14:09 ` Mike Leach
2025-07-23 3:29 ` Jie Gan
2025-07-23 5:10 ` Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 09/10] coresight: tmc: add read " Jie Gan
2025-07-22 15:01 ` Mike Leach
2025-07-23 3:24 ` Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 10/10] arm64: dts: qcom: sa8775p: Add interrupts to CTCU device Jie Gan
2025-07-22 15:09 ` [PATCH v3 RESEND 00/10] coresight: ctcu: Enable byte-cntr function for TMC ETR Mike Leach
2025-07-23 1:26 ` Jie Gan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250714063109.591-7-jie.gan@oss.qualcomm.com \
--to=jie.gan@oss.qualcomm.com \
--cc=alexander.shishkin@linux.intel.com \
--cc=andersson@kernel.org \
--cc=conor+dt@kernel.org \
--cc=coresight@lists.linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=james.clark@linaro.org \
--cc=konradybcio@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mike.leach@linaro.org \
--cc=quic_jiegan@quicinc.com \
--cc=quic_jinlmao@quicinc.com \
--cc=quic_tingweiz@quicinc.com \
--cc=quic_yuanfang@quicinc.com \
--cc=robh@kernel.org \
--cc=suzuki.poulose@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®