From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
To: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Algea Cao <algea.cao@rock-chips.com>,
Dmitry Baryshkov <lumag@kernel.org>
Cc: kernel@collabora.com, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org
Subject: [PATCH v3 06/14] phy: rockchip: samsung-hdptx: Fix coding style alignment
Date: Mon, 18 Aug 2025 21:59:06 +0300 [thread overview]
Message-ID: <20250818-phy-hdptx-frl-v3-6-c79997d8bb2b@collabora.com> (raw)
In-Reply-To: <20250818-phy-hdptx-frl-v3-0-c79997d8bb2b@collabora.com>
Handle a bunch of reported checkpatch.pl complaints:
CHECK: Alignment should match open parenthesis
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 83ec892bd6760865fc9e361f4003c5bfbef55608..495427fc44b385e23da02cd21eefdb137d8b5fdb 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -1657,11 +1657,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset,
LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
- ctrl->tx_jeq_even_ctrl));
+ ctrl->tx_jeq_even_ctrl));
regmap_update_bits(hdptx->regmap, LANE_REG(030c) + offset,
LN_TX_JEQ_ODD_CTRL_RBR_MASK,
FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR_MASK,
- ctrl->tx_jeq_odd_ctrl));
+ ctrl->tx_jeq_odd_ctrl));
regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
LN_TX_SER_40BIT_EN_RBR_MASK,
FIELD_PREP(LN_TX_SER_40BIT_EN_RBR_MASK, 0x1));
@@ -1671,11 +1671,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
- ctrl->tx_jeq_even_ctrl));
+ ctrl->tx_jeq_even_ctrl));
regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
LN_TX_JEQ_ODD_CTRL_HBR_MASK,
FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR_MASK,
- ctrl->tx_jeq_odd_ctrl));
+ ctrl->tx_jeq_odd_ctrl));
regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
LN_TX_SER_40BIT_EN_HBR_MASK,
FIELD_PREP(LN_TX_SER_40BIT_EN_HBR_MASK, 0x1));
@@ -1686,11 +1686,11 @@ static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
- ctrl->tx_jeq_even_ctrl));
+ ctrl->tx_jeq_even_ctrl));
regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
- ctrl->tx_jeq_odd_ctrl));
+ ctrl->tx_jeq_odd_ctrl));
regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
LN_TX_SER_40BIT_EN_HBR2_MASK,
FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2_MASK, 0x1));
--
2.50.1
next prev parent reply other threads:[~2025-08-18 18:59 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-18 18:59 [PATCH v3 00/14] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 01/14] phy: hdmi: Add HDMI 2.1 FRL configuration options Cristian Ciocaltea
2025-08-19 0:42 ` Dmitry Baryshkov
2025-08-19 11:20 ` Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 02/14] phy: rockchip: samsung-hdptx: Fix reported clock rate in high bpc mode Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 03/14] phy: rockchip: samsung-hdptx: Reduce ROPLL loop bandwidth Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 04/14] phy: rockchip: samsung-hdptx: Prevent Inter-Pair Skew from exceeding the limits Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 05/14] phy: rockchip: samsung-hdptx: Use usleep_range() instead of udelay() Cristian Ciocaltea
2025-08-18 18:59 ` Cristian Ciocaltea [this message]
2025-08-18 18:59 ` [PATCH v3 07/14] phy: rockchip: samsung-hdptx: Consistently use [rk_]hdptx_[tmds_] prefixes Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 08/14] phy: rockchip: samsung-hdptx: Enable lane output in common helper Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 09/14] phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 10/14] phy: rockchip: samsung-hdptx: Compute clk rate from PLL config Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 11/14] phy: rockchip: samsung-hdptx: Drop hw_rate driver data Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 12/14] phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 13/14] phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 14/14] phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support Cristian Ciocaltea
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