From: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
To: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Algea Cao <algea.cao@rock-chips.com>,
Dmitry Baryshkov <lumag@kernel.org>
Cc: kernel@collabora.com, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org
Subject: Re: [PATCH v3 01/14] phy: hdmi: Add HDMI 2.1 FRL configuration options
Date: Tue, 19 Aug 2025 03:42:04 +0300 [thread overview]
Message-ID: <3f857197-1cd1-4c18-88e9-e8c00d95af82@oss.qualcomm.com> (raw)
In-Reply-To: <20250818-phy-hdptx-frl-v3-1-c79997d8bb2b@collabora.com>
On 18/08/2025 21:59, Cristian Ciocaltea wrote:
> The HDMI 2.1 specification introduced the Fixed Rate Link (FRL) mode,
> aiming to replace the older Transition-Minimized Differential Signaling
> (TMDS) mode used in previous HDMI versions to support much higher
> bandwidths (up to 48 Gbps) for modern video and audio formats.
>
> FRL has been designed to support ultra high resolution formats at high
> refresh rates like 8K@60Hz or 4K@120Hz, and eliminates the need for
> dynamic bandwidth adjustments, which reduces latency. It operates with
> 3 or 4 lanes at different link rates: 3Gbps, 6Gbps, 8Gbps, 10Gbps or
> 12Gbps.
>
> Add support for configuring the FRL mode for HDMI PHYs.
Could you please point out corresponding DRM patches? They might be WIP
or incomplete. I'd like to see how this works on the consumer side.
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> ---
> include/linux/phy/phy-hdmi.h | 19 +++++++++++++++++--
> 1 file changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h
> index f0ec963c6e84f1b7728acafc824dff191c6b873d..83330d359e3ae345554f20429519da14506b8ab5 100644
> --- a/include/linux/phy/phy-hdmi.h
> +++ b/include/linux/phy/phy-hdmi.h
> @@ -6,16 +6,31 @@
> #ifndef __PHY_HDMI_H_
> #define __PHY_HDMI_H_
>
> +#include <linux/types.h>
> +
> +enum phy_mode_hdmi {
> + PHY_MODE_HDMI_TMDS,
> + PHY_MODE_HDMI_FRL,
There is no unified approach for PHY submode names. Nevertheless I'd
suggest something like PHY_HDMI_MODE_TMDS / _FRL. It follows more
closely the networking / USB submodes. An alternative might be to use
PHY_SUBMODE_HDMI_TMDS / _FRL.
But it's really a nit and/or bikeschedding.
> +};
> +
> /**
> * struct phy_configure_opts_hdmi - HDMI configuration set
> - * @tmds_char_rate: HDMI TMDS Character Rate in Hertz.
> * @bpc: Bits per color channel.
> + * @tmds_char_rate: HDMI TMDS Character Rate in Hertz.
> + * @frl.rate_per_lane: HDMI FRL Rate per Lane in Gbps.
This works nicely until HDMI Forum adds an rate not being even Gbps. Is
there a reason for not using ULL and bps following the tmds_char_rate
design?
> + * @frl.lanes: HDMI FRL lanes count.
> *
> * This structure is used to represent the configuration state of a HDMI phy.
> */
> struct phy_configure_opts_hdmi {
> - unsigned long long tmds_char_rate;
> unsigned int bpc;
> + union {
> + unsigned long long tmds_char_rate;
> + struct {
> + u8 rate_per_lane;
> + u8 lanes;
> + } frl;
> + };
> };
>
> #endif /* __PHY_HDMI_H_ */
>
--
With best wishes
Dmitry
next prev parent reply other threads:[~2025-08-19 0:42 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-18 18:59 [PATCH v3 00/14] Add HDMI 2.1 FRL support to phy-rockchip-samsung-hdptx Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 01/14] phy: hdmi: Add HDMI 2.1 FRL configuration options Cristian Ciocaltea
2025-08-19 0:42 ` Dmitry Baryshkov [this message]
2025-08-19 11:20 ` Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 02/14] phy: rockchip: samsung-hdptx: Fix reported clock rate in high bpc mode Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 03/14] phy: rockchip: samsung-hdptx: Reduce ROPLL loop bandwidth Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 04/14] phy: rockchip: samsung-hdptx: Prevent Inter-Pair Skew from exceeding the limits Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 05/14] phy: rockchip: samsung-hdptx: Use usleep_range() instead of udelay() Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 06/14] phy: rockchip: samsung-hdptx: Fix coding style alignment Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 07/14] phy: rockchip: samsung-hdptx: Consistently use [rk_]hdptx_[tmds_] prefixes Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 08/14] phy: rockchip: samsung-hdptx: Enable lane output in common helper Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 09/14] phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 10/14] phy: rockchip: samsung-hdptx: Compute clk rate from PLL config Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 11/14] phy: rockchip: samsung-hdptx: Drop hw_rate driver data Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 12/14] phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 13/14] phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper Cristian Ciocaltea
2025-08-18 18:59 ` [PATCH v3 14/14] phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support Cristian Ciocaltea
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