* [PATCH v2 1/4] riscv: dts: sophgo: Add SPI NOR node for SG2042
2025-09-16 13:22 [PATCH v2 0/4] Add SPI NOR DTS node for SG2042 SoC and boards using it Zixian Zeng
@ 2025-09-16 13:22 ` Zixian Zeng
2025-09-16 13:22 ` [PATCH v2 2/4] riscv: dts: sophgo: Enable SPI NOR node for PioneerBox Zixian Zeng
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Zixian Zeng @ 2025-09-16 13:22 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen Wang,
Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti
Cc: devicetree, sophgo, linux-riscv, linux-kernel, Han Gao,
Longbin Li, Zixian Zeng
Add SPI NOR controller node for SG2042
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Tested-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index b3e4d3c18fdcf94c2294a56ed6ad866fc59a6adb..0f7d8a3743c35046ceec902902af2b8d3ec8e6bd 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -48,6 +48,30 @@ soc: soc {
interrupt-parent = <&intc>;
ranges;
+ spifmc0: spi@7000180000 {
+ compatible = "sophgo,sg2042-spifmc-nor";
+ reg = <0x70 0x00180000 0x0 0x1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkgen GATE_CLK_AHB_SF>;
+ interrupt-parent = <&intc>;
+ interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rstgen RST_SF0>;
+ status = "disabled";
+ };
+
+ spifmc1: spi@7002180000 {
+ compatible = "sophgo,sg2042-spifmc-nor";
+ reg = <0x70 0x02180000 0x0 0x1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkgen GATE_CLK_AHB_SF>;
+ interrupt-parent = <&intc>;
+ interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&rstgen RST_SF1>;
+ status = "disabled";
+ };
+
i2c0: i2c@7030005000 {
compatible = "snps,designware-i2c";
reg = <0x70 0x30005000 0x0 0x1000>;
--
2.51.0
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v2 2/4] riscv: dts: sophgo: Enable SPI NOR node for PioneerBox
2025-09-16 13:22 [PATCH v2 0/4] Add SPI NOR DTS node for SG2042 SoC and boards using it Zixian Zeng
2025-09-16 13:22 ` [PATCH v2 1/4] riscv: dts: sophgo: Add SPI NOR node for SG2042 Zixian Zeng
@ 2025-09-16 13:22 ` Zixian Zeng
2025-09-16 13:22 ` [PATCH v2 3/4] riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1 Zixian Zeng
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Zixian Zeng @ 2025-09-16 13:22 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen Wang,
Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti
Cc: devicetree, sophgo, linux-riscv, linux-kernel, Han Gao,
Longbin Li, Zixian Zeng
Enable SPI NOR node for PioneerBox device tree
According to PioneerBox schematic, SPI-NOR Flash cannot support QSPI
due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1.
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Tested-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
---
.../riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts | 24 ++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
index ef3a602172b1e5bf3dcf54a8cacdad5172b7f50e..93fb493995522a88d61de67fa570631c01807718 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
@@ -138,6 +138,30 @@ &sd {
status = "okay";
};
+&spifmc0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+};
+
+&spifmc1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+};
+
&uart0 {
pinctrl-0 = <&uart0_cfg>;
pinctrl-names = "default";
--
2.51.0
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v2 3/4] riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1
2025-09-16 13:22 [PATCH v2 0/4] Add SPI NOR DTS node for SG2042 SoC and boards using it Zixian Zeng
2025-09-16 13:22 ` [PATCH v2 1/4] riscv: dts: sophgo: Add SPI NOR node for SG2042 Zixian Zeng
2025-09-16 13:22 ` [PATCH v2 2/4] riscv: dts: sophgo: Enable SPI NOR node for PioneerBox Zixian Zeng
@ 2025-09-16 13:22 ` Zixian Zeng
2025-09-16 13:22 ` [PATCH v2 4/4] riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V2 Zixian Zeng
2025-11-18 1:19 ` [PATCH v2 0/4] Add SPI NOR DTS node for SG2042 SoC and boards using it Inochi Amaoto
4 siblings, 0 replies; 6+ messages in thread
From: Zixian Zeng @ 2025-09-16 13:22 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen Wang,
Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti
Cc: devicetree, sophgo, linux-riscv, linux-kernel, Han Gao,
Longbin Li, Zixian Zeng
Enable SPI NOR node for SG2042_EVB_V1 device tree
According to SG2042_EVB_V1 schematic, SPI-NOR Flash cannot support QSPI
due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1.
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
index 3320bc1dd2c66ab1a77fce719f145070ad51f297..517943696eb464d54d42018825f02a48c6ca00b8 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
@@ -238,6 +238,30 @@ &sd {
status = "okay";
};
+&spifmc0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+};
+
+&spifmc1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+};
+
&uart0 {
pinctrl-0 = <&uart0_cfg>;
pinctrl-names = "default";
--
2.51.0
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v2 4/4] riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V2
2025-09-16 13:22 [PATCH v2 0/4] Add SPI NOR DTS node for SG2042 SoC and boards using it Zixian Zeng
` (2 preceding siblings ...)
2025-09-16 13:22 ` [PATCH v2 3/4] riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1 Zixian Zeng
@ 2025-09-16 13:22 ` Zixian Zeng
2025-11-18 1:19 ` [PATCH v2 0/4] Add SPI NOR DTS node for SG2042 SoC and boards using it Inochi Amaoto
4 siblings, 0 replies; 6+ messages in thread
From: Zixian Zeng @ 2025-09-16 13:22 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen Wang,
Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti
Cc: devicetree, sophgo, linux-riscv, linux-kernel, Han Gao,
Longbin Li, Zixian Zeng
Enable SPI NOR node for SG2042_EVB_V2 device tree
According to SG2042_EVB_V2 schematic, SPI-NOR Flash cannot support QSPI
due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1.
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
index 46980e41b886ce17dacce791fa5f2cef14cfa214..78460b2851a231a3e06b28f9ac6bffd4700e7dab 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
@@ -226,6 +226,18 @@ &sd {
status = "okay";
};
+&spifmc1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+};
+
&uart0 {
pinctrl-0 = <&uart0_cfg>;
pinctrl-names = "default";
--
2.51.0
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v2 0/4] Add SPI NOR DTS node for SG2042 SoC and boards using it
2025-09-16 13:22 [PATCH v2 0/4] Add SPI NOR DTS node for SG2042 SoC and boards using it Zixian Zeng
` (3 preceding siblings ...)
2025-09-16 13:22 ` [PATCH v2 4/4] riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V2 Zixian Zeng
@ 2025-11-18 1:19 ` Inochi Amaoto
4 siblings, 0 replies; 6+ messages in thread
From: Inochi Amaoto @ 2025-11-18 1:19 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen Wang,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Zixian Zeng
Cc: Inochi Amaoto, devicetree, sophgo, linux-riscv, linux-kernel,
Han Gao, Longbin Li
On Tue, 16 Sep 2025 21:22:49 +0800, Zixian Zeng wrote:
> [PATCH 1/4] and [PATCH 2/4] are copied from patch set [1]
> [PATCH v4 4/4] with content changes:
>
> According to SG2042 Pioneer and SG2042_EVB_V1/V2 schematics, SPI-NOR Flash
> cannot support QSPI due to hardware design.
> Thus spi-(tx|rx)-bus-width must be set to 1.
>
> [...]
Applied to dt/riscv, thanks!
[1/4] riscv: dts: sophgo: Add SPI NOR node for SG2042
https://github.com/sophgo/linux/commit/59dc89fdfe0bbcce186116651bd017cfb9f70fc0
[2/4] riscv: dts: sophgo: Enable SPI NOR node for PioneerBox
https://github.com/sophgo/linux/commit/f49314cbbc98f9ab2bf4eb82ccacbf79f179db6c
[3/4] riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1
https://github.com/sophgo/linux/commit/11f4d84c9f724ec4c6810567d6b9713b054bb28b
[4/4] riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V2
https://github.com/sophgo/linux/commit/af5eb17ff893bf6e52680a31059e1816749c2d20
Thanks,
Inochi
^ permalink raw reply [flat|nested] 6+ messages in thread