From: Guodong Xu <guodong@riscstar.com>
To: Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Jonathan Corbet <corbet@lwn.net>,
Shuah Khan <skhan@linuxfoundation.org>,
Conor Dooley <conor@kernel.org>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, Guodong Xu <guodong@riscstar.com>
Subject: [PATCH 1/8] riscv: cpufeature: Add parsing for B
Date: Sat, 07 Feb 2026 18:27:55 +0800 [thread overview]
Message-ID: <20260207-isa-ext-parse-export-v1-1-a64d3a8bc20a@riscstar.com> (raw)
In-Reply-To: <20260207-isa-ext-parse-export-v1-0-a64d3a8bc20a@riscstar.com>
The B extension comprises the Zba, Zbb, and Zbs extensions, as defined
by version 20240411 of the RISC-V Instruction Set Manual Volume I
Unprivileged Architecture.
Add B as a superset extension so that when "b" is encountered in the ISA
string or devicetree, its sub-extensions are automatically enabled.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpufeature.c | 10 ++++++++++
2 files changed, 11 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index aa2af21f3bd32573558e964f94b32f9739f4c89f..35e87e4a8475a9201e84e7f9f8a4d10dfd9e4759 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -11,6 +11,7 @@
#include <uapi/asm/hwcap.h>
#define RISCV_ISA_EXT_a ('a' - 'a')
+#define RISCV_ISA_EXT_b ('b' - 'a')
#define RISCV_ISA_EXT_c ('c' - 'a')
#define RISCV_ISA_EXT_d ('d' - 'a')
#define RISCV_ISA_EXT_f ('f' - 'a')
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 63ad6393b2c6dcbfd6e7e247cf4bacb6c11fe58e..3d3af82a53250f29204a3fb138feaf520a878d0e 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -480,6 +480,15 @@ static const unsigned int riscv_supm_exts[] = {
RISCV_ISA_EXT_SUPM
};
+/*
+ * The B extension comprises Zba, Zbb, and Zbs.
+ */
+static const unsigned int riscv_b_exts[] = {
+ RISCV_ISA_EXT_ZBA,
+ RISCV_ISA_EXT_ZBB,
+ RISCV_ISA_EXT_ZBS,
+};
+
/*
* The canonical order of ISA extension names in the ISA string is defined in
* Chapter 27 of the RISC-V Instruction Set Manual Volume I Unprivileged ISA
@@ -528,6 +537,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_d, riscv_ext_d_validate),
__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
__RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts),
+ __RISCV_ISA_EXT_SUPERSET(b, RISCV_ISA_EXT_b, riscv_b_exts),
__RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_v, riscv_v_exts, riscv_ext_vector_float_validate),
__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
--
2.43.0
next prev parent reply other threads:[~2026-02-07 10:28 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-07 10:27 [PATCH 0/8] riscv: Add cpufeature parsing and hwprobe export for RVA23 extensions Guodong Xu
2026-02-07 10:27 ` Guodong Xu [this message]
2026-02-08 16:43 ` [PATCH 1/8] riscv: cpufeature: Add parsing for B Andrew Jones
2026-02-10 8:15 ` Guodong Xu
2026-02-10 15:14 ` Andrew Jones
2026-02-07 10:27 ` [PATCH 2/8] riscv: hwprobe: Add support for probing B Guodong Xu
2026-02-08 16:47 ` Andrew Jones
2026-02-07 10:27 ` [PATCH 3/8] riscv: cpufeature: Enforce Ziccrse dependency on Zalrsc Guodong Xu
2026-02-07 10:27 ` [PATCH 4/8] riscv: cpufeature: Add parsing for Za64rs, Ziccamoa, Ziccif, and Zicclsm Guodong Xu
2026-02-07 10:27 ` [PATCH 5/8] riscv: hwprobe: Add support for probing Zicclsm Guodong Xu
2026-02-07 10:28 ` [PATCH 6/8] riscv: hwprobe: Add support for probing Ziccif Guodong Xu
2026-02-07 10:28 ` [PATCH 7/8] riscv: cpufeature: Add parsing for Ssccptr, Sscounterenw, Sstvala, Sstvecd, and Ssu64xl Guodong Xu
2026-02-07 10:28 ` [PATCH 8/8] riscv: cpufeature: Add parsing for Sha and its comprised extensions Guodong Xu
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