[PATCH 6/8] riscv: hwprobe: Add support for probing Ziccif

[Guodong Xu <guodong@riscstar.com>]

Ziccif guarantees that instruction fetches from main memory regions with
cacheability and coherence PMAs are atomic for naturally aligned
power-of-2 sizes up to min(ILEN,XLEN). This is a mandatory extension
in the RVA23U64 user-mode profile (and has been since RVA20U64).

Exposing Ziccif through hwprobe allows userspace performing concurrent
code modification (CMODX) to confirm the underlying hardware guarantees
atomic instruction fetches for naturally aligned instructions.

Previous communitiy discussion exists [1].

Link: https://lore.kernel.org/all/20250407180838.42877-12-andybnac@gmail.com/ [1]
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
 Documentation/arch/riscv/hwprobe.rst  | 3 +++
 arch/riscv/include/uapi/asm/hwprobe.h | 1 +
 arch/riscv/kernel/sys_hwprobe.c       | 1 +
 3 files changed, 5 insertions(+)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 198b31bc9a20c2739988849cf7d2948a4fe1bdc4..89ff3d4e9f299de2b7d14b7ed77a04409f821621 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -399,3 +399,6 @@ The following keys are defined:
   * :c:macro:`RISCV_HWPROBE_EXT_ZICCLSM`: The Zicclsm extension for main
     memory that must support misaligned loads and stores, as ratified in
     RISC-V Profiles Version 1.0.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZICCIF`: The Ziccif extension for main memory
+    instruction fetch atomicity, as ratified in RISC-V Profiles Version 1.0.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 323c488de5548883ddceac256bf312ec854ee899..ebf1434f54e6dc640b3414e8a23ab8e29ab243e4 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -118,6 +118,7 @@ struct riscv_hwprobe {
 #define		RISCV_HWPROBE_EXT_ZICFISS	(1ULL << 0)
 #define		RISCV_HWPROBE_IMA_B		(1ULL << 1)
 #define		RISCV_HWPROBE_EXT_ZICCLSM	(1ULL << 2)
+#define		RISCV_HWPROBE_EXT_ZICCIF	(1ULL << 3)
 
 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
 
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 6997c6007a8e86dff85b5b83d14924e7c2466eb2..8d774a0be9110c997a200c4eeeb434e8afd5c7f9 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -209,6 +209,7 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair,
 		 */
 		EXT_KEY(isainfo->isa, ZICFISS, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICCLSM, pair->value, missing);
+		EXT_KEY(isainfo->isa, ZICCIF, pair->value, missing);
 	}
 
 	/* Now turn off reporting features if any CPU is missing it. */

-- 
2.43.0