[PATCH 8/8] riscv: cpufeature: Add parsing for Sha and its comprised extensions

[Guodong Xu <guodong@riscstar.com>]

Sha is a profile-defined extension introduced in RVA23 Profiles
Version 1.0 that captures the full set of features mandated to be
supported along with the H extension. The augmented hypervisor
extension was optional in RVA22 and mandatory in RVA23.

Sha comprises: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala,
Shvstvecd, and Ssstateen.

Add Sha as a superset extension so that when "sha" is encountered in
the ISA string, its sub-extensions are automatically enabled. Also add
individual parsing for each of the comprised extensions.

Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
 arch/riscv/include/asm/hwcap.h |  8 ++++++++
 arch/riscv/kernel/cpufeature.c | 24 ++++++++++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 75f64f5b7355db6ea5218f544ceda3be9619a58a..8cc1d47b1068637fabb94a3f8defb1d6fe3bc180 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -123,6 +123,14 @@
 #define RISCV_ISA_EXT_SSTVALA		113
 #define RISCV_ISA_EXT_SSTVECD		114
 #define RISCV_ISA_EXT_SSU64XL		115
+#define RISCV_ISA_EXT_SHA		116
+#define RISCV_ISA_EXT_SHCOUNTERENW	117
+#define RISCV_ISA_EXT_SHGATPA		118
+#define RISCV_ISA_EXT_SHTVALA		119
+#define RISCV_ISA_EXT_SHVSATPA		120
+#define RISCV_ISA_EXT_SHVSTVALA		121
+#define RISCV_ISA_EXT_SHVSTVECD		122
+#define RISCV_ISA_EXT_SSSTATEEN		123
 
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index fff35a3e85db70f5610df2667f2b4f45f091cb2b..13fa5dd555c4cb40831f75c3a0e0c4c5b518864b 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -498,6 +498,22 @@ static const unsigned int riscv_supm_exts[] = {
 	RISCV_ISA_EXT_SUPM
 };
 
+/*
+ * The Sha extension captures the full set of features mandated along with the
+ * H extension. Sha comprises: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa,
+ * Shvstvala, Shvstvecd, and Ssstateen.
+ */
+static const unsigned int riscv_sha_exts[] = {
+	RISCV_ISA_EXT_h,
+	RISCV_ISA_EXT_SHCOUNTERENW,
+	RISCV_ISA_EXT_SHGATPA,
+	RISCV_ISA_EXT_SHTVALA,
+	RISCV_ISA_EXT_SHVSATPA,
+	RISCV_ISA_EXT_SHVSTVALA,
+	RISCV_ISA_EXT_SHVSTVECD,
+	RISCV_ISA_EXT_SSSTATEEN,
+};
+
 /*
  * The B extension comprises Zba, Zbb, and Zbs.
  */
@@ -638,6 +654,13 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA_VALIDATE(zvksh, RISCV_ISA_EXT_ZVKSH, riscv_ext_vector_crypto_validate),
 	__RISCV_ISA_EXT_BUNDLE_VALIDATE(zvksg, riscv_zvksg_bundled_exts, riscv_ext_vector_crypto_validate),
 	__RISCV_ISA_EXT_DATA_VALIDATE(zvkt, RISCV_ISA_EXT_ZVKT, riscv_ext_vector_crypto_validate),
+	__RISCV_ISA_EXT_SUPERSET(sha, RISCV_ISA_EXT_SHA, riscv_sha_exts),
+	__RISCV_ISA_EXT_DATA(shcounterenw, RISCV_ISA_EXT_SHCOUNTERENW),
+	__RISCV_ISA_EXT_DATA(shgatpa, RISCV_ISA_EXT_SHGATPA),
+	__RISCV_ISA_EXT_DATA(shtvala, RISCV_ISA_EXT_SHTVALA),
+	__RISCV_ISA_EXT_DATA(shvsatpa, RISCV_ISA_EXT_SHVSATPA),
+	__RISCV_ISA_EXT_DATA(shvstvala, RISCV_ISA_EXT_SHVSTVALA),
+	__RISCV_ISA_EXT_DATA(shvstvecd, RISCV_ISA_EXT_SHVSTVECD),
 	__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
 	__RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM),
 	__RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_supm_exts),
@@ -647,6 +670,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
 	__RISCV_ISA_EXT_DATA(sscounterenw, RISCV_ISA_EXT_SSCOUNTERENW),
 	__RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_supm_exts),
+	__RISCV_ISA_EXT_DATA(ssstateen, RISCV_ISA_EXT_SSSTATEEN),
 	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
 	__RISCV_ISA_EXT_DATA(sstvala, RISCV_ISA_EXT_SSTVALA),
 	__RISCV_ISA_EXT_DATA(sstvecd, RISCV_ISA_EXT_SSTVECD),

-- 
2.43.0