From: Guodong Xu <guodong@riscstar.com>
To: Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Jonathan Corbet <corbet@lwn.net>,
Shuah Khan <skhan@linuxfoundation.org>,
Conor Dooley <conor@kernel.org>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, Guodong Xu <guodong@riscstar.com>
Subject: [PATCH 2/8] riscv: hwprobe: Add support for probing B
Date: Sat, 07 Feb 2026 18:27:56 +0800 [thread overview]
Message-ID: <20260207-isa-ext-parse-export-v1-2-a64d3a8bc20a@riscstar.com> (raw)
In-Reply-To: <20260207-isa-ext-parse-export-v1-0-a64d3a8bc20a@riscstar.com>
The B extension is a shorthand for the Zba, Zbb, and Zbs extensions
combined, as defined by version 20240411 of the RISC-V Instruction Set
Manual Volume I Unprivileged Architecture.
The B bit is added as a system-wide check in RISCV_HWPROBE_KEY_IMA_EXT_1
using the global ISA bitmap.
It should be noted that the kernel already exports Zba, Zbb, and Zbs
individually in RISCV_HWPROBE_KEY_IMA_EXT_0 with per-CPU granularity.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
Documentation/arch/riscv/hwprobe.rst | 4 ++++
arch/riscv/include/uapi/asm/hwprobe.h | 1 +
arch/riscv/kernel/sys_hwprobe.c | 3 +++
3 files changed, 8 insertions(+)
diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index c420a8349bc6811573051154bc9c64617f3d7464..8430bc94fdba073e1e3ded973322c773c598a0b5 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -391,3 +391,7 @@ The following keys are defined:
* :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_1`: A bitmask containing additional
extensions that are compatible with the
:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
+
+ * :c:macro:`RISCV_HWPROBE_IMA_B`: The B extension is supported, as defined
+ by version 20240411 of the RISC-V Instruction Set Manual, Volume I
+ Unprivileged Architecture.
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 9139edba0aecbf466098ace486658aaeeb6667e3..e7bd2e9ea33459572d01495f4063e32e3207e48f 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -116,6 +116,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE 15
#define RISCV_HWPROBE_KEY_IMA_EXT_1 16
#define RISCV_HWPROBE_EXT_ZICFISS (1ULL << 0)
+#define RISCV_HWPROBE_IMA_B (1ULL << 1)
/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 1659d31fd288fc296d711c111e8d1a2e2fc8026a..491af3c5b66a0cb30471dafc8b31c70df2f9bed1 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -191,6 +191,9 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair,
pair->value = 0;
+ if (riscv_isa_extension_available(NULL, b))
+ pair->value |= RISCV_HWPROBE_IMA_B;
+
/*
* Loop through and record extensions that 1) anyone has, and 2) anyone
* doesn't have.
--
2.43.0
next prev parent reply other threads:[~2026-02-07 10:28 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-07 10:27 [PATCH 0/8] riscv: Add cpufeature parsing and hwprobe export for RVA23 extensions Guodong Xu
2026-02-07 10:27 ` [PATCH 1/8] riscv: cpufeature: Add parsing for B Guodong Xu
2026-02-08 16:43 ` Andrew Jones
2026-02-10 8:15 ` Guodong Xu
2026-02-10 15:14 ` Andrew Jones
2026-02-07 10:27 ` Guodong Xu [this message]
2026-02-08 16:47 ` [PATCH 2/8] riscv: hwprobe: Add support for probing B Andrew Jones
2026-02-07 10:27 ` [PATCH 3/8] riscv: cpufeature: Enforce Ziccrse dependency on Zalrsc Guodong Xu
2026-02-07 10:27 ` [PATCH 4/8] riscv: cpufeature: Add parsing for Za64rs, Ziccamoa, Ziccif, and Zicclsm Guodong Xu
2026-02-07 10:27 ` [PATCH 5/8] riscv: hwprobe: Add support for probing Zicclsm Guodong Xu
2026-02-07 10:28 ` [PATCH 6/8] riscv: hwprobe: Add support for probing Ziccif Guodong Xu
2026-02-07 10:28 ` [PATCH 7/8] riscv: cpufeature: Add parsing for Ssccptr, Sscounterenw, Sstvala, Sstvecd, and Ssu64xl Guodong Xu
2026-02-07 10:28 ` [PATCH 8/8] riscv: cpufeature: Add parsing for Sha and its comprised extensions Guodong Xu
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