From: Guodong Xu <guodong@riscstar.com>
To: Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Jonathan Corbet <corbet@lwn.net>,
Shuah Khan <skhan@linuxfoundation.org>,
Conor Dooley <conor@kernel.org>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, Guodong Xu <guodong@riscstar.com>
Subject: [PATCH 3/8] riscv: cpufeature: Enforce Ziccrse dependency on Zalrsc
Date: Sat, 07 Feb 2026 18:27:57 +0800 [thread overview]
Message-ID: <20260207-isa-ext-parse-export-v1-3-a64d3a8bc20a@riscstar.com> (raw)
In-Reply-To: <20260207-isa-ext-parse-export-v1-0-a64d3a8bc20a@riscstar.com>
Ziccrse guarantees RsrvEventual for cacheable coherent main memory,
a property that is only meaningful when LR/SC instructions are present.
Since Zalrsc is the extension that provides LR/SC (also implied by A),
add a validation callback to enforce this dependency.
Introduce riscv_ext_zalrsc_depends() following the naming convention
used by other pure dependency checks like riscv_ext_f_depends().
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
arch/riscv/kernel/cpufeature.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 3d3af82a53250f29204a3fb138feaf520a878d0e..68c94fe29cd1b26925fa38a5c877d699bbc88e25 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -338,6 +338,15 @@ static int riscv_ext_supm_validate(const struct riscv_isa_ext_data *data,
return -EPROBE_DEFER;
}
+static int riscv_ext_zalrsc_depends(const struct riscv_isa_ext_data *data,
+ const unsigned long *isa_bitmap)
+{
+ if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZALRSC))
+ return 0;
+
+ return -EPROBE_DEFER;
+}
+
static const unsigned int riscv_a_exts[] = {
RISCV_ISA_EXT_ZAAMO,
RISCV_ISA_EXT_ZALRSC,
@@ -543,7 +552,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
__RISCV_ISA_EXT_DATA_VALIDATE(zicbop, RISCV_ISA_EXT_ZICBOP, riscv_ext_zicbop_validate),
__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate),
- __RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE),
+ __RISCV_ISA_EXT_DATA_VALIDATE(ziccrse, RISCV_ISA_EXT_ZICCRSE, riscv_ext_zalrsc_depends),
__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_xlinuxenvcfg_exts,
riscv_cfilp_validate),
__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicfiss, RISCV_ISA_EXT_ZICFISS, riscv_xlinuxenvcfg_exts,
--
2.43.0
next prev parent reply other threads:[~2026-02-07 10:28 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-07 10:27 [PATCH 0/8] riscv: Add cpufeature parsing and hwprobe export for RVA23 extensions Guodong Xu
2026-02-07 10:27 ` [PATCH 1/8] riscv: cpufeature: Add parsing for B Guodong Xu
2026-02-08 16:43 ` Andrew Jones
2026-02-10 8:15 ` Guodong Xu
2026-02-10 15:14 ` Andrew Jones
2026-02-07 10:27 ` [PATCH 2/8] riscv: hwprobe: Add support for probing B Guodong Xu
2026-02-08 16:47 ` Andrew Jones
2026-02-07 10:27 ` Guodong Xu [this message]
2026-02-07 10:27 ` [PATCH 4/8] riscv: cpufeature: Add parsing for Za64rs, Ziccamoa, Ziccif, and Zicclsm Guodong Xu
2026-02-07 10:27 ` [PATCH 5/8] riscv: hwprobe: Add support for probing Zicclsm Guodong Xu
2026-02-07 10:28 ` [PATCH 6/8] riscv: hwprobe: Add support for probing Ziccif Guodong Xu
2026-02-07 10:28 ` [PATCH 7/8] riscv: cpufeature: Add parsing for Ssccptr, Sscounterenw, Sstvala, Sstvecd, and Ssu64xl Guodong Xu
2026-02-07 10:28 ` [PATCH 8/8] riscv: cpufeature: Add parsing for Sha and its comprised extensions Guodong Xu
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