[PATCH v5 0/2] sched: Enable preferred SMT siblings on NVIDIA Olympus

[PATCH v5 0/2] sched: Enable preferred SMT siblings on NVIDIA Olympus

[Andrea Righi]

NVIDIA Olympus implements SMT with two symmetric processing elements (PEs).
When only one PE is active, the core operates in single-thread mode and
that PE can use the full core resources. When both PEs are active, the core
operates in two-thread mode and the PEs share those resources. This
behavior is common to SMT implementations, but Olympus is particularly
sensitive to brief sibling activations because returning from two-thread
mode to single-thread mode after a sibling becomes idle is not immediate.
As described by commit 293f9611ae735 ("sched/fair: Prefer fully idle cores
for NOHZ balancing"):

  Briefly activating an otherwise idle sibling can reduce the performance
  available to the other sibling and this effect does not necessarily end
  once the activated sibling becomes idle: after the ILB finishes and its
  CPU enters WFI, full single-thread performance is restored only after the
  sibling has remained idle for a qualification interval (10 Ki cycles on
  the tested Vera system).

That change prevents the NOHZ idle load balancer from unnecessarily waking
a sibling of a busy PE. However, ordinary task placement can still select
either sibling of an idle core and repeated changes of the active PE can
keep Olympus cores in two-thread mode despite little or no useful overlap
between the siblings.

This series makes PE0 the preferred sibling of an Olympus core using
SD_ASYM_PACKING and teaches the fair scheduler's idle-selection paths to
honor asymmetric SMT priority. The scheduler first selects a candidate CPU
and core according to its existing placement and capacity rules, then
chooses the highest-priority available sibling within that core. The
generic scheduler behavior is enabled only when an architecture supplies
an SD_ASYM_PACKING SMT domain.

PE0 and PE1 have equal steady-state capacity, the preference does not
identify a faster PE. PE0 is used only as a canonical choice when both
siblings are available. Consistently selecting the same sibling avoids
alternating the active PE across wakeups, lets PE1 remain idle for longer,
and allows more cores to remain in, or return to, full-resource
single-thread mode.

The series was tested on a two-node Vera system using an 88-thread
single-precision GEMM on the 88 physical cores of NUMA node 0.

With the workload allowed to choose either sibling of every core, observed
throughput improved from approximately 9.4 TFLOP/s on the baseline kernel
to approximately 10.1 TFLOP/s with this series applied. Repeated runs also
became more predictable because the workload consistently settled on PE0
while PE1 remained quiet.

Changes in v5:
 - Remove the redundant olympus_prefer_pe0 state (K Prateek Nayak)
 - Link to v4: https://lore.kernel.org/r/20260908082345.103087-1-arighi@nvidia.com

Changes in v4:
 - Honor the SMT sibling priority in the slow path (Srikar Dronamraju)
 - Rename the consolidated helper to select_idle_smt_cpu() (Srikar Dronamraju)
 - Link to v3: https://lore.kernel.org/r/20260907163513.4172411-1-arighi@nvidia.com

Changes in v3:
 - Consolidate the SMT-priority adjustment in select_idle_sibling() after an
   idle candidate has been selected (K Prateek Nayak)
 - Fold the asym SMT checks into select_idle_smt_priority() and scan the
   scheduling-domain span directly (K Prateek Nayak)
 - Link to v2: https://lore.kernel.org/r/20260904091838.3617894-1-arighi@nvidia.com

Changes in v2:
 - Clarify that the generic scheduler change also covers POWER7 (Dietmar
   Eggemann)
 - Simplify sched_smt_asym_prefer() by inspecting the lowest scheduling
   domain directly (Dietmar Eggemann)
 - Link to v1: https://lore.kernel.org/r/20260831181800.1668646-1-arighi@nvidia.com

Andrea Righi (2):
      arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores
      sched/fair: Honor asymmetric SMT priority in idle selection

 arch/arm64/include/asm/topology.h |  1 +
 arch/arm64/kernel/smp.c           |  1 +
 arch/arm64/kernel/topology.c      | 51 +++++++++++++++++++++++
 kernel/sched/fair.c               | 85 +++++++++++++++++++++++++++++++--------
 kernel/sched/sched.h              |  6 +++
 kernel/sched/topology.c           | 36 +++++++++++++++++
 6 files changed, 163 insertions(+), 17 deletions(-)

[PATCH 1/2] arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores

[Andrea Righi]

NVIDIA Olympus implements spatial SMT with symmetric steady-state PE
capacity but two different resource modes. One-Thread Active mode gives
one PE the full core, while waking the other PE restores Two-Thread
Active mode and partitions decode, issue, cache, TLB, and vector
resources. Returning to full-resource mode requires the sibling to
remain in WFI for 10 Ki cycles.

Measurements show that pinned workloads perform equally on either PE,
but freely migratable workloads lose substantial throughput when they
alternate between PE identities. Consistently selecting PE0 keeps PE1
idle, avoids repeated SMT repartitioning, and restores
one-thread-per-core performance.

Describe this scheduling preference with SD_ASYM_PACKING and give PE0,
identified by MPIDR_EL1.Aff0, the higher arch_asym_cpu_priority(). This
is independent of SD_ASYM_CPUCAPACITY: SMT siblings retain equal
capacity, while physical cores with different maximum frequencies are
handled by a higher scheduling domain.

Firmware currently provides no interface for describing the preferred
SMT sibling. Detect Olympus by MIDR until such an interface is
available.

Reviewed-by: K Prateek Nayak <kprateek.nayak@amd.com>
Tested-by: K Prateek Nayak <kprateek.nayak@amd.com>
Signed-off-by: Andrea Righi <arighi@nvidia.com>
---
 arch/arm64/include/asm/topology.h |  1 +
 arch/arm64/kernel/smp.c           |  1 +
 arch/arm64/kernel/topology.c      | 51 +++++++++++++++++++++++++++++++
 3 files changed, 53 insertions(+)

diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h
index b9eaf4ad70850..edc1c59b3448d 100644
--- a/arch/arm64/include/asm/topology.h
+++ b/arch/arm64/include/asm/topology.h
@@ -18,6 +18,7 @@ int pcibus_to_node(struct pci_bus *bus);
 #include <linux/arch_topology.h>
 
 void update_freq_counters_refs(void);
+void arm64_init_sched_topology(void);
 
 /* Replace task scheduler's default frequency-invariant accounting */
 #define arch_scale_freq_tick topology_scale_freq_tick
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index a61dc3016a117..0135ac4eea8bd 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -443,6 +443,7 @@ void __init smp_cpus_done(unsigned int max_cpus)
 	hyp_mode_check();
 	setup_system_features();
 	setup_user_features();
+	arm64_init_sched_topology();
 	mark_linear_text_alias_ro();
 }
 
diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
index d28438f8b83f1..e5a7a4b2e3844 100644
--- a/arch/arm64/kernel/topology.c
+++ b/arch/arm64/kernel/topology.c
@@ -19,6 +19,8 @@
 #include <linux/init.h>
 #include <linux/percpu.h>
 #include <linux/sched/isolation.h>
+#include <linux/sched/topology.h>
+#include <linux/smp.h>
 #include <linux/xarray.h>
 
 #include <asm/cpu.h>
@@ -44,6 +46,55 @@
 static DEFINE_PER_CPU_READ_MOSTLY(unsigned long, arch_max_freq_scale) =  1UL << (2 * SCHED_CAPACITY_SHIFT);
 static cpumask_var_t amu_fie_cpus;
 
+/*
+ * Switching the active PE on an NVIDIA Olympus SMT core can keep the core in
+ * two-thread active mode, with resources partitioned between the PEs.
+ *
+ * Prefer PE0 so PE1 can remain idle and the core can stay in full-resource
+ * mode. Firmware does not currently describe this preference, so detect
+ * Olympus by MIDR until a firmware interface is available.
+ */
+#ifdef CONFIG_SCHED_SMT
+static int arm64_smt_flags(void)
+{
+	return cpu_smt_flags() | SD_ASYM_PACKING;
+}
+#endif
+
+static struct sched_domain_topology_level arm64_asym_smt_topology[] = {
+#ifdef CONFIG_SCHED_SMT
+	SDTL_INIT(tl_smt_mask, arm64_smt_flags, SMT),
+#endif
+#ifdef CONFIG_SCHED_CLUSTER
+	SDTL_INIT(tl_cls_mask, cpu_cluster_flags, CLS),
+#endif
+#ifdef CONFIG_SCHED_MC
+	SDTL_INIT(tl_mc_mask, cpu_core_flags, MC),
+#endif
+	SDTL_INIT(tl_pkg_mask, NULL, PKG),
+	{ NULL, },
+};
+
+void __init arm64_init_sched_topology(void)
+{
+	if (!IS_ENABLED(CONFIG_SCHED_SMT))
+		return;
+
+	if ((read_cpuid_id() & MIDR_CPU_MODEL_MASK) != MIDR_NVIDIA_OLYMPUS)
+		return;
+
+	if (!topology_core_has_smt(smp_processor_id()))
+		return;
+
+	set_sched_topology(arm64_asym_smt_topology);
+	pr_info("Enabling PE0 SMT preference for NVIDIA Olympus\n");
+}
+
+int arch_asym_cpu_priority(int cpu)
+{
+	return MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0) == 0;
+}
+
 struct amu_cntr_sample {
 	u64		arch_const_cycles_prev;
 	u64		arch_core_cycles_prev;
-- 
2.55.0

[PATCH 2/2] sched/fair: Honor asymmetric SMT priority in idle selection

[Andrea Righi]

POWER7 and NVIDIA Olympus use SD_ASYM_PACKING at the shared-capacity SMT
level to order hardware threads. Idle CPU selection does not consult
that order, so a task can wake on an arbitrary sibling and remain there
until load balancing corrects the placement. On these systems, that
initial choice can prevent the core from entering its preferred
lower-thread resource mode and cause a large and persistent performance
loss.

When idle selection finds an available CPU in an SMT core, choose the
highest-priority available sibling. On SMT2 Olympus this only changes
selection on fully idle cores. A partially idle core has only one
available CPU. On wider SMT systems such as POWER7, it also fills
available siblings in priority order while the core is partially busy.

Apply the preference to idle-core and idle-CPU scans,
asymmetric-capacity scans, target, previous, recently-used CPU fast
paths and the slow path. Inspect the lowest scheduling domain directly,
but require both CPUs to share its span because isolcpus can split
hardware siblings across scheduling domains.

Keep physical-core capacity selection independent from SMT sibling
ordering. SD_ASYM_CPUCAPACITY first selects among cores with different
maximum capacities, then SD_ASYM_PACKING selects the preferred available
sibling inside the chosen core, whose siblings continue to share equal
capacity.

Reviewed-by: Srikar Dronamraju <srikar@linux.ibm.com>
Signed-off-by: Andrea Righi <arighi@nvidia.com>
---
 kernel/sched/fair.c     | 85 ++++++++++++++++++++++++++++++++---------
 kernel/sched/sched.h    |  6 +++
 kernel/sched/topology.c | 36 +++++++++++++++++
 3 files changed, 110 insertions(+), 17 deletions(-)

diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
index b8bd308c2d5b1..37837c36288a0 100644
--- a/kernel/sched/fair.c
+++ b/kernel/sched/fair.c
@@ -8587,6 +8587,35 @@ static inline bool test_idle_cores(int cpu)
 	return false;
 }
 
+/*
+ * Redirect a CPU to a higher-priority available sibling in its SMT domain,
+ * subject to task affinity.
+ */
+static inline int select_idle_smt_cpu(struct task_struct *p, int cpu)
+{
+	struct sched_domain *sd;
+	int best = cpu;
+	int sibling;
+
+	if (!sched_smt_asym_active())
+		return cpu;
+
+	sd = rcu_dereference_all(cpu_rq(cpu)->sd);
+	if (!sd || !(sd->flags & SD_SHARE_CPUCAPACITY) ||
+	    !(sd->flags & SD_ASYM_PACKING))
+		return cpu;
+
+	for_each_cpu_and(sibling, sched_domain_span(sd), p->cpus_ptr) {
+		if (sibling == best || !choose_idle_cpu(sibling, p))
+			continue;
+
+		if (sched_asym_prefer(sibling, best))
+			best = sibling;
+	}
+
+	return best;
+}
+
 /*
  * Scans the local SMT mask to see if the entire core is idle, and records this
  * information in sd_balance_shared->has_idle_cores.
@@ -8971,7 +9000,7 @@ static int select_idle_sibling(struct task_struct *p, int prev, int target)
 
 	if (choose_idle_cpu(target, p) &&
 	    asym_fits_cpu(task_util, util_min, util_max, target))
-		return target;
+		goto select_smt_priority;
 
 	/*
 	 * If the previous CPU is cache affine and idle, don't be stupid:
@@ -8981,8 +9010,10 @@ static int select_idle_sibling(struct task_struct *p, int prev, int target)
 	    asym_fits_cpu(task_util, util_min, util_max, prev)) {
 
 		if (!static_branch_unlikely(&sched_cluster_active) ||
-		    cpus_share_resources(prev, target))
-			return prev;
+		    cpus_share_resources(prev, target)) {
+			target = prev;
+			goto select_smt_priority;
+		}
 
 		prev_aff = prev;
 	}
@@ -9000,7 +9031,8 @@ static int select_idle_sibling(struct task_struct *p, int prev, int target)
 	    prev == smp_processor_id() &&
 	    this_rq()->nr_running <= 1 &&
 	    asym_fits_cpu(task_util, util_min, util_max, prev)) {
-		return prev;
+		target = prev;
+		goto select_smt_priority;
 	}
 
 	/* Check a recently used CPU as a potential idle candidate: */
@@ -9014,8 +9046,10 @@ static int select_idle_sibling(struct task_struct *p, int prev, int target)
 	    asym_fits_cpu(task_util, util_min, util_max, recent_used_cpu)) {
 
 		if (!static_branch_unlikely(&sched_cluster_active) ||
-		    cpus_share_resources(recent_used_cpu, target))
-			return recent_used_cpu;
+		    cpus_share_resources(recent_used_cpu, target)) {
+			target = recent_used_cpu;
+			goto select_smt_priority;
+		}
 
 	} else {
 		recent_used_cpu = -1;
@@ -9037,7 +9071,11 @@ static int select_idle_sibling(struct task_struct *p, int prev, int target)
 		 */
 		if (sd) {
 			i = select_idle_capacity(p, sd, target);
-			return ((unsigned)i < nr_cpumask_bits) ? i : target;
+			if ((unsigned int)i < nr_cpumask_bits) {
+				target = i;
+				goto select_smt_priority;
+			}
+			return target;
 		}
 	}
 
@@ -9050,14 +9088,18 @@ static int select_idle_sibling(struct task_struct *p, int prev, int target)
 
 		if (!has_idle_core && cpus_share_cache(prev, target)) {
 			i = select_idle_smt(p, sd, prev);
-			if ((unsigned int)i < nr_cpumask_bits)
-				return i;
+			if ((unsigned int)i < nr_cpumask_bits) {
+				target = i;
+				goto select_smt_priority;
+			}
 		}
 	}
 
 	i = select_idle_cpu(p, sd, has_idle_core, target);
-	if ((unsigned)i < nr_cpumask_bits)
-		return i;
+	if ((unsigned int)i < nr_cpumask_bits) {
+		target = i;
+		goto select_smt_priority;
+	}
 
 	/*
 	 * For cluster machines which have lower sharing cache like L2 or
@@ -9065,12 +9107,19 @@ static int select_idle_sibling(struct task_struct *p, int prev, int target)
 	 * first. But prev_cpu or recent_used_cpu may also be a good candidate,
 	 * use them if possible when no idle CPU found in select_idle_cpu().
 	 */
-	if ((unsigned int)prev_aff < nr_cpumask_bits)
-		return prev_aff;
-	if ((unsigned int)recent_used_cpu < nr_cpumask_bits)
-		return recent_used_cpu;
+	if ((unsigned int)prev_aff < nr_cpumask_bits) {
+		target = prev_aff;
+		goto select_smt_priority;
+	}
+	if ((unsigned int)recent_used_cpu < nr_cpumask_bits) {
+		target = recent_used_cpu;
+		goto select_smt_priority;
+	}
 
 	return target;
+
+select_smt_priority:
+	return select_idle_smt_cpu(p, target);
 }
 
 /**
@@ -9747,8 +9796,10 @@ select_task_rq_fair(struct task_struct *p, int prev_cpu, int wake_flags)
 	}
 
 	/* Slow path */
-	if (unlikely(sd))
-		return sched_balance_find_dst_cpu(sd, p, cpu, prev_cpu, sd_flag);
+	if (unlikely(sd)) {
+		new_cpu = sched_balance_find_dst_cpu(sd, p, cpu, prev_cpu, sd_flag);
+		return select_idle_smt_cpu(p, new_cpu);
+	}
 
 	/* Fast path */
 	if (wake_flags & WF_TTWU)
diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h
index 6c3ad70e58b8e..568cb1ed2dd6b 100644
--- a/kernel/sched/sched.h
+++ b/kernel/sched/sched.h
@@ -2240,6 +2240,7 @@ DECLARE_PER_CPU(struct sched_domain __rcu *, sd_asym_packing);
 DECLARE_PER_CPU(struct sched_domain __rcu *, sd_asym_cpucapacity);
 
 extern struct static_key_false sched_asym_cpucapacity;
+extern struct static_key_false sched_smt_asym_packing;
 extern struct static_key_false sched_cluster_active;
 
 static __always_inline bool sched_asym_cpucap_active(void)
@@ -2247,6 +2248,11 @@ static __always_inline bool sched_asym_cpucap_active(void)
 	return static_branch_unlikely(&sched_asym_cpucapacity);
 }
 
+static __always_inline bool sched_smt_asym_active(void)
+{
+	return static_branch_unlikely(&sched_smt_asym_packing);
+}
+
 struct sched_group_capacity {
 	atomic_t		ref;
 	/*
diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c
index 0248227d983a7..06c40eb5932af 100644
--- a/kernel/sched/topology.c
+++ b/kernel/sched/topology.c
@@ -683,8 +683,24 @@ DEFINE_PER_CPU(struct sched_domain __rcu *, sd_asym_packing);
 DEFINE_PER_CPU(struct sched_domain __rcu *, sd_asym_cpucapacity);
 
 DEFINE_STATIC_KEY_FALSE(sched_asym_cpucapacity);
+DEFINE_STATIC_KEY_FALSE(sched_smt_asym_packing);
 DEFINE_STATIC_KEY_FALSE(sched_cluster_active);
 
+static bool has_asym_smt_domain(int cpu)
+{
+	struct sched_domain *sd;
+
+	for_each_domain(cpu, sd) {
+		if (!(sd->flags & SD_SHARE_CPUCAPACITY))
+			break;
+
+		if (sd->flags & SD_ASYM_PACKING)
+			return true;
+	}
+
+	return false;
+}
+
 static void update_top_cache_domain(int cpu)
 {
 	struct sched_domain_shared *sds = NULL;
@@ -3084,6 +3100,7 @@ build_sched_domains(const struct cpumask *cpu_map, struct sched_domain_attr *att
 	struct rq *rq = NULL;
 	int i, ret = -ENOMEM;
 	bool has_asym = false;
+	bool has_asym_smt = false;
 	bool has_cluster = false;
 
 	if (WARN_ON(cpumask_empty(cpu_map)))
@@ -3202,6 +3219,9 @@ build_sched_domains(const struct cpumask *cpu_map, struct sched_domain_attr *att
 
 		cpu_attach_domain(sd, d.rd, i);
 
+		if (has_asym_smt_domain(i))
+			has_asym_smt = true;
+
 		if (lowest_flag_domain(i, SD_CLUSTER))
 			has_cluster = true;
 	}
@@ -3210,6 +3230,9 @@ build_sched_domains(const struct cpumask *cpu_map, struct sched_domain_attr *att
 	if (has_asym)
 		static_branch_inc_cpuslocked(&sched_asym_cpucapacity);
 
+	if (has_asym_smt)
+		static_branch_inc_cpuslocked(&sched_smt_asym_packing);
+
 	if (has_cluster)
 		static_branch_inc_cpuslocked(&sched_cluster_active);
 
@@ -3310,11 +3333,24 @@ int __init sched_init_domains(const struct cpumask *cpu_map)
 static void detach_destroy_domains(const struct cpumask *cpu_map)
 {
 	unsigned int cpu = cpumask_any(cpu_map);
+	bool has_asym_smt = false;
 	int i;
 
+	rcu_read_lock();
+	for_each_cpu(i, cpu_map) {
+		if (has_asym_smt_domain(i)) {
+			has_asym_smt = true;
+			break;
+		}
+	}
+	rcu_read_unlock();
+
 	if (rcu_access_pointer(per_cpu(sd_asym_cpucapacity, cpu)))
 		static_branch_dec_cpuslocked(&sched_asym_cpucapacity);
 
+	if (has_asym_smt)
+		static_branch_dec_cpuslocked(&sched_smt_asym_packing);
+
 	if (static_branch_unlikely(&sched_cluster_active))
 		static_branch_dec_cpuslocked(&sched_cluster_active);
 
-- 
2.55.0

Re: [PATCH v5 0/2] sched: Enable preferred SMT siblings on NVIDIA Olympus

[K Prateek Nayak]

Hello Andrea,

On 9/9/2026 11:56 AM, Andrea Righi wrote:
> NVIDIA Olympus implements SMT with two symmetric processing elements (PEs).
> When only one PE is active, the core operates in single-thread mode and
> that PE can use the full core resources. When both PEs are active, the core
> operates in two-thread mode and the PEs share those resources. This
> behavior is common to SMT implementations, but Olympus is particularly
> sensitive to brief sibling activations because returning from two-thread
> mode to single-thread mode after a sibling becomes idle is not immediate.
> As described by commit 293f9611ae735 ("sched/fair: Prefer fully idle cores
> for NOHZ balancing"):
> 
>   Briefly activating an otherwise idle sibling can reduce the performance
>   available to the other sibling and this effect does not necessarily end
>   once the activated sibling becomes idle: after the ILB finishes and its
>   CPU enters WFI, full single-thread performance is restored only after the
>   sibling has remained idle for a qualification interval (10 Ki cycles on
>   the tested Vera system).
> 
> That change prevents the NOHZ idle load balancer from unnecessarily waking
> a sibling of a busy PE. However, ordinary task placement can still select
> either sibling of an idle core and repeated changes of the active PE can
> keep Olympus cores in two-thread mode despite little or no useful overlap
> between the siblings.
> 
> This series makes PE0 the preferred sibling of an Olympus core using
> SD_ASYM_PACKING and teaches the fair scheduler's idle-selection paths to
> honor asymmetric SMT priority. The scheduler first selects a candidate CPU
> and core according to its existing placement and capacity rules, then
> chooses the highest-priority available sibling within that core. The
> generic scheduler behavior is enabled only when an architecture supplies
> an SD_ASYM_PACKING SMT domain.
> 
> PE0 and PE1 have equal steady-state capacity, the preference does not
> identify a faster PE. PE0 is used only as a canonical choice when both
> siblings are available. Consistently selecting the same sibling avoids
> alternating the active PE across wakeups, lets PE1 remain idle for longer,
> and allows more cores to remain in, or return to, full-resource
> single-thread mode.
> 
> The series was tested on a two-node Vera system using an 88-thread
> single-precision GEMM on the 88 physical cores of NUMA node 0.
> 
> With the workload allowed to choose either sibling of every core, observed
> throughput improved from approximately 9.4 TFLOP/s on the baseline kernel
> to approximately 10.1 TFLOP/s with this series applied. Repeated runs also
> became more predictable because the workload consistently settled on PE0
> while PE1 remained quiet.
> 
> Changes in v5:
>  - Remove the redundant olympus_prefer_pe0 state (K Prateek Nayak)
>  - Link to v4: https://lore.kernel.org/r/20260908082345.103087-1-arighi@nvidia.com

My replies failed to keep up with your speed on iterations :-)

Since this is same as v4 and I had taken it for a spin on a
x86 and an ARM64 server, feel free to include:

Reviewed-by: K Prateek Nayak <kprateek.nayak@amd.com>
Tested-by: K Prateek Nayak <kprateek.nayak@amd.com>

-- 
Thanks and Regards,
Prateek

Re: [PATCH v5 0/2] sched: Enable preferred SMT siblings on NVIDIA Olympus

[Andrea Righi]

On Wed, Sep 09, 2026 at 12:06:06PM +0530, K Prateek Nayak wrote:
> Hello Andrea,
> 
> On 9/9/2026 11:56 AM, Andrea Righi wrote:
> > NVIDIA Olympus implements SMT with two symmetric processing elements (PEs).
> > When only one PE is active, the core operates in single-thread mode and
> > that PE can use the full core resources. When both PEs are active, the core
> > operates in two-thread mode and the PEs share those resources. This
> > behavior is common to SMT implementations, but Olympus is particularly
> > sensitive to brief sibling activations because returning from two-thread
> > mode to single-thread mode after a sibling becomes idle is not immediate.
> > As described by commit 293f9611ae735 ("sched/fair: Prefer fully idle cores
> > for NOHZ balancing"):
> > 
> >   Briefly activating an otherwise idle sibling can reduce the performance
> >   available to the other sibling and this effect does not necessarily end
> >   once the activated sibling becomes idle: after the ILB finishes and its
> >   CPU enters WFI, full single-thread performance is restored only after the
> >   sibling has remained idle for a qualification interval (10 Ki cycles on
> >   the tested Vera system).
> > 
> > That change prevents the NOHZ idle load balancer from unnecessarily waking
> > a sibling of a busy PE. However, ordinary task placement can still select
> > either sibling of an idle core and repeated changes of the active PE can
> > keep Olympus cores in two-thread mode despite little or no useful overlap
> > between the siblings.
> > 
> > This series makes PE0 the preferred sibling of an Olympus core using
> > SD_ASYM_PACKING and teaches the fair scheduler's idle-selection paths to
> > honor asymmetric SMT priority. The scheduler first selects a candidate CPU
> > and core according to its existing placement and capacity rules, then
> > chooses the highest-priority available sibling within that core. The
> > generic scheduler behavior is enabled only when an architecture supplies
> > an SD_ASYM_PACKING SMT domain.
> > 
> > PE0 and PE1 have equal steady-state capacity, the preference does not
> > identify a faster PE. PE0 is used only as a canonical choice when both
> > siblings are available. Consistently selecting the same sibling avoids
> > alternating the active PE across wakeups, lets PE1 remain idle for longer,
> > and allows more cores to remain in, or return to, full-resource
> > single-thread mode.
> > 
> > The series was tested on a two-node Vera system using an 88-thread
> > single-precision GEMM on the 88 physical cores of NUMA node 0.
> > 
> > With the workload allowed to choose either sibling of every core, observed
> > throughput improved from approximately 9.4 TFLOP/s on the baseline kernel
> > to approximately 10.1 TFLOP/s with this series applied. Repeated runs also
> > became more predictable because the workload consistently settled on PE0
> > while PE1 remained quiet.
> > 
> > Changes in v5:
> >  - Remove the redundant olympus_prefer_pe0 state (K Prateek Nayak)
> >  - Link to v4: https://lore.kernel.org/r/20260908082345.103087-1-arighi@nvidia.com
> 
> My replies failed to keep up with your speed on iterations :-)

Haha, sorry about that! :D

> 
> Since this is same as v4 and I had taken it for a spin on a
> x86 and an ARM64 server, feel free to include:
> 
> Reviewed-by: K Prateek Nayak <kprateek.nayak@amd.com>
> Tested-by: K Prateek Nayak <kprateek.nayak@amd.com>

And thanks!

-Andrea

Re: [PATCH v5 0/2] sched: Enable preferred SMT siblings on NVIDIA Olympus

[Peter Zijlstra]

On Wed, Sep 09, 2026 at 08:26:07AM +0200, Andrea Righi wrote:

> Andrea Righi (2):
>       arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores
>       sched/fair: Honor asymmetric SMT priority in idle selection
> 
>  arch/arm64/include/asm/topology.h |  1 +
>  arch/arm64/kernel/smp.c           |  1 +
>  arch/arm64/kernel/topology.c      | 51 +++++++++++++++++++++++
>  kernel/sched/fair.c               | 85 +++++++++++++++++++++++++++++++--------
>  kernel/sched/sched.h              |  6 +++
>  kernel/sched/topology.c           | 36 +++++++++++++++++
>  6 files changed, 163 insertions(+), 17 deletions(-)

I tentatively picked these up, but I need an arm64 ack before I can
merge them, and ideally vingu will bless them too :-)

Re: [PATCH 1/2] arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores

[Dietmar Eggemann]

On 09.09.26 08:26, Andrea Righi wrote:

[...]

> +void __init arm64_init_sched_topology(void)
> +{
> +	if (!IS_ENABLED(CONFIG_SCHED_SMT))
> +		return;
> +
> +	if ((read_cpuid_id() & MIDR_CPU_MODEL_MASK) != MIDR_NVIDIA_OLYMPUS)
> +		return;
> +
> +	if (!topology_core_has_smt(smp_processor_id()))
> +		return;
> +
> +	set_sched_topology(arm64_asym_smt_topology);
> +	pr_info("Enabling PE0 SMT preference for NVIDIA Olympus\n");

I'm not really a big fan of using this arm64 setup for NVIDIA Olympus
alone here.

> +}
> +
> +int arch_asym_cpu_priority(int cpu)
> +{
> +	return MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0) == 0;
> +}
> +

This is done since it will only be called for NVIDIA Olympus since it's
the only CPU model enabling this. I think it will work but it's still
ugly :-)

[...]

Re: [PATCH 1/2] arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores

[Will Deacon]

On Wed, Sep 09, 2026 at 08:26:08AM +0200, Andrea Righi wrote:
> diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
> index d28438f8b83f1..e5a7a4b2e3844 100644
> --- a/arch/arm64/kernel/topology.c
> +++ b/arch/arm64/kernel/topology.c
> @@ -19,6 +19,8 @@
>  #include <linux/init.h>
>  #include <linux/percpu.h>
>  #include <linux/sched/isolation.h>
> +#include <linux/sched/topology.h>
> +#include <linux/smp.h>
>  #include <linux/xarray.h>
>  
>  #include <asm/cpu.h>
> @@ -44,6 +46,55 @@
>  static DEFINE_PER_CPU_READ_MOSTLY(unsigned long, arch_max_freq_scale) =  1UL << (2 * SCHED_CAPACITY_SHIFT);
>  static cpumask_var_t amu_fie_cpus;
>  
> +/*
> + * Switching the active PE on an NVIDIA Olympus SMT core can keep the core in
> + * two-thread active mode, with resources partitioned between the PEs.
> + *
> + * Prefer PE0 so PE1 can remain idle and the core can stay in full-resource
> + * mode. Firmware does not currently describe this preference, so detect
> + * Olympus by MIDR until a firmware interface is available.
> + */

Fix the firmware?

If we add this MIDR kludge, I guarantee that it will never be fixed.

Will

Re: [PATCH v5 0/2] sched: Enable preferred SMT siblings on NVIDIA Olympus

[Will Deacon]

On Wed, Sep 09, 2026 at 03:14:15PM +0200, Peter Zijlstra wrote:
> On Wed, Sep 09, 2026 at 08:26:07AM +0200, Andrea Righi wrote:
> 
> > Andrea Righi (2):
> >       arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores
> >       sched/fair: Honor asymmetric SMT priority in idle selection
> > 
> >  arch/arm64/include/asm/topology.h |  1 +
> >  arch/arm64/kernel/smp.c           |  1 +
> >  arch/arm64/kernel/topology.c      | 51 +++++++++++++++++++++++
> >  kernel/sched/fair.c               | 85 +++++++++++++++++++++++++++++++--------
> >  kernel/sched/sched.h              |  6 +++
> >  kernel/sched/topology.c           | 36 +++++++++++++++++
> >  6 files changed, 163 insertions(+), 17 deletions(-)
> 
> I tentatively picked these up, but I need an arm64 ack before I can
> merge them, and ideally vingu will bless them too :-)

We've had five versions of this in five minutes, but the arch code is
pretty filthy tbh. Detecting topology based on MIDR is a non-starter,
sorry.

Will

Re: [PATCH 1/2] arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores

[Andrea Righi]

Hi Will,

On Wed, Sep 09, 2026 at 04:34:18PM +0100, Will Deacon wrote:
> On Wed, Sep 09, 2026 at 08:26:08AM +0200, Andrea Righi wrote:
> > diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
> > index d28438f8b83f1..e5a7a4b2e3844 100644
> > --- a/arch/arm64/kernel/topology.c
> > +++ b/arch/arm64/kernel/topology.c
> > @@ -19,6 +19,8 @@
> >  #include <linux/init.h>
> >  #include <linux/percpu.h>
> >  #include <linux/sched/isolation.h>
> > +#include <linux/sched/topology.h>
> > +#include <linux/smp.h>
> >  #include <linux/xarray.h>
> >  
> >  #include <asm/cpu.h>
> > @@ -44,6 +46,55 @@
> >  static DEFINE_PER_CPU_READ_MOSTLY(unsigned long, arch_max_freq_scale) =  1UL << (2 * SCHED_CAPACITY_SHIFT);
> >  static cpumask_var_t amu_fie_cpus;
> >  
> > +/*
> > + * Switching the active PE on an NVIDIA Olympus SMT core can keep the core in
> > + * two-thread active mode, with resources partitioned between the PEs.
> > + *
> > + * Prefer PE0 so PE1 can remain idle and the core can stay in full-resource
> > + * mode. Firmware does not currently describe this preference, so detect
> > + * Olympus by MIDR until a firmware interface is available.
> > + */
> 
> Fix the firmware?
> 
> If we add this MIDR kludge, I guarantee that it will never be fixed.

Understood. The existing PPTT already describes the SMT relationship, but as far
as I can tell ACPI doesn't currently provide a way to describe a preferred SMT
sibling. Both PEs also have equal isolated performance, so representing this
using different _CPC highest_perf values wouldn't accurately describe their
capacity.

I'll drop the MIDR-based enablement and coordinate with the firmware team on a
proper ABI.

In the meantime, for systems with the existing firmware, would an explicit
kernel boot option be acceptable as a fallback? It'd enable SD_ASYM_PACKING at
the SMT level and prefer the primary PE, but only when requested by the user;
the kernel would not infer this policy from the CPU model.

Other ideas?

Thanks,
-Andrea

Re: [PATCH 1/2] arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores

[Andrea Righi]

On Wed, Sep 09, 2026 at 05:19:08PM +0200, Dietmar Eggemann wrote:
> On 09.09.26 08:26, Andrea Righi wrote:
> 
> [...]
> 
> > +void __init arm64_init_sched_topology(void)
> > +{
> > +	if (!IS_ENABLED(CONFIG_SCHED_SMT))
> > +		return;
> > +
> > +	if ((read_cpuid_id() & MIDR_CPU_MODEL_MASK) != MIDR_NVIDIA_OLYMPUS)
> > +		return;
> > +
> > +	if (!topology_core_has_smt(smp_processor_id()))
> > +		return;
> > +
> > +	set_sched_topology(arm64_asym_smt_topology);
> > +	pr_info("Enabling PE0 SMT preference for NVIDIA Olympus\n");
> 
> I'm not really a big fan of using this arm64 setup for NVIDIA Olympus
> alone here.
> 
> > +}
> > +
> > +int arch_asym_cpu_priority(int cpu)
> > +{
> > +	return MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0) == 0;
> > +}
> > +
> 
> This is done since it will only be called for NVIDIA Olympus since it's
> the only CPU model enabling this. I think it will work but it's still
> ugly :-)
> 
> [...]
> 

Agreed on both points. As mentioned in the other email, I'll coordinate with the
firmware team on a proper ABI for describing the PE0 preference. For the systems
with the current firmware, I don't have many ideas on how to enable this... a
special scheduler facility enabled via kernel boot option? Other ideas?

Thanks,
-Andrea

Re: [PATCH v5 0/2] sched: Enable preferred SMT siblings on NVIDIA Olympus

[Peter Zijlstra]

On Wed, Sep 09, 2026 at 04:36:01PM +0100, Will Deacon wrote:
> On Wed, Sep 09, 2026 at 03:14:15PM +0200, Peter Zijlstra wrote:
> > On Wed, Sep 09, 2026 at 08:26:07AM +0200, Andrea Righi wrote:
> > 
> > > Andrea Righi (2):
> > >       arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores
> > >       sched/fair: Honor asymmetric SMT priority in idle selection
> > > 
> > >  arch/arm64/include/asm/topology.h |  1 +
> > >  arch/arm64/kernel/smp.c           |  1 +
> > >  arch/arm64/kernel/topology.c      | 51 +++++++++++++++++++++++
> > >  kernel/sched/fair.c               | 85 +++++++++++++++++++++++++++++++--------
> > >  kernel/sched/sched.h              |  6 +++
> > >  kernel/sched/topology.c           | 36 +++++++++++++++++
> > >  6 files changed, 163 insertions(+), 17 deletions(-)
> > 
> > I tentatively picked these up, but I need an arm64 ack before I can
> > merge them, and ideally vingu will bless them too :-)
> 
> We've had five versions of this in five minutes, but the arch code is
> pretty filthy tbh. Detecting topology based on MIDR is a non-starter,
> sorry.

Yeah, Andrea is a wee bit fast with re-posting. I'll drop this, no
worries.

Re: [PATCH 1/2] arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores

[Will Deacon]

On Wed, Sep 09, 2026 at 06:07:04PM +0200, Andrea Righi wrote:
> On Wed, Sep 09, 2026 at 04:34:18PM +0100, Will Deacon wrote:
> > On Wed, Sep 09, 2026 at 08:26:08AM +0200, Andrea Righi wrote:
> > > diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
> > > index d28438f8b83f1..e5a7a4b2e3844 100644
> > > --- a/arch/arm64/kernel/topology.c
> > > +++ b/arch/arm64/kernel/topology.c
> > > @@ -19,6 +19,8 @@
> > >  #include <linux/init.h>
> > >  #include <linux/percpu.h>
> > >  #include <linux/sched/isolation.h>
> > > +#include <linux/sched/topology.h>
> > > +#include <linux/smp.h>
> > >  #include <linux/xarray.h>
> > >  
> > >  #include <asm/cpu.h>
> > > @@ -44,6 +46,55 @@
> > >  static DEFINE_PER_CPU_READ_MOSTLY(unsigned long, arch_max_freq_scale) =  1UL << (2 * SCHED_CAPACITY_SHIFT);
> > >  static cpumask_var_t amu_fie_cpus;
> > >  
> > > +/*
> > > + * Switching the active PE on an NVIDIA Olympus SMT core can keep the core in
> > > + * two-thread active mode, with resources partitioned between the PEs.
> > > + *
> > > + * Prefer PE0 so PE1 can remain idle and the core can stay in full-resource
> > > + * mode. Firmware does not currently describe this preference, so detect
> > > + * Olympus by MIDR until a firmware interface is available.
> > > + */
> > 
> > Fix the firmware?
> > 
> > If we add this MIDR kludge, I guarantee that it will never be fixed.
> 
> Understood. The existing PPTT already describes the SMT relationship, but as far
> as I can tell ACPI doesn't currently provide a way to describe a preferred SMT
> sibling. Both PEs also have equal isolated performance, so representing this
> using different _CPC highest_perf values wouldn't accurately describe their
> capacity.
> 
> I'll drop the MIDR-based enablement and coordinate with the firmware team on a
> proper ABI.

Thanks, Andrea, I must confess that I wasn't expecting that!

> In the meantime, for systems with the existing firmware, would an explicit
> kernel boot option be acceptable as a fallback? It'd enable SD_ASYM_PACKING at
> the SMT level and prefer the primary PE, but only when requested by the user;
> the kernel would not infer this policy from the CPU model.

I'm ok with that.

Will

Re: [PATCH 1/2] arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores

[Dietmar Eggemann]

On 09.09.26 18:17, Andrea Righi wrote:
> On Wed, Sep 09, 2026 at 05:19:08PM +0200, Dietmar Eggemann wrote:
>> On 09.09.26 08:26, Andrea Righi wrote:
>>
>> [...]
>>
>>> +void __init arm64_init_sched_topology(void)
>>> +{
>>> +	if (!IS_ENABLED(CONFIG_SCHED_SMT))
>>> +		return;
>>> +
>>> +	if ((read_cpuid_id() & MIDR_CPU_MODEL_MASK) != MIDR_NVIDIA_OLYMPUS)
>>> +		return;
>>> +
>>> +	if (!topology_core_has_smt(smp_processor_id()))
>>> +		return;
>>> +
>>> +	set_sched_topology(arm64_asym_smt_topology);
>>> +	pr_info("Enabling PE0 SMT preference for NVIDIA Olympus\n");
>>
>> I'm not really a big fan of using this arm64 setup for NVIDIA Olympus
>> alone here.
>>
>>> +}
>>> +
>>> +int arch_asym_cpu_priority(int cpu)
>>> +{
>>> +	return MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0) == 0;
>>> +}
>>> +
>>
>> This is done since it will only be called for NVIDIA Olympus since it's
>> the only CPU model enabling this. I think it will work but it's still
>> ugly :-)
>>
>> [...]
>>
> 
> Agreed on both points. As mentioned in the other email, I'll coordinate with the
> firmware team on a proper ABI for describing the PE0 preference. For the systems
> with the current firmware, I don't have many ideas on how to enable this... a
> special scheduler facility enabled via kernel boot option? Other ideas?
With the explicit kernel boot time option discussed in the other thread,
how do you want to code arch_asym_cpu_priority()?

AFAIK, Arm architecture does not require the first/primary HW thread of
an SMT core to have MPIDR_EL1.Aff0 == 0.

The closest I came to you setup in Arm64 is a ThunderX2 SMT-4 machine on
which I can run 'OpenBLAS benchmark/sgemm.goto'. This machine has
symmetric CPU capacity though like Power7.
It has MPIDR_EL1.Aff0 == {0,1,2,3} for HW threads but '== 0' wouldn't
work here.

[...]

Re: [PATCH 1/2] arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores

[Andrea Righi]

On Thu, Sep 10, 2026 at 09:53:38AM +0100, Will Deacon wrote:
> On Wed, Sep 09, 2026 at 06:07:04PM +0200, Andrea Righi wrote:
> > On Wed, Sep 09, 2026 at 04:34:18PM +0100, Will Deacon wrote:
> > > On Wed, Sep 09, 2026 at 08:26:08AM +0200, Andrea Righi wrote:
> > > > diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
> > > > index d28438f8b83f1..e5a7a4b2e3844 100644
> > > > --- a/arch/arm64/kernel/topology.c
> > > > +++ b/arch/arm64/kernel/topology.c
> > > > @@ -19,6 +19,8 @@
> > > >  #include <linux/init.h>
> > > >  #include <linux/percpu.h>
> > > >  #include <linux/sched/isolation.h>
> > > > +#include <linux/sched/topology.h>
> > > > +#include <linux/smp.h>
> > > >  #include <linux/xarray.h>
> > > >  
> > > >  #include <asm/cpu.h>
> > > > @@ -44,6 +46,55 @@
> > > >  static DEFINE_PER_CPU_READ_MOSTLY(unsigned long, arch_max_freq_scale) =  1UL << (2 * SCHED_CAPACITY_SHIFT);
> > > >  static cpumask_var_t amu_fie_cpus;
> > > >  
> > > > +/*
> > > > + * Switching the active PE on an NVIDIA Olympus SMT core can keep the core in
> > > > + * two-thread active mode, with resources partitioned between the PEs.
> > > > + *
> > > > + * Prefer PE0 so PE1 can remain idle and the core can stay in full-resource
> > > > + * mode. Firmware does not currently describe this preference, so detect
> > > > + * Olympus by MIDR until a firmware interface is available.
> > > > + */
> > > 
> > > Fix the firmware?
> > > 
> > > If we add this MIDR kludge, I guarantee that it will never be fixed.
> > 
> > Understood. The existing PPTT already describes the SMT relationship, but as far
> > as I can tell ACPI doesn't currently provide a way to describe a preferred SMT
> > sibling. Both PEs also have equal isolated performance, so representing this
> > using different _CPC highest_perf values wouldn't accurately describe their
> > capacity.
> > 
> > I'll drop the MIDR-based enablement and coordinate with the firmware team on a
> > proper ABI.
> 
> Thanks, Andrea, I must confess that I wasn't expecting that!

I try to be a good citizen every now and then. :)

> 
> > In the meantime, for systems with the existing firmware, would an explicit
> > kernel boot option be acceptable as a fallback? It'd enable SD_ASYM_PACKING at
> > the SMT level and prefer the primary PE, but only when requested by the user;
> > the kernel would not infer this policy from the CPU model.
> 
> I'm ok with that.

Awesome! I'll work through Dietmar's point for this and post a new version
without the MIDR-based detection.

Thanks,
-Andrea

Re: [PATCH 1/2] arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores

[Andrea Righi]

Hi Dietmar,

On Thu, Sep 10, 2026 at 12:11:06PM +0200, Dietmar Eggemann wrote:
> On 09.09.26 18:17, Andrea Righi wrote:
> > On Wed, Sep 09, 2026 at 05:19:08PM +0200, Dietmar Eggemann wrote:
> >> On 09.09.26 08:26, Andrea Righi wrote:
> >>
> >> [...]
> >>
> >>> +void __init arm64_init_sched_topology(void)
> >>> +{
> >>> +	if (!IS_ENABLED(CONFIG_SCHED_SMT))
> >>> +		return;
> >>> +
> >>> +	if ((read_cpuid_id() & MIDR_CPU_MODEL_MASK) != MIDR_NVIDIA_OLYMPUS)
> >>> +		return;
> >>> +
> >>> +	if (!topology_core_has_smt(smp_processor_id()))
> >>> +		return;
> >>> +
> >>> +	set_sched_topology(arm64_asym_smt_topology);
> >>> +	pr_info("Enabling PE0 SMT preference for NVIDIA Olympus\n");
> >>
> >> I'm not really a big fan of using this arm64 setup for NVIDIA Olympus
> >> alone here.
> >>
> >>> +}
> >>> +
> >>> +int arch_asym_cpu_priority(int cpu)
> >>> +{
> >>> +	return MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0) == 0;
> >>> +}
> >>> +
> >>
> >> This is done since it will only be called for NVIDIA Olympus since it's
> >> the only CPU model enabling this. I think it will work but it's still
> >> ugly :-)
> >>
> >> [...]
> >>
> > 
> > Agreed on both points. As mentioned in the other email, I'll coordinate with the
> > firmware team on a proper ABI for describing the PE0 preference. For the systems
> > with the current firmware, I don't have many ideas on how to enable this... a
> > special scheduler facility enabled via kernel boot option? Other ideas?
> With the explicit kernel boot time option discussed in the other thread,
> how do you want to code arch_asym_cpu_priority()?

Good point.

I think we can avoid an arm64 override entirely and rely on the default
implementation:

int __weak arch_asym_cpu_priority(int cpu)
{
	return -cpu;
}

The boot option would only add SD_ASYM_PACKING to the SMT domain. A rough
prototype could look like this in kernel/sched/topology.c:

static bool sched_smt_asym_packing __read_mostly;

static int __init setup_sched_smt_asym_packing(char *str)
{
	sched_smt_asym_packing = true;
	return 1;
}
__setup("sched_smt_asym_packing", setup_sched_smt_asym_packing);

int cpu_smt_flags(void)
{
	int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_LLC;

	if (sched_smt_asym_packing)
		flags |= SD_ASYM_PACKING;

	return flags;
}

This would make the option generic rather than specific to arm64 or Olympus.

> 
> AFAIK, Arm architecture does not require the first/primary HW thread of
> an SMT core to have MPIDR_EL1.Aff0 == 0.

Agreed. Using the default -cpu ordering avoids making any assumptions about
MPIDR and consistently prefers the lowest-numbered logical CPU in each SMT
domain.

> 
> The closest I came to you setup in Arm64 is a ThunderX2 SMT-4 machine on
> which I can run 'OpenBLAS benchmark/sgemm.goto'. This machine has
> symmetric CPU capacity though like Power7.
> It has MPIDR_EL1.Aff0 == {0,1,2,3} for HW threads but '== 0' wouldn't
> work here.
> 
> [...]

Right, -cpu provides a total ordering for all threads, so this should provide
the expected sibling ordering on the ThunderX2 machine as well. If you're
willing to test the next version there, that would be very useful!

Thanks,
-Andrea