From: Andrea Righi <arighi@nvidia.com>
To: Will Deacon <will@kernel.org>
Cc: Ingo Molnar <mingo@redhat.com>,
Peter Zijlstra <peterz@infradead.org>,
Juri Lelli <juri.lelli@redhat.com>,
Vincent Guittot <vincent.guittot@linaro.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Dietmar Eggemann <dietmar.eggemann@arm.com>,
Steven Rostedt <rostedt@goodmis.org>,
Ben Segall <bsegall@google.com>, Mel Gorman <mgorman@suse.de>,
Valentin Schneider <vschneid@redhat.com>,
K Prateek Nayak <kprateek.nayak@amd.com>,
Mark Rutland <mark.rutland@arm.com>,
Christian Loehle <christian.loehle@arm.com>,
Shrikanth Hegde <sshegde@linux.ibm.com>,
Phil Auld <pauld@redhat.com>, Breno Leitao <leitao@debian.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores
Date: Fri, 11 Sep 2026 08:50:27 +0200 [thread overview]
Message-ID: <aqOksw5aoBDtuWI0@gpd4> (raw)
In-Reply-To: <aqJwEpnrmqnEzpui@willie-the-truck>
On Thu, Sep 10, 2026 at 09:53:38AM +0100, Will Deacon wrote:
> On Wed, Sep 09, 2026 at 06:07:04PM +0200, Andrea Righi wrote:
> > On Wed, Sep 09, 2026 at 04:34:18PM +0100, Will Deacon wrote:
> > > On Wed, Sep 09, 2026 at 08:26:08AM +0200, Andrea Righi wrote:
> > > > diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
> > > > index d28438f8b83f1..e5a7a4b2e3844 100644
> > > > --- a/arch/arm64/kernel/topology.c
> > > > +++ b/arch/arm64/kernel/topology.c
> > > > @@ -19,6 +19,8 @@
> > > > #include <linux/init.h>
> > > > #include <linux/percpu.h>
> > > > #include <linux/sched/isolation.h>
> > > > +#include <linux/sched/topology.h>
> > > > +#include <linux/smp.h>
> > > > #include <linux/xarray.h>
> > > >
> > > > #include <asm/cpu.h>
> > > > @@ -44,6 +46,55 @@
> > > > static DEFINE_PER_CPU_READ_MOSTLY(unsigned long, arch_max_freq_scale) = 1UL << (2 * SCHED_CAPACITY_SHIFT);
> > > > static cpumask_var_t amu_fie_cpus;
> > > >
> > > > +/*
> > > > + * Switching the active PE on an NVIDIA Olympus SMT core can keep the core in
> > > > + * two-thread active mode, with resources partitioned between the PEs.
> > > > + *
> > > > + * Prefer PE0 so PE1 can remain idle and the core can stay in full-resource
> > > > + * mode. Firmware does not currently describe this preference, so detect
> > > > + * Olympus by MIDR until a firmware interface is available.
> > > > + */
> > >
> > > Fix the firmware?
> > >
> > > If we add this MIDR kludge, I guarantee that it will never be fixed.
> >
> > Understood. The existing PPTT already describes the SMT relationship, but as far
> > as I can tell ACPI doesn't currently provide a way to describe a preferred SMT
> > sibling. Both PEs also have equal isolated performance, so representing this
> > using different _CPC highest_perf values wouldn't accurately describe their
> > capacity.
> >
> > I'll drop the MIDR-based enablement and coordinate with the firmware team on a
> > proper ABI.
>
> Thanks, Andrea, I must confess that I wasn't expecting that!
I try to be a good citizen every now and then. :)
>
> > In the meantime, for systems with the existing firmware, would an explicit
> > kernel boot option be acceptable as a fallback? It'd enable SD_ASYM_PACKING at
> > the SMT level and prefer the primary PE, but only when requested by the user;
> > the kernel would not infer this policy from the CPU model.
>
> I'm ok with that.
Awesome! I'll work through Dietmar's point for this and post a new version
without the MIDR-based detection.
Thanks,
-Andrea
next prev parent reply other threads:[~2026-09-11 6:50 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-09 6:26 [PATCH v5 0/2] sched: Enable preferred SMT siblings on NVIDIA Olympus Andrea Righi
2026-09-09 6:26 ` [PATCH 1/2] arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores Andrea Righi
2026-09-09 15:19 ` Dietmar Eggemann
2026-09-09 16:17 ` Andrea Righi
2026-09-10 10:11 ` Dietmar Eggemann
2026-09-11 9:11 ` Andrea Righi
2026-09-11 14:15 ` Dietmar Eggemann
2026-09-09 15:34 ` Will Deacon
2026-09-09 16:07 ` Andrea Righi
2026-09-10 8:53 ` Will Deacon
2026-09-11 6:50 ` Andrea Righi [this message]
2026-09-09 6:26 ` [PATCH 2/2] sched/fair: Honor asymmetric SMT priority in idle selection Andrea Righi
2026-09-11 14:11 ` Dietmar Eggemann
2026-09-09 6:36 ` [PATCH v5 0/2] sched: Enable preferred SMT siblings on NVIDIA Olympus K Prateek Nayak
2026-09-09 6:41 ` Andrea Righi
2026-09-09 13:14 ` Peter Zijlstra
2026-09-09 15:36 ` Will Deacon
2026-09-09 21:51 ` Peter Zijlstra
-- strict thread matches above, loose matches on Subject: below --
2026-09-08 8:23 [PATCH v4 " Andrea Righi
2026-09-08 8:23 ` [PATCH 1/2] arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores Andrea Righi
2026-09-08 20:09 ` K Prateek Nayak
2026-09-08 20:57 ` Andrea Righi
2026-09-07 16:30 [PATCH v3 0/2] sched: Enable preferred SMT siblings on NVIDIA Olympus Andrea Righi
2026-09-07 16:30 ` [PATCH 1/2] arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores Andrea Righi
2026-09-04 9:18 [PATCH v2 0/2] sched: Enable preferred SMT siblings on NVIDIA Olympus Andrea Righi
2026-09-04 9:18 ` [PATCH 1/2] arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores Andrea Righi
2026-08-31 18:10 [PATCH 0/2] sched: Enable preferred SMT siblings on NVIDIA Olympus Andrea Righi
2026-08-31 18:10 ` [PATCH 1/2] arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores Andrea Righi
2026-08-31 21:13 ` Christian Loehle
2026-08-31 21:43 ` Andrea Righi
2026-09-01 6:05 ` Andrea Righi
2026-09-01 8:32 ` Christian Loehle
2026-09-01 19:38 ` Andrea Righi
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