From: Will Deacon <will@kernel.org>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, "Will Deacon" <will@kernel.org>,
"Thomas Gleixner" <tglx@kernel.org>,
"Ben Horgan" <ben.horgan@arm.com>,
"Ștefania Ion" <stefion@google.com>,
"Catalin Marinas" <catalin.marinas@arm.com>,
"Pankaj Patil" <pankaj.patil@oss.qualcomm.com>,
"Borislav Petkov" <bp@alien8.de>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Jinjie Ruan" <ruanjinjie@huawei.com>,
"Mark Rutland" <mark.rutland@arm.com>,
"Tarun Sahu" <tarunsahu@google.com>,
"Fuad Tabba" <fuad.tabba@linux.dev>,
"David Woodhouse" <dwmw@amazon.co.uk>,
"Peter Zijlstra" <peterz@infradead.org>,
"Marc Zyngier" <maz@kernel.org>
Subject: [PATCH v2 21/23] arm64: smp: Pass secondary CPU boot parameters via firmware if possible
Date: Fri, 9 Oct 2026 11:07:32 +0100 [thread overview]
Message-ID: <20261009100738.31288-22-will@kernel.org> (raw)
In-Reply-To: <20261009100738.31288-1-will@kernel.org>
In preparation for parallel bringup of secondary CPUs, the global
'secondary_data' structure used for initial paramater passing must be
localised.
Pass the idle 'task_struct' pointer for secondary CPUs directly to
->cpu_boot() if the backend supports it.
Reviewed-by: Jinjie Ruan <ruanjinjie@huawei.com>
Signed-off-by: Will Deacon <will@kernel.org>
---
arch/arm64/include/asm/smp.h | 1 +
arch/arm64/kernel/head.S | 12 +++++++++++-
arch/arm64/kernel/psci.c | 4 ++--
arch/arm64/kernel/smp.c | 25 +++++++++++--------------
4 files changed, 25 insertions(+), 17 deletions(-)
diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h
index 7b986a6a765b..7f2cd84b7785 100644
--- a/arch/arm64/include/asm/smp.h
+++ b/arch/arm64/include/asm/smp.h
@@ -95,6 +95,7 @@ struct secondary_data {
extern struct secondary_data secondary_data;
extern long __early_cpu_boot_status;
extern void secondary_entry(void);
+extern void secondary_entry_with_arg(void);
extern void arch_send_call_function_single_ipi(int cpu);
extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 87a822e5c4ca..17868b497d7c 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -335,6 +335,7 @@ SYM_FUNC_END(init_kernel_el)
* cores are held until we're ready for them to initialise.
*/
SYM_FUNC_START(secondary_holding_pen)
+ mov x19, xzr
mov x0, xzr
bl init_kernel_el // w0=cpu_boot_mode
mrs x2, mpidr_el1
@@ -353,10 +354,16 @@ SYM_FUNC_END(secondary_holding_pen)
* be used where CPUs are brought online dynamically by the kernel.
*/
SYM_FUNC_START(secondary_entry)
+ mov x0, xzr
+ b secondary_entry_with_arg
+SYM_FUNC_END(secondary_entry)
+
+SYM_FUNC_START(secondary_entry_with_arg)
+ mov x19, x0
mov x0, xzr
bl init_kernel_el // w0=cpu_boot_mode
b secondary_startup
-SYM_FUNC_END(secondary_entry)
+SYM_FUNC_END(secondary_entry_with_arg)
SYM_FUNC_START_LOCAL(secondary_startup)
/*
@@ -391,10 +398,13 @@ SYM_FUNC_START_LOCAL(__secondary_switched)
msr vbar_el1, x5
isb
+ mov x2, x19
+ cbnz x2, 1f
adr_l x0, secondary_data
ldr x2, [x0, #CPU_BOOT_TASK]
cbz x2, __secondary_too_slow
+1:
init_cpu_task x2, x1, x3
#ifdef CONFIG_ARM64_PTR_AUTH
diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c
index 8cd74a77de2e..54aa91039b69 100644
--- a/arch/arm64/kernel/psci.c
+++ b/arch/arm64/kernel/psci.c
@@ -38,8 +38,8 @@ static int __init cpu_psci_cpu_prepare(unsigned int cpu)
static int cpu_psci_cpu_boot(unsigned int cpu, unsigned long context)
{
- phys_addr_t pa_secondary_entry = __pa_symbol(secondary_entry);
- int err = psci_ops.cpu_on(cpu_logical_map(cpu), pa_secondary_entry,
+ void *entry_va = context ? secondary_entry_with_arg : secondary_entry;
+ int err = psci_ops.cpu_on(cpu_logical_map(cpu), __pa_symbol(entry_va),
context);
if (err && err != -EPERM)
pr_err("failed to boot CPU%d (%d)\n", cpu, err);
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 29c70616a107..fb3a93090a3c 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -93,34 +93,31 @@ static inline int op_cpu_kill(unsigned int cpu)
}
#endif
-
/*
* Boot a secondary CPU, and assign it the specified idle task.
* This also gives us the initial stack to use for this CPU.
*/
-static int boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
- const struct cpu_operations *ops = get_secondary_cpu_ops();
-
- if (ops->cpu_boot)
- return ops->cpu_boot(cpu, 0);
-
- return -EOPNOTSUPP;
-}
-
int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *idle)
{
- int ret;
+ const struct cpu_operations *ops = get_secondary_cpu_ops();
+ int ret = -EOPNOTSUPP;
+ void *arg = NULL;
/*
* We need to tell the secondary core where to find its stack and the
* page tables.
*/
- secondary_data.task = idle;
+ if (ops->cpu_boot_has_arg && ops->cpu_boot_has_arg())
+ arg = idle;
+ else
+ secondary_data.task = idle;
+
update_cpu_boot_status(CPU_MMU_OFF);
/* Now bring the CPU into our world */
- ret = boot_secondary(cpu, idle);
+ if (ops->cpu_boot)
+ ret = ops->cpu_boot(cpu, (unsigned long)arg);
+
if (ret && ret != -EPERM)
pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
return ret;
--
2.56.0.385.gd3acb90ef8-goog
next prev parent reply other threads:[~2026-10-09 10:09 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-09 10:07 [PATCH v2 00/23] arm64: Implement parallel CPU onlining with PSCI v0.2+ Will Deacon
2026-10-09 10:07 ` [PATCH v2 01/23] cpu/hotplug: Clean up cmpxchg() logic in cpuhp_can_boot_ap() Will Deacon
2026-10-09 10:07 ` [PATCH v2 02/23] cpu/hotplug: Avoid trying to bring up CPUs that are already online Will Deacon
2026-10-09 10:07 ` [PATCH v2 03/23] cpu/hotplug: Avoid busy-polling on archs where cpu_relax() is a no-op Will Deacon
2026-10-09 10:46 ` David Woodhouse
2026-10-09 11:07 ` Will Deacon
2026-10-09 10:07 ` [PATCH v2 04/23] cpu/hotplug: Propagate bring-up status to arch_cpuhp_cleanup_kick_cpu() Will Deacon
2026-10-09 10:07 ` [PATCH v2 05/23] arm64: cpufeature: Check arm64_ftr_regs[] before the first store Will Deacon
2026-10-09 10:07 ` [PATCH v2 06/23] arm64: cpufeature: Add read_cpuid_with_overrides() Will Deacon
2026-10-09 10:07 ` [PATCH v2 07/23] arm64: cpufeature: Read MPAMIDR_EL1 in __cpuinfo_store_cpu() Will Deacon
2026-10-09 15:44 ` Ben Horgan
2026-10-09 10:07 ` [PATCH v2 08/23] arm64: cpufeature: Store every ID register with its overrides applied Will Deacon
2026-10-09 15:51 ` Ben Horgan
2026-10-09 10:07 ` [PATCH v2 09/23] arm64: smp: Tidy up smp_prepare_cpus() Will Deacon
2026-10-09 10:07 ` [PATCH v2 10/23] arm64: smp: Tidy up cpuinfo init and cpufeature updates Will Deacon
2026-10-09 10:07 ` [PATCH v2 11/23] arm64: smp: Defer update of secondary CPU capabilities Will Deacon
2026-10-09 10:07 ` [PATCH v2 12/23] arm64: smp: Don't bother printing the I-cache policy for each CPU Will Deacon
2026-10-09 10:07 ` [PATCH v2 13/23] arm64: smp: Defer RCU registration during secondary CPU bringup Will Deacon
2026-10-09 10:07 ` [PATCH v2 14/23] arm64: smp: Use generic HOTPLUG_CORE_SYNC_FULL machinery for CPU onlining Will Deacon
2026-10-09 10:07 ` [PATCH v2 15/23] arm64: smp: Use generic HOTPLUG_SPLIT_STARTUP " Will Deacon
2026-10-09 10:07 ` [PATCH v2 16/23] arm64: cpu_ops: Make 'cpu_operations' pointer global instead of per-cpu Will Deacon
2026-10-09 10:07 ` [PATCH v2 17/23] arm64: cpu_ops: Introduce get_secondary_cpu_ops() Will Deacon
2026-10-09 10:07 ` [PATCH v2 18/23] firmware/psci: Cache PSCI v0.2+ version number to avoid redundant SMCs Will Deacon
2026-10-09 10:07 ` [PATCH v2 19/23] firmware/psci: Extend ->cpu_on() callback to take an additional argument Will Deacon
2026-10-09 10:07 ` [PATCH v2 20/23] arm64: cpu_ops: Expose optional argument to target cpu in ->cpu_boot() Will Deacon
2026-10-09 10:07 ` Will Deacon [this message]
2026-10-09 10:07 ` [PATCH v2 22/23] arm64: smp: Use generic HOTPLUG_PARALLEL machinery for CPU onlining Will Deacon
2026-10-09 10:07 ` [PATCH v2 23/23] arm64: smp: Harden parallel CPU bringup against broken PSCI firmware Will Deacon
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