[PATCH 0/8] riscv: add OpenHW Group CVA6 APU on Digilent Genesys 2

[PATCH 0/8] riscv: add OpenHW Group CVA6 APU on Digilent Genesys 2

[marouene.boubakri]

From: Marouene Boubakri <marouene.boubakri@oss.nxp.com>

This series adds support for the OpenHW Group CVA6 APU, the FPGA SoC
built around the CVA6 core (https://github.com/openhwgroup/cva6,
corev_apu/fpga, release v5.3.0), running on the Digilent Genesys 2.

Both configurations of the core built for this board are covered: the
64-bit cv64a6 (rv64imafdc plus B, Zcb, Zicond and Zkn, Sv39, 1 GiB) and
the 32-bit cv32a6 (rv32ima, Sv32, 128 MiB). The SoC description is
shared in a dtsi and the two board .dts files only carry the core
specific properties and the memory size.

The peripherals use existing bindings: 8250 UART, Xilinx SPI with an
mmc-spi-slot, Xilinx GPIO with gpio-leds, SiFive compatible CLINT and
PLIC. Patches 1 to 5 add the vendor prefix and the compatible strings
these bindings need, patch 6 the ARCH_OPENHWGROUP Kconfig option,
patch 7 the device trees and the MAINTAINERS entry, patch 8 enables the
platform in the defconfig.

The lowRISC Ethernet controller and the PULP timer of the platform have
no upstream bindings yet and are left out of the device trees.

The device trees have been validated with dtbs_check. The cv64a6
configuration has been booted on the Genesys 2 from U-Boot 2026.10 with
the board support submitted to U-Boot, using the same device tree
content as this series. The cv32a6 configuration is build tested.

Marouene Boubakri (8):
  dt-bindings: vendor-prefixes: add OpenHW Group
  dt-bindings: riscv: cpus: add OpenHW Group CVA6 compatibles
  dt-bindings: timer: sifive,clint: add OpenHW Group CVA6 APU
  dt-bindings: interrupt-controller: sifive,plic: add OpenHW Group CVA6
    APU
  dt-bindings: riscv: add OpenHW Group CVA6 APU boards
  riscv: add ARCH_OPENHWGROUP Kconfig option
  riscv: dts: openhwgroup: add CVA6 APU on Digilent Genesys 2
  riscv: defconfig: enable OpenHW Group CVA6 APU support

 .../sifive,plic-1.0.0.yaml                    |   1 +
 .../devicetree/bindings/riscv/cpus.yaml       |   2 +
 .../bindings/riscv/openhwgroup.yaml           |  30 +++++
 .../bindings/timer/sifive,clint.yaml          |   1 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 MAINTAINERS                                   |   7 +
 arch/riscv/Kconfig.socs                       |   6 +
 arch/riscv/boot/dts/Makefile                  |   1 +
 arch/riscv/boot/dts/openhwgroup/Makefile      |   2 +
 .../boot/dts/openhwgroup/cv32a6-genesys2.dts  |  29 +++++
 .../boot/dts/openhwgroup/cv64a6-genesys2.dts  |  31 +++++
 .../boot/dts/openhwgroup/cva6-genesys2.dtsi   | 123 ++++++++++++++++++
 arch/riscv/configs/defconfig                  |   3 +
 13 files changed, 238 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/openhwgroup.yaml
 create mode 100644 arch/riscv/boot/dts/openhwgroup/Makefile
 create mode 100644 arch/riscv/boot/dts/openhwgroup/cv32a6-genesys2.dts
 create mode 100644 arch/riscv/boot/dts/openhwgroup/cv64a6-genesys2.dts
 create mode 100644 arch/riscv/boot/dts/openhwgroup/cva6-genesys2.dtsi

-- 
2.43.0

[PATCH 1/8] dt-bindings: vendor-prefixes: add OpenHW Group

[marouene.boubakri]

From: Marouene Boubakri <marouene.boubakri@oss.nxp.com>

The OpenHW Group (https://www.openhwgroup.org) maintains the CORE-V
family of open source RISC-V cores, including the CVA6 application
class core and the CVA6 APU FPGA platform built around it.

Signed-off-by: Marouene Boubakri <marouene.boubakri@oss.nxp.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index ba20029693..82440d498d 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1263,6 +1263,8 @@ patternProperties:
     description: OpenCores.org
   "^openembed,.*":
     description: OpenEmbed
+  "^openhwgroup,.*":
+    description: OpenHW Group
   "^openpandora,.*":
     description: OpenPandora GmbH
   "^openrisc,.*":
-- 
2.43.0

Re: [PATCH 1/8] dt-bindings: vendor-prefixes: add OpenHW Group

[Conor Dooley]

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On Mon, Nov 02, 2026 at 03:17:20PM +0100, marouene.boubakri@oss.nxp.com wrote:
> From: Marouene Boubakri <marouene.boubakri@oss.nxp.com>
> 
> The OpenHW Group (https://www.openhwgroup.org) maintains the CORE-V
> family of open source RISC-V cores, including the CVA6 application
> class core and the CVA6 APU FPGA platform built around it.
> 
> Signed-off-by: Marouene Boubakri <marouene.boubakri@oss.nxp.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

> ---
>  Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index ba20029693..82440d498d 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -1263,6 +1263,8 @@ patternProperties:
>      description: OpenCores.org
>    "^openembed,.*":
>      description: OpenEmbed
> +  "^openhwgroup,.*":
> +    description: OpenHW Group
>    "^openpandora,.*":
>      description: OpenPandora GmbH
>    "^openrisc,.*":
> -- 
> 2.43.0
> 

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[PATCH 2/8] dt-bindings: riscv: cpus: add OpenHW Group CVA6 compatibles

[marouene.boubakri]

From: Marouene Boubakri <marouene.boubakri@oss.nxp.com>

Add the compatible strings for the two configurations of the OpenHW
Group CVA6 application class core: the 64-bit cv64a6 and the 32-bit
cv32a6.

Signed-off-by: Marouene Boubakri <marouene.boubakri@oss.nxp.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 0da219ae67..81c3a6cf91 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -49,6 +49,8 @@ properties:
               - andestech,ax45mp
               - canaan,k210
               - nuclei,ux900
+              - openhwgroup,cv32a6
+              - openhwgroup,cv64a6
               - sifive,bullet0
               - sifive,e5
               - sifive,e7
-- 
2.43.0

Re: [PATCH 2/8] dt-bindings: riscv: cpus: add OpenHW Group CVA6 compatibles

[Conor Dooley]

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Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

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[PATCH 3/8] dt-bindings: timer: sifive,clint: add OpenHW Group CVA6 APU

[marouene.boubakri]

From: Marouene Boubakri <marouene.boubakri@oss.nxp.com>

The CVA6 APU FPGA platform integrates a CLINT compatible with the SiFive
CLINT v0. Add its compatible string.

Signed-off-by: Marouene Boubakri <marouene.boubakri@oss.nxp.com>
---
 Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index 3673836e14..467a1e26de 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -32,6 +32,7 @@ properties:
               - canaan,k210-clint       # Canaan Kendryte K210
               - eswin,eic7700-clint     # ESWIN EIC7700
               - microchip,pic64gx-clint # Microchip PIC64GX
+              - openhwgroup,cva6-clint  # OpenHW Group CVA6 APU
               - sifive,fu540-c000-clint # SiFive FU540
               - spacemit,k1-clint       # SpacemiT K1
               - spacemit,k3-clint       # SpacemiT K3
-- 
2.43.0

Re: [PATCH 3/8] dt-bindings: timer: sifive,clint: add OpenHW Group CVA6 APU

[Conor Dooley]

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Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

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[PATCH 4/8] dt-bindings: interrupt-controller: sifive,plic: add OpenHW Group CVA6 APU

[marouene.boubakri]

From: Marouene Boubakri <marouene.boubakri@oss.nxp.com>

The CVA6 APU FPGA platform integrates a PLIC compatible with the SiFive
PLIC 1.0.0. Add its compatible string.

Signed-off-by: Marouene Boubakri <marouene.boubakri@oss.nxp.com>
---
 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index cde4bb6918..00ad63ab0f 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -62,6 +62,7 @@ properties:
               - canaan,k210-plic
               - eswin,eic7700-plic
               - microchip,pic64gx-plic
+              - openhwgroup,cva6-plic
               - sifive,fu540-c000-plic
               - spacemit,k1-plic
               - starfive,jh7100-plic
-- 
2.43.0

Re: [PATCH 4/8] dt-bindings: interrupt-controller: sifive,plic: add OpenHW Group CVA6 APU

[Conor Dooley]

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Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

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[PATCH 5/8] dt-bindings: riscv: add OpenHW Group CVA6 APU boards

[marouene.boubakri]

From: Marouene Boubakri <marouene.boubakri@oss.nxp.com>

The CVA6 APU is the FPGA SoC built around the OpenHW Group CVA6 core in
the CVA6 repository (corev_apu/fpga). Add the board compatible strings
for its Digilent Genesys 2 builds with the 32-bit (cv32a6) and the
64-bit (cv64a6) configurations of the core.

Signed-off-by: Marouene Boubakri <marouene.boubakri@oss.nxp.com>
---
 .../bindings/riscv/openhwgroup.yaml           | 30 +++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/openhwgroup.yaml

diff --git a/Documentation/devicetree/bindings/riscv/openhwgroup.yaml b/Documentation/devicetree/bindings/riscv/openhwgroup.yaml
new file mode 100644
index 0000000000..3bca66cad5
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/openhwgroup.yaml
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/openhwgroup.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: OpenHW Group SoC-based boards
+
+maintainers:
+  - Marouene Boubakri <marouene.boubakri@oss.nxp.com>
+
+description:
+  OpenHW Group SoC-based boards. The CVA6 APU is the FPGA SoC built around
+  the CVA6 core in the CVA6 repository (corev_apu/fpga).
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: CVA6 APU on the Digilent Genesys 2 board
+        items:
+          - enum:
+              - openhwgroup,cv32a6-genesys2
+              - openhwgroup,cv64a6-genesys2
+          - const: openhwgroup,cva6-apu
+
+additionalProperties: true
+
+...
-- 
2.43.0

Re: [PATCH 5/8] dt-bindings: riscv: add OpenHW Group CVA6 APU boards

[Conor Dooley]

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On Mon, Nov 02, 2026 at 03:17:24PM +0100, marouene.boubakri@oss.nxp.com wrote:
> From: Marouene Boubakri <marouene.boubakri@oss.nxp.com>
> 
> The CVA6 APU is the FPGA SoC built around the OpenHW Group CVA6 core in
> the CVA6 repository (corev_apu/fpga). Add the board compatible strings
> for its Digilent Genesys 2 builds with the 32-bit (cv32a6) and the
> 64-bit (cv64a6) configurations of the core.
> 
> Signed-off-by: Marouene Boubakri <marouene.boubakri@oss.nxp.com>
> ---
>  .../bindings/riscv/openhwgroup.yaml           | 30 +++++++++++++++++++
>  1 file changed, 30 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/openhwgroup.yaml
> 
> diff --git a/Documentation/devicetree/bindings/riscv/openhwgroup.yaml b/Documentation/devicetree/bindings/riscv/openhwgroup.yaml
> new file mode 100644
> index 0000000000..3bca66cad5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/openhwgroup.yaml
> @@ -0,0 +1,30 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/openhwgroup.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: OpenHW Group SoC-based boards
> +
> +maintainers:
> +  - Marouene Boubakri <marouene.boubakri@oss.nxp.com>
> +
> +description:
> +  OpenHW Group SoC-based boards. The CVA6 APU is the FPGA SoC built around
> +  the CVA6 core in the CVA6 repository (corev_apu/fpga).
> +
> +properties:
> +  $nodename:
> +    const: '/'
> +  compatible:
> +    oneOf:
> +      - description: CVA6 APU on the Digilent Genesys 2 board
> +        items:
> +          - enum:
> +              - openhwgroup,cv32a6-genesys2
> +              - openhwgroup,cv64a6-genesys2
> +          - const: openhwgroup,cva6-apu

On riscv, the rule for platforms implemented on FPGAs is that they must
be strictly versioned and match with some clear and obvious release from
the vendor. In your case, this should be easy, because you have github
releases of the platform to match with.

pw-bot: changes-requested

Thanks,
Conor.

> +
> +additionalProperties: true
> +
> +...
> -- 
> 2.43.0
> 

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[PATCH 6/8] riscv: add ARCH_OPENHWGROUP Kconfig option

[marouene.boubakri]

From: Marouene Boubakri <marouene.boubakri@oss.nxp.com>

Add the SoC selection entry for OpenHW Group platforms, which is used
to build the device trees of the CVA6 APU FPGA platform.

Signed-off-by: Marouene Boubakri <marouene.boubakri@oss.nxp.com>
---
 arch/riscv/Kconfig.socs | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index cecbce0c49..289448e489 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -26,6 +26,15 @@ config ARCH_MICROCHIP
 	help
 	  This enables support for Microchip SoC platforms.
 
+config ARCH_OPENHWGROUP
+	bool "OpenHW Group SoCs"
+	help
+	  This enables support for OpenHW Group SoC platform hardware.
+	  Current support is for the CVA6 APU, the FPGA platform built
+	  around the CVA6 application class core, with the 32-bit (cv32a6)
+	  and 64-bit (cv64a6) configurations of the core on the Digilent
+	  Genesys 2 board.
+
 config ARCH_RENESAS
 	bool "Renesas RISC-V SoCs"
 	help
-- 
2.43.0

Re: [PATCH 6/8] riscv: add ARCH_OPENHWGROUP Kconfig option

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1239 bytes --]

On Mon, Nov 02, 2026 at 03:17:25PM +0100, marouene.boubakri@oss.nxp.com wrote:
> From: Marouene Boubakri <marouene.boubakri@oss.nxp.com>
> 
> Add the SoC selection entry for OpenHW Group platforms, which is used
> to build the device trees of the CVA6 APU FPGA platform.
> 
> Signed-off-by: Marouene Boubakri <marouene.boubakri@oss.nxp.com>
> ---
>  arch/riscv/Kconfig.socs | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index cecbce0c49..289448e489 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -26,6 +26,15 @@ config ARCH_MICROCHIP
>  	help
>  	  This enables support for Microchip SoC platforms.
>  
> +config ARCH_OPENHWGROUP
> +	bool "OpenHW Group SoCs"
> +	help
> +	  This enables support for OpenHW Group SoC platform hardware.

> +	  Current support is for the CVA6 APU, the FPGA platform built
> +	  around the CVA6 application class core, with the 32-bit (cv32a6)
> +	  and 64-bit (cv64a6) configurations of the core on the Digilent
> +	  Genesys 2 board.

Delete all this, it'll just bitrot over time.

> +
>  config ARCH_RENESAS
>  	bool "Renesas RISC-V SoCs"
>  	help
> -- 
> 2.43.0
> 

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[PATCH 7/8] riscv: dts: openhwgroup: add CVA6 APU on Digilent Genesys 2

[marouene.boubakri]

From: Marouene Boubakri <marouene.boubakri@oss.nxp.com>

The CVA6 APU is the FPGA SoC built around the OpenHW Group CVA6 core in
the CVA6 repository (corev_apu/fpga, release v5.3.0). It targets the
Digilent Genesys 2 board and provides a CLINT, a PLIC, a 16550 UART, a
Xilinx SPI controller connected to the SD card slot and a Xilinx GPIO
block driving the LEDs.

Describe the SoC in cva6-genesys2.dtsi, shared by the two configurations
of the core that the FPGA platform builds, and add a board device tree
for each of them:

  - cv64a6: rv64imafdc with the B, Zcb, Zicond and Zkn extensions,
    Sv39, 1 GiB of DDR3
  - cv32a6: rv32ima, Sv32, 128 MiB of DDR3

The ISA extensions follow the core configurations of CVA6 v5.3.0
(core/include/cv64a6_imafdc_sv39_config_pkg.sv and
cv32a6_ima_sv32_fpga_config_pkg.sv).

The platform also has a lowRISC Ethernet controller and a PULP APB
timer. They are left out until bindings exist for them.

Signed-off-by: Marouene Boubakri <marouene.boubakri@oss.nxp.com>
---
 MAINTAINERS                                   |   7 +
 arch/riscv/boot/dts/Makefile                  |   1 +
 arch/riscv/boot/dts/openhwgroup/Makefile      |   2 +
 .../boot/dts/openhwgroup/cv32a6-genesys2.dts  |  29 ++++
 .../boot/dts/openhwgroup/cv64a6-genesys2.dts  |  31 +++++
 .../boot/dts/openhwgroup/cva6-genesys2.dtsi   | 131 ++++++++++++++++++
 6 files changed, 201 insertions(+)
 create mode 100644 arch/riscv/boot/dts/openhwgroup/Makefile
 create mode 100644 arch/riscv/boot/dts/openhwgroup/cv32a6-genesys2.dts
 create mode 100644 arch/riscv/boot/dts/openhwgroup/cv64a6-genesys2.dts
 create mode 100644 arch/riscv/boot/dts/openhwgroup/cva6-genesys2.dtsi

diff --git a/MAINTAINERS b/MAINTAINERS
index 782389bd5c..17865074a2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -23566,6 +23566,13 @@ T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
 F:	arch/riscv/boot/dts/canaan/
 F:	arch/riscv/boot/dts/sifive/
 
+RISC-V OPENHW GROUP SoC SUPPORT
+M:	Marouene Boubakri <marouene.boubakri@oss.nxp.com>
+L:	linux-riscv@lists.infradead.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/riscv/openhwgroup.yaml
+F:	arch/riscv/boot/dts/openhwgroup/
+
 RISC-V PMU DRIVERS
 M:	Atish Patra <atish.patra@linux.dev>
 R:	Anup Patel <anup@brainfault.org>
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 69d8751fb1..305a93ad6f 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -5,6 +5,7 @@ subdir-y += anlogic
 subdir-y += canaan
 subdir-y += eswin
 subdir-y += microchip
+subdir-y += openhwgroup
 subdir-y += renesas
 subdir-y += sifive
 subdir-y += sophgo
diff --git a/arch/riscv/boot/dts/openhwgroup/Makefile b/arch/riscv/boot/dts/openhwgroup/Makefile
new file mode 100644
index 0000000000..a75a5863b7
--- /dev/null
+++ b/arch/riscv/boot/dts/openhwgroup/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_OPENHWGROUP) += cv32a6-genesys2.dtb cv64a6-genesys2.dtb
diff --git a/arch/riscv/boot/dts/openhwgroup/cv32a6-genesys2.dts b/arch/riscv/boot/dts/openhwgroup/cv32a6-genesys2.dts
new file mode 100644
index 0000000000..83d0286171
--- /dev/null
+++ b/arch/riscv/boot/dts/openhwgroup/cv32a6-genesys2.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright 2026 NXP
+ *
+ * OpenHW Group CVA6 APU, 32-bit core (cv32a6), on the Digilent Genesys 2.
+ */
+
+/dts-v1/;
+
+#include "cva6-genesys2.dtsi"
+
+/ {
+	model = "OpenHW Group CVA6 cv32a6 on Digilent Genesys 2";
+	compatible = "openhwgroup,cv32a6-genesys2", "openhwgroup,cva6-apu";
+
+	memory@80000000 {
+		device_type = "memory";
+		/* 128 MiB of DDR3, as configured for this core by the FPGA build */
+		reg = <0x0 0x80000000 0x0 0x8000000>;
+	};
+};
+
+&cpu0 {
+	compatible = "openhwgroup,cv32a6", "riscv";
+	riscv,isa-base = "rv32i";
+	riscv,isa-extensions = "i", "m", "a", "zicntr", "zicsr", "zifencei",
+			       "zihpm";
+	mmu-type = "riscv,sv32";
+};
diff --git a/arch/riscv/boot/dts/openhwgroup/cv64a6-genesys2.dts b/arch/riscv/boot/dts/openhwgroup/cv64a6-genesys2.dts
new file mode 100644
index 0000000000..8fe653b35c
--- /dev/null
+++ b/arch/riscv/boot/dts/openhwgroup/cv64a6-genesys2.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright 2026 NXP
+ *
+ * OpenHW Group CVA6 APU, 64-bit core (cv64a6), on the Digilent Genesys 2.
+ */
+
+/dts-v1/;
+
+#include "cva6-genesys2.dtsi"
+
+/ {
+	model = "OpenHW Group CVA6 cv64a6 on Digilent Genesys 2";
+	compatible = "openhwgroup,cv64a6-genesys2", "openhwgroup,cva6-apu";
+
+	memory@80000000 {
+		device_type = "memory";
+		/* 1 GiB of DDR3, as configured for this core by the FPGA build */
+		reg = <0x0 0x80000000 0x0 0x40000000>;
+	};
+};
+
+&cpu0 {
+	compatible = "openhwgroup,cv64a6", "riscv";
+	riscv,isa-base = "rv64i";
+	riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "zba",
+			       "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs",
+			       "zca", "zcb", "zcd", "zicntr", "zicond", "zicsr",
+			       "zifencei", "zihpm", "zknd", "zkne", "zknh";
+	mmu-type = "riscv,sv39";
+};
diff --git a/arch/riscv/boot/dts/openhwgroup/cva6-genesys2.dtsi b/arch/riscv/boot/dts/openhwgroup/cva6-genesys2.dtsi
new file mode 100644
index 0000000000..95978274a7
--- /dev/null
+++ b/arch/riscv/boot/dts/openhwgroup/cva6-genesys2.dtsi
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+/*
+ * Copyright 2026 NXP
+ *
+ * OpenHW Group CVA6 APU on the Digilent Genesys 2 FPGA board.
+ *
+ * The SoC description is shared between the 32-bit (cv32a6) and the
+ * 64-bit (cv64a6) configurations of the CVA6 core. The core specific
+ * properties and the memory size are set in the board .dts files.
+ */
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		/* The CLINT mtime counter runs at half the core clock */
+		timebase-frequency = <25000000>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			clock-frequency = <50000000>;
+			tlb-split;
+
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+	};
+
+	/* Peripheral clock, the same as the core clock */
+	clk50: clock-50mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <50000000>;
+		clock-output-names = "clk50";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			gpios = <&gpio0 1 0>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+
+		clint: clint@2000000 {
+			compatible = "openhwgroup,cva6-clint", "sifive,clint0";
+			reg = <0x0 0x2000000 0x0 0xc0000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+		};
+
+		plic: interrupt-controller@c000000 {
+			compatible = "openhwgroup,cva6-plic", "sifive,plic-1.0.0";
+			reg = <0x0 0xc000000 0x0 0x4000000>;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+			riscv,ndev = <30>;
+		};
+
+		uart0: serial@10000000 {
+			compatible = "ns16550a";
+			reg = <0x0 0x10000000 0x0 0x1000>;
+			clock-frequency = <50000000>;
+			interrupt-parent = <&plic>;
+			interrupts = <1>;
+			/* Registers are 32-bit wide and 32-bit aligned */
+			reg-shift = <2>;
+			reg-io-width = <4>;
+		};
+
+		spi0: spi@20000000 {
+			compatible = "xlnx,xps-spi-2.00.a";
+			reg = <0x0 0x20000000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupt-parent = <&plic>;
+			interrupts = <2>;
+			xlnx,num-ss-bits = <1>;
+			xlnx,num-transfer-bits = <8>;
+
+			mmc@0 {
+				compatible = "mmc-spi-slot";
+				reg = <0>;
+				spi-max-frequency = <12500000>;
+				voltage-ranges = <3300 3300>;
+				disable-wp;
+			};
+		};
+
+		gpio0: gpio@40000000 {
+			compatible = "xlnx,xps-gpio-1.00.a";
+			reg = <0x0 0x40000000 0x0 0x10000>;
+			clocks = <&clk50>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			xlnx,all-inputs = <0>;
+			xlnx,all-inputs-2 = <0>;
+			xlnx,dout-default = <0>;
+			xlnx,dout-default-2 = <0>;
+			xlnx,gpio-width = <8>;
+			xlnx,gpio2-width = <8>;
+			xlnx,interrupt-present = <0>;
+			xlnx,is-dual = <1>;
+			xlnx,tri-default = <0xffffffff>;
+			xlnx,tri-default-2 = <0xffffffff>;
+		};
+	};
+};
-- 
2.43.0

Re: [PATCH 7/8] riscv: dts: openhwgroup: add CVA6 APU on Digilent Genesys 2

[Conor Dooley]

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On Mon, Nov 02, 2026 at 03:17:26PM +0100, marouene.boubakri@oss.nxp.com wrote:
> From: Marouene Boubakri <marouene.boubakri@oss.nxp.com>
> 
> The CVA6 APU is the FPGA SoC built around the OpenHW Group CVA6 core in
> the CVA6 repository (corev_apu/fpga, release v5.3.0). It targets the
> Digilent Genesys 2 board and provides a CLINT, a PLIC, a 16550 UART, a
> Xilinx SPI controller connected to the SD card slot and a Xilinx GPIO
> block driving the LEDs.
> 
> Describe the SoC in cva6-genesys2.dtsi, shared by the two configurations
> of the core that the FPGA platform builds, and add a board device tree
> for each of them:
> 
>   - cv64a6: rv64imafdc with the B, Zcb, Zicond and Zkn extensions,
>     Sv39, 1 GiB of DDR3
>   - cv32a6: rv32ima, Sv32, 128 MiB of DDR3
> 
> The ISA extensions follow the core configurations of CVA6 v5.3.0
> (core/include/cv64a6_imafdc_sv39_config_pkg.sv and
> cv32a6_ima_sv32_fpga_config_pkg.sv).
> 
> The platform also has a lowRISC Ethernet controller and a PULP APB
> timer. They are left out until bindings exist for them.
> 
> Signed-off-by: Marouene Boubakri <marouene.boubakri@oss.nxp.com>
> ---
>  MAINTAINERS                                   |   7 +
>  arch/riscv/boot/dts/Makefile                  |   1 +
>  arch/riscv/boot/dts/openhwgroup/Makefile      |   2 +
>  .../boot/dts/openhwgroup/cv32a6-genesys2.dts  |  29 ++++
>  .../boot/dts/openhwgroup/cv64a6-genesys2.dts  |  31 +++++
>  .../boot/dts/openhwgroup/cva6-genesys2.dtsi   | 131 ++++++++++++++++++
>  6 files changed, 201 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/openhwgroup/Makefile
>  create mode 100644 arch/riscv/boot/dts/openhwgroup/cv32a6-genesys2.dts
>  create mode 100644 arch/riscv/boot/dts/openhwgroup/cv64a6-genesys2.dts
>  create mode 100644 arch/riscv/boot/dts/openhwgroup/cva6-genesys2.dtsi
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 782389bd5c..17865074a2 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -23566,6 +23566,13 @@ T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
>  F:	arch/riscv/boot/dts/canaan/
>  F:	arch/riscv/boot/dts/sifive/
>  
> +RISC-V OPENHW GROUP SoC SUPPORT
> +M:	Marouene Boubakri <marouene.boubakri@oss.nxp.com>
> +L:	linux-riscv@lists.infradead.org
> +S:	Maintained
> +F:	Documentation/devicetree/bindings/riscv/openhwgroup.yaml
> +F:	arch/riscv/boot/dts/openhwgroup/

There's no git tree here, are you expecting me to apply the patches for
your platform?

> +
>  RISC-V PMU DRIVERS
>  M:	Atish Patra <atish.patra@linux.dev>
>  R:	Anup Patel <anup@brainfault.org>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index 69d8751fb1..305a93ad6f 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -5,6 +5,7 @@ subdir-y += anlogic
>  subdir-y += canaan
>  subdir-y += eswin
>  subdir-y += microchip
> +subdir-y += openhwgroup
>  subdir-y += renesas
>  subdir-y += sifive
>  subdir-y += sophgo
> diff --git a/arch/riscv/boot/dts/openhwgroup/Makefile b/arch/riscv/boot/dts/openhwgroup/Makefile
> new file mode 100644
> index 0000000000..a75a5863b7
> --- /dev/null
> +++ b/arch/riscv/boot/dts/openhwgroup/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_OPENHWGROUP) += cv32a6-genesys2.dtb cv64a6-genesys2.dtb
> diff --git a/arch/riscv/boot/dts/openhwgroup/cv32a6-genesys2.dts b/arch/riscv/boot/dts/openhwgroup/cv32a6-genesys2.dts
> new file mode 100644
> index 0000000000..83d0286171
> --- /dev/null
> +++ b/arch/riscv/boot/dts/openhwgroup/cv32a6-genesys2.dts
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
> +/*
> + * Copyright 2026 NXP
> + *
> + * OpenHW Group CVA6 APU, 32-bit core (cv32a6), on the Digilent Genesys 2.
> + */
> +
> +/dts-v1/;
> +
> +#include "cva6-genesys2.dtsi"
> +
> +/ {
> +	model = "OpenHW Group CVA6 cv32a6 on Digilent Genesys 2";
> +	compatible = "openhwgroup,cv32a6-genesys2", "openhwgroup,cva6-apu";
> +
> +	memory@80000000 {
> +		device_type = "memory";
> +		/* 128 MiB of DDR3, as configured for this core by the FPGA build */
> +		reg = <0x0 0x80000000 0x0 0x8000000>;
> +	};
> +};
> +
> +&cpu0 {
> +	compatible = "openhwgroup,cv32a6", "riscv";
> +	riscv,isa-base = "rv32i";
> +	riscv,isa-extensions = "i", "m", "a", "zicntr", "zicsr", "zifencei",
> +			       "zihpm";
> +	mmu-type = "riscv,sv32";
> +};
> diff --git a/arch/riscv/boot/dts/openhwgroup/cv64a6-genesys2.dts b/arch/riscv/boot/dts/openhwgroup/cv64a6-genesys2.dts
> new file mode 100644
> index 0000000000..8fe653b35c
> --- /dev/null
> +++ b/arch/riscv/boot/dts/openhwgroup/cv64a6-genesys2.dts
> @@ -0,0 +1,31 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
> +/*
> + * Copyright 2026 NXP
> + *
> + * OpenHW Group CVA6 APU, 64-bit core (cv64a6), on the Digilent Genesys 2.
> + */
> +
> +/dts-v1/;
> +
> +#include "cva6-genesys2.dtsi"
> +
> +/ {
> +	model = "OpenHW Group CVA6 cv64a6 on Digilent Genesys 2";
> +	compatible = "openhwgroup,cv64a6-genesys2", "openhwgroup,cva6-apu";

As I mentioned, these need to change.

> +
> +	memory@80000000 {
> +		device_type = "memory";
> +		/* 1 GiB of DDR3, as configured for this core by the FPGA build */
> +		reg = <0x0 0x80000000 0x0 0x40000000>;
> +	};
> +};
> +
> +&cpu0 {
> +	compatible = "openhwgroup,cv64a6", "riscv";
> +	riscv,isa-base = "rv64i";
> +	riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "zba",
> +			       "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs",
> +			       "zca", "zcb", "zcd", "zicntr", "zicond", "zicsr",
> +			       "zifencei", "zihpm", "zknd", "zkne", "zknh";
> +	mmu-type = "riscv,sv39";
> +};
> diff --git a/arch/riscv/boot/dts/openhwgroup/cva6-genesys2.dtsi b/arch/riscv/boot/dts/openhwgroup/cva6-genesys2.dtsi
> new file mode 100644
> index 0000000000..95978274a7
> --- /dev/null
> +++ b/arch/riscv/boot/dts/openhwgroup/cva6-genesys2.dtsi
> @@ -0,0 +1,131 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
> +/*
> + * Copyright 2026 NXP
> + *
> + * OpenHW Group CVA6 APU on the Digilent Genesys 2 FPGA board.
> + *
> + * The SoC description is shared between the 32-bit (cv32a6) and the
> + * 64-bit (cv64a6) configurations of the CVA6 core. The core specific
> + * properties and the memory size are set in the board .dts files.
> + */
> +
> +/ {
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};

As I understand it, these should always be at the board level, but given
this is a pure FPGA design there's gonna be some oddness and I think
that's okay.


> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		/* The CLINT mtime counter runs at half the core clock */
> +		timebase-frequency = <25000000>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			reg = <0>;
> +			clock-frequency = <50000000>;
> +			tlb-split;
> +
> +			cpu0_intc: interrupt-controller {
> +				#interrupt-cells = <1>;
> +				interrupt-controller;
> +				compatible = "riscv,cpu-intc";
> +			};
> +		};
> +	};
> +
> +	/* Peripheral clock, the same as the core clock */

Sounds like you're then missing a clocks property in your cpu?

> +	clk50: clock-50mhz {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <50000000>;
> +		clock-output-names = "clk50";
> +	};

Is this genuinely a fixed clock, or an output of a clocking-wizard
instance (or similar)?

Cheers,
Conor.

> +
> +	leds {
> +		compatible = "gpio-leds";
> +
> +		led-0 {
> +			gpios = <&gpio0 1 0>;
> +			linux,default-trigger = "heartbeat";
> +		};
> +	};
> +
> +	soc {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		compatible = "simple-bus";
> +		ranges;
> +
> +		clint: clint@2000000 {
> +			compatible = "openhwgroup,cva6-clint", "sifive,clint0";
> +			reg = <0x0 0x2000000 0x0 0xc0000>;
> +			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> +		};
> +
> +		plic: interrupt-controller@c000000 {
> +			compatible = "openhwgroup,cva6-plic", "sifive,plic-1.0.0";
> +			reg = <0x0 0xc000000 0x0 0x4000000>;
> +			#address-cells = <0>;
> +			#interrupt-cells = <1>;
> +			interrupt-controller;
> +			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> +			riscv,ndev = <30>;
> +		};
> +
> +		uart0: serial@10000000 {
> +			compatible = "ns16550a";
> +			reg = <0x0 0x10000000 0x0 0x1000>;
> +			clock-frequency = <50000000>;
> +			interrupt-parent = <&plic>;
> +			interrupts = <1>;
> +			/* Registers are 32-bit wide and 32-bit aligned */
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +		};
> +
> +		spi0: spi@20000000 {
> +			compatible = "xlnx,xps-spi-2.00.a";
> +			reg = <0x0 0x20000000 0x0 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			interrupt-parent = <&plic>;
> +			interrupts = <2>;
> +			xlnx,num-ss-bits = <1>;
> +			xlnx,num-transfer-bits = <8>;
> +
> +			mmc@0 {
> +				compatible = "mmc-spi-slot";
> +				reg = <0>;
> +				spi-max-frequency = <12500000>;
> +				voltage-ranges = <3300 3300>;
> +				disable-wp;
> +			};
> +		};
> +
> +		gpio0: gpio@40000000 {
> +			compatible = "xlnx,xps-gpio-1.00.a";
> +			reg = <0x0 0x40000000 0x0 0x10000>;
> +			clocks = <&clk50>;
> +			#gpio-cells = <2>;
> +			gpio-controller;
> +			xlnx,all-inputs = <0>;
> +			xlnx,all-inputs-2 = <0>;
> +			xlnx,dout-default = <0>;
> +			xlnx,dout-default-2 = <0>;
> +			xlnx,gpio-width = <8>;
> +			xlnx,gpio2-width = <8>;
> +			xlnx,interrupt-present = <0>;
> +			xlnx,is-dual = <1>;
> +			xlnx,tri-default = <0xffffffff>;
> +			xlnx,tri-default-2 = <0xffffffff>;
> +		};
> +	};
> +};
> -- 
> 2.43.0
> 

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[PATCH 8/8] riscv: defconfig: enable OpenHW Group CVA6 APU support

[marouene.boubakri]

From: Marouene Boubakri <marouene.boubakri@oss.nxp.com>

Enable ARCH_OPENHWGROUP so the CVA6 APU device trees are built, and the
Xilinx SPI and GPIO drivers used by the SD card slot and the LEDs on the
Digilent Genesys 2.

Signed-off-by: Marouene Boubakri <marouene.boubakri@oss.nxp.com>
---
 arch/riscv/configs/defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 04ae305d55..ed495eb8ad 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -26,6 +26,7 @@ CONFIG_ARCH_ANDES=y
 CONFIG_ARCH_ANLOGIC=y
 CONFIG_ARCH_ESWIN=y
 CONFIG_ARCH_MICROCHIP=y
+CONFIG_ARCH_OPENHWGROUP=y
 CONFIG_ARCH_SIFIVE=y
 CONFIG_ARCH_SOPHGO=y
 CONFIG_ARCH_SPACEMIT=y
@@ -166,6 +167,7 @@ CONFIG_SPI_FSL_QUADSPI=m
 CONFIG_SPI_PL022=m
 CONFIG_SPI_SIFIVE=y
 CONFIG_SPI_SUN6I=y
+CONFIG_SPI_XILINX=y
 # CONFIG_PTP_1588_CLOCK is not set
 CONFIG_PINCTRL_TH1520=y
 CONFIG_PINCTRL_SOPHGO_CV1800B=y
@@ -175,6 +177,7 @@ CONFIG_PINCTRL_SOPHGO_SG2002=y
 CONFIG_GPIO_DWAPB=y
 CONFIG_GPIO_SIFIVE=y
 CONFIG_GPIO_SPACEMIT_K1=y
+CONFIG_GPIO_XILINX=y
 CONFIG_GPIO_PCA953X=m
 CONFIG_GPIO_PCA953X_IRQ=y
 CONFIG_POWER_RESET_GPIO_RESTART=y
-- 
2.43.0