From: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
To: Bryan O'Donoghue <bod@kernel.org>
Cc: Vinod Koul <vkoul@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Manivannan Sadhasivam <mani@kernel.org>,
gjorgji.rosikopulos@oss.qualcomm.com,
hariram.purushothaman@oss.qualcomm.com, akapatra@quicinc.com,
jigarkumar.zala@oss.qualcomm.com, linux-phy@lists.infradead.org,
linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v2 3/5] phy: qcom-mipi-csi2: Make OPP table optional
Date: Tue, 3 Nov 2026 13:41:03 -0800 [thread overview]
Message-ID: <20261103214105.3605181-4-anusha.nandi@oss.qualcomm.com> (raw)
In-Reply-To: <20261103214105.3605181-1-anusha.nandi@oss.qualcomm.com>
Not every SoC the generic MIPI CSI2 PHY driver supports needs an OPP
table: a CSIPHY with only a single, unscaled power-domain has no
performance state to vote on, so running its "core" clock through
the OPP framework buys nothing over a plain clk_set_rate(). Skip
devm_pm_opp_set_clkname()/devm_pm_opp_of_add_table() in probe() and
the OPP/performance-state handling in
phy_qcom_mipi_csi2_set_clock_rates() when soc_cfg->opp_clk_name is
unset, falling back to clk_round_rate()/clk_set_rate() on the timer
clock only.
x1e80100 still sets opp_clk_name, so this is a no-op for it.
Reviewed-by: Jigarkumar Zala <jigarkumar.zala@oss.qualcomm.com>
Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
---
.../phy/qualcomm/phy-qcom-mipi-csi2-core.c | 72 ++++++++++---------
1 file changed, 39 insertions(+), 33 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c
index 3de25728ed28..181813caf282 100644
--- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c
+++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c
@@ -32,40 +32,43 @@ phy_qcom_mipi_csi2_set_clock_rates(struct mipi_csi2phy_device *csi2phy,
unsigned long opp_rate = link_freq / 4;
struct dev_pm_opp *opp;
long timer_rate;
- int i, pstate;
+ int i = 0, pstate;
int ret;
- opp = dev_pm_opp_find_freq_ceil(dev, &opp_rate);
- if (IS_ERR(opp)) {
- dev_err(csi2phy->dev, "Couldn't find ceiling for %lld Hz\n",
- link_freq);
- return PTR_ERR(opp);
- }
+ if (csi2phy->soc_cfg->opp_clk_name) {
+ opp = dev_pm_opp_find_freq_ceil(dev, &opp_rate);
+ if (IS_ERR(opp)) {
+ dev_err(csi2phy->dev, "Couldn't find ceiling for %lld Hz\n",
+ link_freq);
+ return PTR_ERR(opp);
+ }
- pstate = 0;
- for (i = 0; csi2phy->pd_list && i < csi2phy->pd_list->num_pds; i++) {
- unsigned int perf;
+ pstate = 0;
+ for (i = 0; csi2phy->pd_list && i < csi2phy->pd_list->num_pds; i++) {
+ unsigned int perf;
- if (!csi2phy->soc_cfg->genpds[i].scaled)
- continue;
+ if (!csi2phy->soc_cfg->genpds[i].scaled)
+ continue;
- perf = dev_pm_opp_get_required_pstate(opp, pstate);
- pstate += 1;
+ perf = dev_pm_opp_get_required_pstate(opp, pstate);
+ pstate += 1;
- ret = dev_pm_genpd_set_performance_state(csi2phy->pd_list->pd_devs[i], perf);
- if (ret) {
- dev_err(csi2phy->dev, "Couldn't set perf state %u\n",
- perf);
- dev_pm_opp_put(opp);
- goto unset_pstate;
+ ret = dev_pm_genpd_set_performance_state(csi2phy->pd_list->pd_devs[i],
+ perf);
+ if (ret) {
+ dev_err(csi2phy->dev, "Couldn't set perf state %u\n",
+ perf);
+ dev_pm_opp_put(opp);
+ goto unset_pstate;
+ }
}
- }
- dev_pm_opp_put(opp);
+ dev_pm_opp_put(opp);
- ret = dev_pm_opp_set_rate(dev, opp_rate);
- if (ret) {
- dev_err(csi2phy->dev, "dev_pm_opp_set_rate() fail\n");
- goto unset_opp_rate;
+ ret = dev_pm_opp_set_rate(dev, opp_rate);
+ if (ret) {
+ dev_err(csi2phy->dev, "dev_pm_opp_set_rate() fail\n");
+ goto unset_opp_rate;
+ }
}
timer_rate = clk_round_rate(csi2phy->timer_clk, link_freq / 4);
@@ -83,7 +86,8 @@ phy_qcom_mipi_csi2_set_clock_rates(struct mipi_csi2phy_device *csi2phy,
return 0;
unset_opp_rate:
- dev_pm_opp_set_rate(dev, 0);
+ if (csi2phy->soc_cfg->opp_clk_name)
+ dev_pm_opp_set_rate(dev, 0);
unset_pstate:
while (i--) {
@@ -405,13 +409,15 @@ static int phy_qcom_mipi_csi2_probe(struct platform_device *pdev)
if (!csi2phy->timer_clk)
return dev_err_probe(dev, -ENODEV, "no timer clock\n");
- ret = devm_pm_opp_set_clkname(dev, csi2phy->soc_cfg->opp_clk_name);
- if (ret)
- return dev_err_probe(dev, ret, "Failed to set opp clkname\n");
+ if (csi2phy->soc_cfg->opp_clk_name) {
+ ret = devm_pm_opp_set_clkname(dev, csi2phy->soc_cfg->opp_clk_name);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to set opp clkname\n");
- ret = devm_pm_opp_of_add_table(dev);
- if (ret)
- return dev_err_probe(dev, ret, "invalid OPP table in device tree\n");
+ ret = devm_pm_opp_of_add_table(dev);
+ if (ret)
+ return dev_err_probe(dev, ret, "invalid OPP table in device tree\n");
+ }
num_supplies = csi2phy->soc_cfg->num_supplies;
csi2phy->supplies = devm_kzalloc(dev, sizeof(*csi2phy->supplies) * num_supplies,
--
2.34.1
next prev parent reply other threads:[~2026-11-03 21:41 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-03 21:41 [PATCH v2 0/5] phy: qcom-mipi-csi2: Add D-PHY support for sa8775p, qcs8300 and sc7280 Anusha Arun Nandi
2026-11-03 21:41 ` [PATCH v2 1/5] dt-bindings: phy: qcom: Add common qcom,csi2-phy Anusha Arun Nandi
2026-11-03 21:41 ` [PATCH v2 2/5] phy: qcom-mipi-csi2: Make timer and OPP clock names configurable Anusha Arun Nandi
2026-11-03 21:41 ` Anusha Arun Nandi [this message]
2026-11-03 21:41 ` [PATCH v2 4/5] phy: qcom-mipi-csi2: Add sa8775p D-PHY support Anusha Arun Nandi
2026-11-03 21:41 ` [PATCH v2 5/5] phy: qcom-mipi-csi2: Add sc7280 D-PHY provider Anusha Arun Nandi
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