[PATCH 00/25] riscv: add support for the Metanoia MT2824 SoC and MT5824 EVB

[PATCH 00/25] riscv: add support for the Metanoia MT2824 SoC and MT5824 EVB

[Benoît Monin]

Hi all,

This series adds initial upstream support for the Metanoia MT2824 SoC
and its MT5824 evaluation board.

The MT2824 is a dual-core RISC-V SoC built on Andes AX45MP cores. It
integrates two 8250-compatible UARTs, the Andes PLIC/PLICSW/PLMT interrupt
and timer blocks, the AX45MP L2 cache controller, a simple reset controller
and a system reboot controller, the ATCWDT200 watchdog, one QSPI and eight
ATCSPI200 SPI controllers, a Synopsys DWC MSHC 2.00a eMMC/SD controller,
and a Synopsys DWC2 USB2 host controller with a reset-only USB2 PHY.

The series is organised as:

- patches 1-14 add the device tree bindings, the Metanoia vendor prefix,
  the RISC-V board schema and the SoC block compatibles
- patch 15 adds ARCH_METANOIA and selects the AX45MP errata
- patches 16-23 add the reset, SPI, watchdog, MMC, PHY and USB changes
  needed to build and probe on this SoC
- patch 24 adds the MT2824 SoC and MT5824 EVB device trees
- patch 25 adds the MAINTAINERS entry

The ATCSPI200 driver gains optional interrupt support for PIO transfers:
when the controller IRQ is wired, the FIFOs and the end of transfer
are serviced from the handler, with a fallback to polling when no IRQ
is available.

The DWC MSHC controller on the evaluation board is wired to either an
SD slot or an eMMC through a board jumper that the SoC cannot read. In
the absence of a fixed card type in the device tree, the driver probes
the eMMC first at 1.8 V and falls back to the SD slot at 3.3 V. The
controller also needs custom tuning and HS400 PHY DLL handling, which
is why it has its own sdhci_ops.

The MT2824 SoC contains other controllers not yet exposed (I2C, GPIO,
pinctrl, Ethernet, DSP, ...). This first series allows accessing the
evaluation board via its serial console, and all its storage options
(SPI-NOR, eMMC, SD card). The watchdog and the USB port are also
available.

The driver changes do not depend on the DTS at build time and are gated
on the new compatible strings. For merge ordering, the DTS depends on the
ARCH_METANOIA Kconfig entry (patch 15) and on the binding compatibles
being accepted. The patches can therefore go through their respective
subsystem trees, with the Kconfig, DTS and MAINTAINERS patches going
through the RISC-V tree once the driver and binding patches have landed.

The series is based on v7.4-rc1.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
Benoît Monin (25):
      dt-bindings: vendor-prefixes: add Metanoia Communications
      dt-bindings: riscv: add Metanoia SoC-based boards
      dt-bindings: reset: add Metanoia MT2824
      dt-bindings: power: reset: add Metanoia MT2824 reboot
      dt-bindings: phy: add Metanoia USB2 PHY
      dt-bindings: cache: andestech,ax45mp-cache: add MT2824 compatible
      dt-bindings: interrupt-controller: sifive,plic-1.0.0: add Metanoia MT2824
      dt-bindings: interrupt-controller: andestech,plicsw: add Metanoia MT2824
      dt-bindings: timer: andestech,plmt0: add Metanoia MT2824
      dt-bindings: mmc: snps,dwcmshc-sdhci: add Metanoia MT2824
      dt-bindings: spi: andestech,ae350-spi: make DMA and interrupts optional
      dt-bindings: spi: andestech,ae350-spi: add Metanoia MT2824
      dt-bindings: usb: dwc2: add Metanoia MT2824
      dt-bindings: watchdog: andestech,ae350-wdt: add Metanoia MT2824
      riscv: add ARCH_METANOIA Kconfig entry
      reset: simple: add Metanoia MT2824 support
      spi: atcspi200: add optional interrupt support
      spi: atcspi200: allow building for Metanoia SoCs
      watchdog: atcwdt200: allow building for Metanoia SoCs
      mmc: sdhci-of-dwcmshc: add MT2824 support
      mmc: sdhci-of-dwcmshc: add MT2824 tuning and HS400 support
      phy: metanoia: add USB2 PHY driver
      usb: dwc2: add support for Metanoia MT2824
      riscv: add Metanoia MT2824 SoC and MT5824 EVB support
      MAINTAINERS: add RISC-V Metanoia SoC support

 .../bindings/cache/andestech,ax45mp-cache.yaml     |   1 +
 .../interrupt-controller/andestech,plicsw.yaml     |   1 +
 .../interrupt-controller/sifive,plic-1.0.0.yaml    |   1 +
 .../bindings/mmc/snps,dwcmshc-sdhci.yaml           |   1 +
 .../devicetree/bindings/phy/metanoia,usb2-phy.yaml |  43 ++
 .../bindings/power/reset/metanoia,reboot.yaml      |  34 +
 .../devicetree/bindings/reset/metanoia,reset.yaml  |  40 ++
 .../devicetree/bindings/riscv/metanoia.yaml        |  25 +
 .../bindings/spi/andestech,ae350-spi.yaml          |   9 +-
 .../devicetree/bindings/timer/andestech,plmt0.yaml |   1 +
 Documentation/devicetree/bindings/usb/dwc2.yaml    |   1 +
 .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
 .../bindings/watchdog/andestech,ae350-wdt.yaml     |   1 +
 MAINTAINERS                                        |  11 +
 arch/riscv/Kconfig.socs                            |   8 +
 arch/riscv/boot/dts/Makefile                       |   1 +
 arch/riscv/boot/dts/metanoia/Makefile              |   2 +
 arch/riscv/boot/dts/metanoia/mt2824.dtsi           | 330 ++++++++++
 arch/riscv/boot/dts/metanoia/mt5824-evb.dts        |  81 +++
 drivers/mmc/host/Kconfig                           |   1 +
 drivers/mmc/host/sdhci-of-dwcmshc.c                | 704 +++++++++++++++++++++
 drivers/phy/Kconfig                                |   1 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/metanoia/Kconfig                       |  16 +
 drivers/phy/metanoia/Makefile                      |   3 +
 drivers/phy/metanoia/phy-usb2.c                    |  88 +++
 drivers/reset/Kconfig                              |   2 +-
 drivers/reset/reset-simple.c                       |   1 +
 drivers/spi/Kconfig                                |   2 +-
 drivers/spi/spi-atcspi200.c                        | 255 +++++++-
 drivers/usb/dwc2/params.c                          |  13 +
 drivers/watchdog/Kconfig                           |   2 +-
 32 files changed, 1667 insertions(+), 15 deletions(-)
---
base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
change-id: 20261016-mt2824-32a77a241798

Best regards,
--  
Benoît Monin, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

[PATCH 01/25] dt-bindings: vendor-prefixes: add Metanoia Communications

[Benoît Monin]

Add the vendor prefix for Metanoia Communications Inc., a fabless
semiconductor company specializing in wireline and 5G radio access
networking chips.

Link: https://metanoia-comm.com/about-us/company-overview/

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 5471a06f93f1..085749fb8a72 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1087,6 +1087,8 @@ patternProperties:
     description: Cisco Meraki, LLC
   "^merrii,.*":
     description: Merrii Technology Co., Ltd.
+  "^metanoia,.*":
+    description: Metanoia Communications Inc.
   "^methode,.*":
     description: Methode Electronics, Inc.
   "^micrel,.*":

-- 
2.56.0

[PATCH 02/25] dt-bindings: riscv: add Metanoia SoC-based boards

[Benoît Monin]

Document the compatible strings of the Metanoia MT2824 SoC and the
MT5824 evaluation board.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 .../devicetree/bindings/riscv/metanoia.yaml        | 25 ++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/metanoia.yaml b/Documentation/devicetree/bindings/riscv/metanoia.yaml
new file mode 100644
index 000000000000..a651917630fc
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/metanoia.yaml
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/metanoia.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Metanoia SoC-based boards
+
+maintainers:
+  - Jun Chang <jun.chang@metanoia-comm.com>
+
+description:
+  Metanoia SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - metanoia,mt5824-evb
+          - const: metanoia,mt2824
+
+additionalProperties: true

-- 
2.56.0

[PATCH 03/25] dt-bindings: reset: add Metanoia MT2824

[Benoît Monin]

Document the Metanoia MT2824 reset controller, which provides warm reset
and system reset controls through memory-mapped registers.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 .../devicetree/bindings/reset/metanoia,reset.yaml  | 40 ++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/Documentation/devicetree/bindings/reset/metanoia,reset.yaml b/Documentation/devicetree/bindings/reset/metanoia,reset.yaml
new file mode 100644
index 000000000000..f169d1fa919c
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/metanoia,reset.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/metanoia,reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Metanoia Reset Controller
+
+maintainers:
+  - Jun Chang <jun.chang@metanoia-comm.com>
+
+description:
+  Metanoia reset controllers provide warm-reset and system reset controls
+  via memory-mapped registers.
+
+properties:
+  compatible:
+    enum:
+      - metanoia,mt2824-reset
+
+  reg:
+    maxItems: 1
+
+  "#reset-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    rst: rst-controller@1000000c {
+        compatible = "metanoia,mt2824-reset";
+        reg = <0x1000000c 0x4>;
+        #reset-cells = <1>;
+    };

-- 
2.56.0

[PATCH 04/25] dt-bindings: power: reset: add Metanoia MT2824 reboot

[Benoît Monin]

Document the Metanoia MT2824 reboot register, which the firmware writes
in machine mode to perform a warm system reboot. OpenSBI has a system
reset driver for it.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 .../bindings/power/reset/metanoia,reboot.yaml      | 34 ++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/Documentation/devicetree/bindings/power/reset/metanoia,reboot.yaml b/Documentation/devicetree/bindings/power/reset/metanoia,reboot.yaml
new file mode 100644
index 000000000000..2670fe7ab93f
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/metanoia,reboot.yaml
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/reset/metanoia,reboot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Metanoia MT2824 Reboot Controller
+
+maintainers:
+  - Jun Chang <jun.chang@metanoia-comm.com>
+
+description:
+  The Metanoia MT2824 reboot controller provides a system warm reboot through
+  a memory-mapped register. It is used by the firmware in machine mode.
+
+properties:
+  compatible:
+    const: metanoia,mt2824-reboot
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    reboot: reboot@10000004 {
+      compatible = "metanoia,mt2824-reboot";
+      reg = <0x10000004 0x8>;
+    };

-- 
2.56.0

[PATCH 05/25] dt-bindings: phy: add Metanoia USB2 PHY

[Benoît Monin]

Document the USB2 PHY found in Metanoia MT2824 SoC.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 .../devicetree/bindings/phy/metanoia,usb2-phy.yaml | 43 ++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/metanoia,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/metanoia,usb2-phy.yaml
new file mode 100644
index 000000000000..0605e6d0f67d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/metanoia,usb2-phy.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/metanoia,usb2-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Metanoia USB2 PHY
+
+description: |
+  The Metanoia MT2824 USB2 PHY is controlled solely through a reset line.
+
+maintainers:
+  - Jun Chang <jun.chang@metanoia-comm.com>
+
+properties:
+  compatible:
+    const: metanoia,mt2824-usb2-phy
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    const: usb2-phy
+
+  "#phy-cells":
+    const: 0
+
+required:
+  - compatible
+  - resets
+  - reset-names
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    usb2phy: usb2-phy-reset {
+        compatible = "metanoia,mt2824-usb2-phy";
+        #phy-cells = <0>;
+        resets = <&rst 18>;
+        reset-names = "usb2-phy";
+    };

-- 
2.56.0

[PATCH 06/25] dt-bindings: cache: andestech,ax45mp-cache: add MT2824 compatible

[Benoît Monin]

The MT2824 reuses the AX45MP L2 cache controller with its own cache
configuration. Add a SoC-specific compatible in case there are additional
differences between the two implementations.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
index b135ffa4ab6b..c94044a049b2 100644
--- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
+++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
@@ -30,6 +30,7 @@ properties:
     items:
       - enum:
           - andestech,qilai-ax45mp-cache
+          - metanoia,mt2824-ax45mp-cache
           - renesas,r9a07g043f-ax45mp-cache
       - const: andestech,ax45mp-cache
       - const: cache

-- 
2.56.0

[PATCH 07/25] dt-bindings: interrupt-controller: sifive,plic-1.0.0: add Metanoia MT2824

[Benoît Monin]

The Metanoia MT2824 integrates the Andes NCEPLIC100 platform-level
interrupt controller. Add its compatible string, with andestech,nceplic100
as a fallback.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 .../devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml      | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index cde4bb691897..b76e2fc4cc88 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -54,6 +54,7 @@ properties:
       - items:
           - enum:
               - andestech,qilai-plic
+              - metanoia,mt2824-plic
               - renesas,r9a07g043-plic
           - const: andestech,nceplic100
       - items:

-- 
2.56.0

[PATCH 08/25] dt-bindings: interrupt-controller: andestech,plicsw: add Metanoia MT2824

[Benoît Monin]

The Metanoia MT2824 integrates the Andes PLICSW software interrupt
controller. Add its compatible string, with andestech,plicsw as a
fallback.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 .../devicetree/bindings/interrupt-controller/andestech,plicsw.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml b/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
index eb2eb611ac09..a61fe7ca9023 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
@@ -23,6 +23,7 @@ properties:
     items:
       - enum:
           - andestech,qilai-plicsw
+          - metanoia,mt2824-plicsw
       - const: andestech,plicsw
 
   reg:

-- 
2.56.0

[PATCH 09/25] dt-bindings: timer: andestech,plmt0: add Metanoia MT2824

[Benoît Monin]

The Metanoia MT2824 integrates the Andes PLMT0 timer. Add its compatible
string, with andestech,plmt0 as a fallback.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 Documentation/devicetree/bindings/timer/andestech,plmt0.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/timer/andestech,plmt0.yaml b/Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
index 90b612096004..b33350cf43a5 100644
--- a/Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
+++ b/Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
@@ -21,6 +21,7 @@ properties:
     items:
       - enum:
           - andestech,qilai-plmt
+          - metanoia,mt2824-plmt
       - const: andestech,plmt0
 
   reg:

-- 
2.56.0

[PATCH 10/25] dt-bindings: mmc: snps,dwcmshc-sdhci: add Metanoia MT2824

[Benoît Monin]

The Metanoia MT2824 integrates the Synopsys DesignWare Mobile Storage
Host Controller for eMMC/SD. Add its compatible string.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
index cd823a3ef213..0ebd0f9c1d62 100644
--- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
@@ -26,6 +26,7 @@ properties:
           - canaan,k230-emmc
           - canaan,k230-sdio
           - hpe,gsc-dwcmshc
+          - metanoia,mt2824-dwcmshc
           - rockchip,rk3568-dwcmshc
           - rockchip,rk3588-dwcmshc
           - snps,dwcmshc-sdhci

-- 
2.56.0

[PATCH 11/25] dt-bindings: spi: andestech,ae350-spi: make DMA and interrupts optional

[Benoît Monin]

The ATCSPI200 controller can be used in PIO mode, without DMA, and PIO
transfers can optionally use the controller's interrupt. Make dmas,
dma-names and interrupts optional, and require dma-names if dmas is
specified.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml b/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml
index 381042e07fd0..91e04f5d354a 100644
--- a/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml
@@ -24,6 +24,9 @@ properties:
   clocks:
     maxItems: 1
 
+  interrupts:
+    maxItems: 1
+
   dmas:
     items:
       - description: Transmit FIFO DMA channel
@@ -34,6 +37,9 @@ properties:
       - const: tx
       - const: rx
 
+dependencies:
+  dmas: [ dma-names ]
+
 patternProperties:
   "@[0-9a-f]+$":
     type: object
@@ -55,8 +61,6 @@ required:
   - compatible
   - reg
   - clocks
-  - dmas
-  - dma-names
 
 unevaluatedProperties: false
 

-- 
2.56.0

[PATCH 12/25] dt-bindings: spi: andestech,ae350-spi: add Metanoia MT2824

[Benoît Monin]

The Metanoia MT2824 integrates the Andes ATCSPI200 SPI controller. Add
its compatible string, with andestech,ae350-spi as a fallback.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml b/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml
index 91e04f5d354a..6e5dd8175aa9 100644
--- a/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml
@@ -15,6 +15,7 @@ properties:
       - items:
           - enum:
               - andestech,qilai-spi
+              - metanoia,mt2824-spi
           - const: andestech,ae350-spi
       - const: andestech,ae350-spi
 

-- 
2.56.0

[PATCH 13/25] dt-bindings: usb: dwc2: add Metanoia MT2824

[Benoît Monin]

Document the metanoia,mt2824-usb compatible, which falls back to the
generic snps,dwc2 binding, so that the DWC2 USB controller on the Metanoia
MT2824 SoC can be described in device trees.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 Documentation/devicetree/bindings/usb/dwc2.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml
index 6c3a10991b8b..898c83e57843 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
@@ -55,6 +55,7 @@ properties:
               - amlogic,meson-g12a-usb
               - amlogic,meson-a1-usb
               - intel,socfpga-agilex-hsotg
+              - metanoia,mt2824-usb
           - const: snps,dwc2
       - const: amcc,dwc-otg
       - const: apm,apm82181-dwc-otg

-- 
2.56.0

[PATCH 14/25] dt-bindings: watchdog: andestech,ae350-wdt: add Metanoia MT2824

[Benoît Monin]

The Metanoia MT2824 SoC integrates the Andes ATCWDT200 watchdog. Add its
compatible string, with andestech,ae350-wdt as a fallback.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml b/Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml
index f1107c552788..d8c6f38e1035 100644
--- a/Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml
@@ -18,6 +18,7 @@ properties:
       - items:
           - enum:
               - andestech,qilai-wdt
+              - metanoia,mt2824-wdt
           - const: andestech,ae350-wdt
       - const: andestech,ae350-wdt
 

-- 
2.56.0

[PATCH 15/25] riscv: add ARCH_METANOIA Kconfig entry

[Benoît Monin]

Add support for Metanoia RISC-V SoCs such as the MT2824. The Metanoia
MT2824 is built around Andes AX45MP cores, so select the Andes errata
workarounds.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 arch/riscv/Kconfig.socs | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index cecbce0c4983..adcb10bca966 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -18,6 +18,14 @@ config ARCH_ESWIN
 	  This enables support for ESWIN SoC platform hardware,
 	  including the ESWIN EIC7700 SoC.
 
+config ARCH_METANOIA
+	bool "Metanoia SoCs"
+	depends on MMU
+	select ARCH_HAS_RESET_CONTROLLER
+	select ERRATA_ANDES
+	help
+	  This enables support for Metanoia SoC platforms.
+
 config ARCH_MICROCHIP_POLARFIRE
 	def_bool ARCH_MICROCHIP
 

-- 
2.56.0

[PATCH 16/25] reset: simple: add Metanoia MT2824 support

[Benoît Monin]

The Metanoia MT2824 integrates a simple reset controller with the same
register layout as the other reset-simple controllers. Add its compatible
string and build reset-simple for ARCH_METANOIA by default.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/reset/Kconfig        | 2 +-
 drivers/reset/reset-simple.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index eda9c698a95f..b42768d7b88a 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -297,7 +297,7 @@ config RESET_SCMI
 
 config RESET_SIMPLE
 	bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
-	default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
+	default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_METANOIA || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
 	depends on HAS_IOMEM
 	help
 	  This enables a simple reset controller driver for reset lines that
diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c
index 79e94ecfe4f5..177df36235a5 100644
--- a/drivers/reset/reset-simple.c
+++ b/drivers/reset/reset-simple.c
@@ -148,6 +148,7 @@ static const struct of_device_id reset_simple_dt_ids[] = {
 		.data = &reset_simple_active_low },
 	{ .compatible = "brcm,bcm4908-misc-pcie-reset",
 		.data = &reset_simple_active_low },
+	{ .compatible = "metanoia,mt2824-reset" },
 	{ .compatible = "snps,dw-high-reset" },
 	{ .compatible = "snps,dw-low-reset",
 		.data = &reset_simple_active_low },

-- 
2.56.0

[PATCH 17/25] spi: atcspi200: add optional interrupt support

[Benoît Monin]

For PIO transfers, the driver busy-polls the FIFO empty/full flags and
the SPI active bit for completion. When the controller's interrupt is
available, use it instead of polling to keep the FIFO serviced and to
detect the end of transfer.

Interrupts are optional. Controllers without an interrupt keep using the
polling path, as do command-only transfers; the driver also falls back to
polling when the interrupt cannot be requested.

The command register is now written when a transfer is started instead of
in atcspi_prepare_trans(), so the interrupt path can enable interrupts
before starting the transfer and the first FIFO or end-of-transfer
event is not missed. As a result, it is also set at the beginning of
atcspi_dma_trans() and atcspi_xfer_data_poll(), and in the command-only
path of atcspi_exec_mem_op().

Introduce atcspi_reset_engine() as a helper to reset the SPI controller
and the FIFOs, and use on transfer error and in atcspi_setup().

The interrupt path configures the FIFO thresholds for the transfer and
restores them afterwards. It acknowledges the interrupt status before
servicing the FIFOs so events arriving during servicing are not lost,
and resets the controller if a transfer times out or completes with
transmit/receive words left unhandled.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/spi/spi-atcspi200.c | 255 ++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 245 insertions(+), 10 deletions(-)

diff --git a/drivers/spi/spi-atcspi200.c b/drivers/spi/spi-atcspi200.c
index b532c58c0ab9..df932620a690 100644
--- a/drivers/spi/spi-atcspi200.c
+++ b/drivers/spi/spi-atcspi200.c
@@ -12,6 +12,7 @@
 #include <linux/dmaengine.h>
 #include <linux/err.h>
 #include <linux/errno.h>
+#include <linux/interrupt.h>
 #include <linux/jiffies.h>
 #include <linux/minmax.h>
 #include <linux/module.h>
@@ -20,6 +21,7 @@
 #include <linux/regmap.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/spi-mem.h>
+#include <linux/unaligned.h>
 
 /* Register definitions  */
 #define ATCSPI_TRANS_FMT	0x10	/* SPI transfer format register */
@@ -29,6 +31,8 @@
 #define ATCSPI_DATA		0x2C	/* SPI data register */
 #define ATCSPI_CTRL		0x30	/* SPI control register */
 #define ATCSPI_STATUS		0x34	/* SPI status register */
+#define ATCSPI_INTR_EN		0x38	/* SPI interrupt enable register */
+#define ATCSPI_INTR_ST		0x3C	/* SPI interrupt status register */
 #define ATCSPI_TIMING		0x40	/* SPI interface timing register */
 #define ATCSPI_CONFIG		0x7C	/* SPI configuration register */
 
@@ -62,11 +66,23 @@
 #define CTRL_TX_FIFO_RST	BIT(2)
 #define CTRL_RX_DMA_EN		BIT(3)
 #define CTRL_TX_DMA_EN		BIT(4)
+#define CTRL_TX_THRES		GENMASK(23, 16)
+#define CTRL_RX_THRES		GENMASK(15, 8)
 
 /* Status register */
 #define ATCSPI_ACTIVE		BIT(0)
 #define ATCSPI_RX_EMPTY		BIT(14)
 #define ATCSPI_TX_FULL		BIT(23)
+#define ATCSPI_RXNUM_LO(x)	FIELD_GET(GENMASK(13, 8), (x))
+#define ATCSPI_RXNUM_HI(x)	FIELD_GET(GENMASK(25, 24), (x))
+#define ATCSPI_TXNUM_LO(x)	FIELD_GET(GENMASK(21, 16), (x))
+#define ATCSPI_TXNUM_HI(x)	FIELD_GET(GENMASK(29, 28), (x))
+
+/* Interrupt enable/status registers */
+#define ATCSPI_END_INT		BIT(4)
+#define ATCSPI_TX_FIFO_INT	BIT(3)
+#define ATCSPI_RX_FIFO_INT	BIT(2)
+#define ATCSPI_INTR_ALL		GENMASK(5, 0)
 
 /* Interface timing setting */
 #define TIMING_SCLK_DIV_MASK	GENMASK(7, 0)
@@ -104,6 +120,12 @@
  *                  the current transfer.
  * @use_dma:        Enable DMA mode if ATCSPI_DMA_SUPPORT is set and DMA is
  *                  successfully configured.
+ * @irq:            The controller interrupt, or 0 when it is not wired.
+ * @xfer_done:      Completion signalled by the interrupt handler.
+ * @tx_ptr:         Current position in the transmit buffer.
+ * @tx_words:       Number of FIFO entries left to transmit.
+ * @rx_ptr:         Current position in the receive buffer.
+ * @rx_words:       Number of FIFO entries left to receive.
  */
 struct atcspi_dev {
 	struct spi_controller	*host;
@@ -119,6 +141,12 @@ struct atcspi_dev {
 	unsigned int		rxfifo_size;
 	bool			data_merge;
 	bool			use_dma;
+	int			irq;
+	struct completion	xfer_done;
+	const void		*tx_ptr;
+	unsigned int		tx_words;
+	void			*rx_ptr;
+	unsigned int		rx_words;
 };
 
 static int atcspi_wait_fifo_ready(struct atcspi_dev *spi,
@@ -141,6 +169,193 @@ static int atcspi_wait_fifo_ready(struct atcspi_dev *spi,
 	return ret;
 }
 
+static unsigned int atcspi_rx_fifo_avail(unsigned int status)
+{
+	return ATCSPI_RXNUM_LO(status) | (ATCSPI_RXNUM_HI(status) << 6);
+}
+
+static unsigned int atcspi_tx_fifo_avail(struct atcspi_dev *spi, unsigned int status)
+{
+	unsigned int n = ATCSPI_TXNUM_LO(status) | (ATCSPI_TXNUM_HI(status) << 6);
+
+	return n < spi->txfifo_size ? spi->txfifo_size - n : 0;
+}
+
+static void atcspi_fifo_read(struct atcspi_dev *spi, void *dst, unsigned int nb_words)
+{
+	unsigned int val, i;
+
+	if (spi->data_merge) {
+		unsigned int *buf = dst;
+
+		for (i = 0; i < nb_words; i++) {
+			regmap_read(spi->regmap, ATCSPI_DATA, &val);
+			put_unaligned(val, buf++);
+		}
+	} else {
+		unsigned char *buf = dst;
+
+		for (i = 0; i < nb_words; i++) {
+			regmap_read(spi->regmap, ATCSPI_DATA, &val);
+			*buf++ = (unsigned char)val;
+		}
+	}
+}
+
+static void atcspi_fifo_write(struct atcspi_dev *spi, const void *src, unsigned int nb_words)
+{
+	unsigned int val, i;
+
+	if (spi->data_merge) {
+		const unsigned int *buf = src;
+
+		for (i = 0; i < nb_words; i++) {
+			val = get_unaligned(buf++);
+			regmap_write(spi->regmap, ATCSPI_DATA, val);
+		}
+	} else {
+		const unsigned char *buf = src;
+
+		for (i = 0; i < nb_words; i++) {
+			val = *buf++;
+			regmap_write(spi->regmap, ATCSPI_DATA, val);
+		}
+	}
+}
+
+static irqreturn_t atcspi_irq(int irq, void *dev_id)
+{
+	struct atcspi_dev *spi = dev_id;
+	int num_byte = spi->data_merge ? 4 : 1;
+	unsigned int st, en, status, n;
+
+	regmap_read(spi->regmap, ATCSPI_INTR_ST, &st);
+	regmap_read(spi->regmap, ATCSPI_INTR_EN, &en);
+	st &= en;
+	if (!st)
+		return IRQ_NONE;
+
+	regmap_write(spi->regmap, ATCSPI_INTR_ST, st);
+
+	regmap_read(spi->regmap, ATCSPI_STATUS, &status);
+
+	if (st & (ATCSPI_RX_FIFO_INT | ATCSPI_END_INT)) {
+		n = min(atcspi_rx_fifo_avail(status), spi->rx_words);
+		atcspi_fifo_read(spi, spi->rx_ptr, n);
+		spi->rx_words -= n;
+		spi->rx_ptr = (unsigned char *)spi->rx_ptr + n * num_byte;
+	}
+
+	if (st & ATCSPI_TX_FIFO_INT) {
+		n = min(atcspi_tx_fifo_avail(spi, status), spi->tx_words);
+		atcspi_fifo_write(spi, spi->tx_ptr, n);
+		spi->tx_words -= n;
+		spi->tx_ptr = (unsigned char *)spi->tx_ptr + n * num_byte;
+		if (!spi->tx_words) {
+			en &= ~ATCSPI_TX_FIFO_INT;
+			regmap_write(spi->regmap, ATCSPI_INTR_EN, en);
+		}
+	}
+
+	if (st & ATCSPI_END_INT) {
+		regmap_write(spi->regmap, ATCSPI_INTR_EN, 0);
+		complete(&spi->xfer_done);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int atcspi_reset_engine(struct atcspi_dev *spi)
+{
+	unsigned int ctrl_val = CTRL_SPI_RST | CTRL_TX_FIFO_RST | CTRL_RX_FIFO_RST;
+	unsigned int val;
+
+	regmap_write(spi->regmap, ATCSPI_CTRL, ctrl_val);
+
+	return regmap_read_poll_timeout(spi->regmap,
+					ATCSPI_CTRL,
+					val,
+					!(val & ctrl_val),
+					0,
+					ATCSPI_RDY_TIMEOUT_US);
+}
+
+static int atcspi_xfer_data_irq(struct atcspi_dev *spi,
+				const struct spi_mem_op *op)
+{
+	unsigned int ctrl, en = ATCSPI_END_INT;
+	int num_byte = spi->data_merge ? 4 : 1;
+	bool has_timedout = false;
+	int timeout;
+
+	spi->rx_words = 0;
+	spi->tx_words = 0;
+	spi->rx_ptr = op->data.buf.in;
+	spi->tx_ptr = op->data.buf.out;
+
+	if (op->data.dir == SPI_MEM_DATA_IN) {
+		spi->rx_words = op->data.nbytes / num_byte;
+		en |= ATCSPI_RX_FIFO_INT;
+	} else {
+		spi->tx_words = op->data.nbytes / num_byte;
+		en |= ATCSPI_TX_FIFO_INT;
+	}
+
+	regmap_read(spi->regmap, ATCSPI_CTRL, &ctrl);
+	ctrl &= ~(CTRL_TX_THRES | CTRL_RX_THRES);
+	ctrl |= FIELD_PREP(CTRL_TX_THRES, spi->txfifo_size / 2) |
+	FIELD_PREP(CTRL_RX_THRES, spi->rxfifo_size / 2);
+	regmap_write(spi->regmap, ATCSPI_CTRL, ctrl);
+
+	reinit_completion(&spi->xfer_done);
+
+	if (spi->tx_words) {
+		unsigned int status, nb_words;
+
+		regmap_read(spi->regmap, ATCSPI_STATUS, &status);
+		nb_words = min(atcspi_tx_fifo_avail(spi, status), spi->tx_words);
+		atcspi_fifo_write(spi, spi->tx_ptr, nb_words);
+		spi->tx_words -= nb_words;
+		spi->tx_ptr = (unsigned char *)spi->tx_ptr + nb_words * num_byte;
+	}
+
+	regmap_write(spi->regmap, ATCSPI_INTR_ST, ATCSPI_INTR_ALL);
+	regmap_write(spi->regmap, ATCSPI_INTR_EN, en);
+
+	regmap_write(spi->regmap, ATCSPI_CMD, op->cmd.opcode);
+
+	timeout = msecs_to_jiffies(ATCSPI_XFER_TIMEOUT(op->data.nbytes));
+	if (!wait_for_completion_timeout(&spi->xfer_done, timeout)) {
+		regmap_write(spi->regmap, ATCSPI_INTR_EN, 0);
+		synchronize_irq(spi->irq);
+
+		if (!completion_done(&spi->xfer_done))
+			has_timedout = true;
+	}
+
+	regmap_write(spi->regmap, ATCSPI_INTR_EN, 0);
+	regmap_write(spi->regmap, ATCSPI_INTR_ST, ATCSPI_INTR_ALL);
+
+	/* Reset the SPI controller if the transfer never completed */
+	if (has_timedout) {
+		atcspi_reset_engine(spi);
+
+		return -ETIMEDOUT;
+	}
+
+	/* Reset the controller for completed but truncated transfer */
+	if (spi->rx_words || spi->tx_words) {
+		atcspi_reset_engine(spi);
+
+		return -EIO;
+	}
+
+	/* restore FIFO thresholds for other transfer paths */
+	regmap_clear_bits(spi->regmap, ATCSPI_CTRL, CTRL_TX_THRES | CTRL_RX_THRES);
+
+	return 0;
+}
+
 static int atcspi_xfer_data_poll(struct atcspi_dev *spi,
 				 const struct spi_mem_op *op)
 {
@@ -151,6 +366,8 @@ static int atcspi_xfer_data_poll(struct atcspi_dev *spi,
 	int num_byte;
 	int ret = 0;
 
+	regmap_write(spi->regmap, ATCSPI_CMD, op->cmd.opcode);
+
 	num_byte = spi->data_merge ? 4 : 1;
 	while (trans_bytes) {
 		if (op->data.dir == SPI_MEM_DATA_OUT) {
@@ -249,7 +466,6 @@ static void atcspi_prepare_trans(struct atcspi_dev *spi,
 	atcspi_set_trans_ctl(spi, op);
 	if (op->addr.nbytes)
 		regmap_write(spi->regmap, ATCSPI_ADDR, op->addr.val);
-	regmap_write(spi->regmap, ATCSPI_CMD, op->cmd.opcode);
 }
 
 static int atcspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
@@ -313,6 +529,8 @@ static int atcspi_dma_trans(struct atcspi_dev *spi,
 	int timeout;
 	int ret;
 
+	regmap_write(spi->regmap, ATCSPI_CMD, op->cmd.opcode);
+
 	regmap_read(spi->regmap, ATCSPI_CTRL, &ctrl);
 	ctrl |= CTRL_TX_DMA_EN | CTRL_RX_DMA_EN;
 	regmap_write(spi->regmap, ATCSPI_CTRL, ctrl);
@@ -373,12 +591,16 @@ static int atcspi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
 	if (op->data.nbytes) {
 		if (spi->use_dma && op->data.nbytes >= ATCSPI_DMA_THRESHOLD)
 			ret = atcspi_dma_trans(spi, op);
+		else if (spi->irq)
+			ret = atcspi_xfer_data_irq(spi, op);
 		else
 			ret = atcspi_xfer_data_poll(spi, op);
 		if (ret) {
 			dev_info(spi->dev, "SPI transmission failed\n");
 			goto exec_mem_exit;
 		}
+	} else {
+		regmap_write(spi->regmap, ATCSPI_CMD, op->cmd.opcode);
 	}
 
 	ret = regmap_read_poll_timeout(spi->regmap,
@@ -403,20 +625,12 @@ static const struct spi_controller_mem_ops atcspi_mem_ops = {
 
 static int atcspi_setup(struct atcspi_dev *spi)
 {
-	unsigned int ctrl_val;
 	unsigned int val;
 	int actual_spi_sclk_f;
 	int ret;
 	unsigned char div;
 
-	ctrl_val = CTRL_TX_FIFO_RST | CTRL_RX_FIFO_RST | CTRL_SPI_RST;
-	regmap_write(spi->regmap, ATCSPI_CTRL, ctrl_val);
-	ret = regmap_read_poll_timeout(spi->regmap,
-				       ATCSPI_CTRL,
-				       val,
-				       !(val & ctrl_val),
-				       0,
-				       ATCSPI_RDY_TIMEOUT_US);
+	ret = atcspi_reset_engine(spi);
 	if (ret)
 		return dev_err_probe(spi->dev, ret,
 				     "Timed out waiting for ATCSPI_CTRL\n");
@@ -586,6 +800,27 @@ static int atcspi_probe(struct platform_device *pdev)
 			spi->use_dma = true;
 	}
 
+	spi->irq = platform_get_irq_optional(pdev, 0);
+	if (spi->irq == -ENXIO)
+		spi->irq = 0;
+	else if (spi->irq < 0)
+		return dev_err_probe(spi->dev, spi->irq,
+				     "Failed to get IRQ\n");
+
+	if (spi->irq) {
+		init_completion(&spi->xfer_done);
+		regmap_write(spi->regmap, ATCSPI_INTR_EN, 0);
+
+		ret = devm_request_irq(&pdev->dev, spi->irq, atcspi_irq, 0,
+				       dev_name(&pdev->dev), spi);
+		if (ret) {
+			dev_info(spi->dev,
+				 "Failed to request IRQ %d, fallback to polling\n",
+				 spi->irq);
+			spi->irq = 0;
+		}
+	}
+
 	ret = devm_spi_register_controller(&pdev->dev, host);
 	if (ret)
 		return dev_err_probe(spi->dev, ret,

-- 
2.56.0

[PATCH 18/25] spi: atcspi200: allow building for Metanoia SoCs

[Benoît Monin]

The Metanoia MT2824 integrates the Andes ATCSPI200 SPI controller. Allow
the driver to be built for ARCH_METANOIA.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/spi/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 49088e5886d3..f8188de1b802 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -152,7 +152,7 @@ config SPI_ARMADA_3700
 
 config SPI_ATCSPI200
 	tristate "Andes ATCSPI200 SPI controller"
-	depends on ARCH_ANDES || COMPILE_TEST
+	depends on ARCH_ANDES || ARCH_METANOIA || COMPILE_TEST
 	help
 	  SPI driver for Andes ATCSPI200 SPI controller.
 	  ATCSPI200 controller supports DMA and PIO modes. When DMA

-- 
2.56.0

[PATCH 19/25] watchdog: atcwdt200: allow building for Metanoia SoCs

[Benoît Monin]

The Metanoia MT2824 integrates the Andes ATCWDT200 watchdog. Allow the
driver to be built for ARCH_METANOIA.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/watchdog/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index f7d0a0c2c0ef..2499a6612f85 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -2148,7 +2148,7 @@ config WATCHDOG_RTAS
 
 config ATCWDT200_WATCHDOG
 	tristate "Andes ATCWDT200 Watchdog support"
-	depends on ARCH_ANDES || COMPILE_TEST
+	depends on ARCH_ANDES || ARCH_METANOIA || COMPILE_TEST
 	help
 	  Driver for the Andes ATCWDT200 watchdog timer. It provides access to
 	  programmable reset and interrupt counters with clock-source dependent

-- 
2.56.0

[PATCH 20/25] mmc: sdhci-of-dwcmshc: add MT2824 support

[Benoît Monin]

The Metanoia MT2824 has a DWC MSHC 2.00a controller with the DWC eMMC/SD
PHY. The evaluation board has a switch that allows connecting the
controller to either an SD card slot or an eMMC; the switch is only
changed between boots.

Add the "metanoia,mt2824-dwcmshc" compatible string and the special
handling needed by the controller and PHY.

Writing to the low byte of the HOST_CONTROL2 register breaks the response
of the next command, even if the value is unchanged. Add a .write_w()
callback to skip the HOST_CONTROL2 register write if its value is
unchanged, and reset the CMD and DATA lines after every change to the
register.

The transmit clock is not stable when CLOCK_CONTROL reports Internal
Clock Stable. Add a 1 ms delay before SD Clock Enable, and clear the
HOST_CTRL3 command conflict check, which breaks tuning at 200 MHz.

The card type on the evaluation board cannot be determined because the
DIP switch that selects it cannot be read by the SoC. Implement card
probing by starting with the eMMC at 1.8 V. Fall back to the SD slot at
3.3 V after a few attempts.

The SD Bus Voltage Select of POWER_CONTROL also drives the EMMC_VSEL
pull-up rail. Ask for 1.8 V whenever the pads run at 1.8 V: for an eMMC,
and for a UHS SD card at 1.8 V signaling. On the evaluation board the SD
VDD rail remains at 3.3 V, so only the pull-up rail changes. Ignore
ios.signal_voltage until the card is powered on because the core powers
up with the value left over from the previous session. Program the rail
before the core enables the new signaling, reconfigure the PHY pads after
each switch, and set the 1.8 V Signal Enable bit on a reset of all when
the pads are at 1.8 V.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/mmc/host/Kconfig            |   1 +
 drivers/mmc/host/sdhci-of-dwcmshc.c | 505 ++++++++++++++++++++++++++++++++++++
 2 files changed, 506 insertions(+)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 79bfc425e7c7..6237d8c352cd 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -244,6 +244,7 @@ config MMC_SDHCI_OF_DWCMSHC
 	depends on OF
 	depends on COMMON_CLK
 	select MMC_CQHCI
+	select MMC_SDHCI_IO_ACCESSORS
 	help
 	  This selects Synopsys DesignWare Cores Mobile Storage Controller
 	  support.
diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index 09702022e708..cb248fc572e2 100644
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -45,6 +45,7 @@
 /* HPE GSC SoC MSHCCS register */
 #define HPE_GSC_MSHCCS_SCGSYNCDIS	BIT(18)
 #define DWCMSHC_CARD_IS_EMMC		BIT(0)
+#define DWCMSHC_EMMC_RST_N		BIT(2)
 #define DWCMSHC_ENHANCED_STROBE		BIT(8)
 #define DWCMSHC_EMMC_ATCTRL		0x40
 #define DWCMSHC_AT_STAT			0x44
@@ -85,6 +86,19 @@
 #define CV18XX_TUNE_STEP			1
 #define CV18XX_RETRY_TUNING_MAX			50
 
+/* Metanoia MT2824: HOST_CTRL3 sampling edge and PHY pad settings */
+#define MT2824_HOST_CTRL3_NEGEDGE_DATAOUT	BIT(1)
+/* 1.8 V eMMC probe attempts before falling back to the SD slot */
+#define MT2824_PROBE_ATTEMPTS			2
+/* PHY pad settings of the MT2824 pad ring */
+#define MT2824_PHY_PAD_SP_3V3			0x9
+#define MT2824_PHY_PAD_SP_1V8			0x8
+#define MT2824_PHY_PAD_SN			0x8
+#define MT2824_PHY_TXSLEW			0x1
+#define MT2824_PHY_TXSLEW_P_STROBE		0x3
+#define MT2824_PHY_SMPLDL_CNFG			0x0c
+#define MT2824_PHY_ATDL_CNFG			0x0c
+
 /* Rockchip specific Registers */
 #define DWCMSHC_EMMC_DLL_CTRL		0x800
 #define DWCMSHC_EMMC_DLL_RXCLK		0x804
@@ -2108,6 +2122,470 @@ static const struct sdhci_ops sdhci_dwcmshc_k230_ops = {
 	.adma_write_desc = dwcmshc_adma_write_desc,
 };
 
+/* Metanoia MT2824 */
+
+enum mt2824_card_type {
+	MT2824_CARD_UNKNOWN,	/* eMMC-first probe in progress */
+	MT2824_CARD_EMMC,
+	MT2824_CARD_SD,
+};
+
+struct mt2824_priv {
+	enum mt2824_card_type card_type;
+	unsigned int probe_attempts;
+};
+
+static struct mt2824_priv *mt2824_get_priv(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
+
+	return dwc_priv->priv;
+}
+
+/*
+ * The board jumper selects the SD slot or the eMMC and is only changed
+ * between boots. Until the type is known, probe the eMMC at 1.8 V first.
+ */
+static bool mt2824_card_is_emmc(struct sdhci_host *host)
+{
+	struct mt2824_priv *priv = mt2824_get_priv(host);
+
+	if (priv) {
+		if (priv->card_type == MT2824_CARD_EMMC)
+			return true;
+		if (priv->card_type == MT2824_CARD_SD)
+			return false;
+
+		/* eMMC-first probe; an SD card does not answer CMD1 */
+		return true;
+	}
+
+	return (host->mmc->caps2 & MMC_CAP2_NO_SD) ||
+	       (host->mmc->card && mmc_card_mmc(host->mmc->card));
+}
+
+/* The pads follow the signal voltage, and an eMMC is always at 1.8 V */
+static bool mt2824_pads_1v8(struct sdhci_host *host)
+{
+	return mt2824_card_is_emmc(host) ||
+	       (host->mmc->ios.power_mode == MMC_POWER_ON &&
+		host->mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_180);
+}
+
+/*
+ * On this controller, a write of the HOST_CONTROL2 low byte breaks the
+ * response of the command that follows, even when the value does not
+ * change. Drop the writes that do not change the register.
+ */
+static void mt2824_write_w(struct sdhci_host *host, u16 val, int reg)
+{
+	if (reg == SDHCI_HOST_CONTROL2 && sdhci_readw(host, reg) == val)
+		return;
+
+	writew(val, host->ioaddr + reg);
+}
+
+/*
+ * A timing change must write the new bus speed mode to HOST_CONTROL2.
+ * Reset the CMD and DATA lines after the write, while the card clock is
+ * off, so that the next command gets a good response.
+ */
+static void mt2824_set_uhs_signaling(struct sdhci_host *host,
+				     unsigned int timing)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
+	u32 reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;
+	u16 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+	u8 ctrl;
+
+	ctrl = sdhci_readb(host, reg);
+	ctrl &= ~MT2824_HOST_CTRL3_NEGEDGE_DATAOUT;
+	if (timing == MMC_TIMING_MMC_DDR52 ||
+	    timing == MMC_TIMING_UHS_DDR50)
+		ctrl |= MT2824_HOST_CTRL3_NEGEDGE_DATAOUT;
+	sdhci_writeb(host, ctrl, reg);
+
+	dwcmshc_set_uhs_signaling(host, timing);
+	if (sdhci_readw(host, SDHCI_HOST_CONTROL2) != ctrl2)
+		dwcmshc_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+}
+
+/* PHY pads and delay lines of the MT2824 pad ring, then release the PHY */
+static int mt2824_phy_init(struct sdhci_host *host, bool v1v8)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
+	u32 rxsel = v1v8 ? PHY_PAD_RXSEL_1V8 : PHY_PAD_RXSEL_3V3;
+	u32 val;
+	int ret;
+
+	val = rxsel;
+	val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP);
+	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, MT2824_PHY_TXSLEW);
+	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, MT2824_PHY_TXSLEW);
+	sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);
+	sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);
+	sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);
+
+	val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, MT2824_PHY_TXSLEW);
+	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, MT2824_PHY_TXSLEW);
+	sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);
+
+	val = PHY_PAD_RXSEL_1V8;
+	val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN);
+	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, MT2824_PHY_TXSLEW_P_STROBE);
+	val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, MT2824_PHY_TXSLEW);
+	sdhci_writew(host, val, PHY_STBPAD_CNFG_R);
+
+	sdhci_writeb(host, MT2824_PHY_SMPLDL_CNFG, PHY_SMPLDL_CNFG_R);
+	sdhci_writeb(host, MT2824_PHY_ATDL_CNFG, PHY_ATDL_CNFG_R);
+
+	val = sdhci_readl(host, PHY_CNFG_R);
+	val &= ~(PHY_CNFG_PAD_SP_MASK | PHY_CNFG_PAD_SN_MASK);
+	val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK,
+			  v1v8 ? MT2824_PHY_PAD_SP_1V8 : MT2824_PHY_PAD_SP_3V3);
+	val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, MT2824_PHY_PAD_SN);
+	sdhci_writel(host, val, PHY_CNFG_R);
+
+	ret = read_poll_timeout(sdhci_readl, val, val & PHY_CNFG_PHY_PWRGOOD_MASK,
+				1000, 20000, false, host, PHY_CNFG_R);
+	if (ret) {
+		dev_err(mmc_dev(host->mmc), "PHY power never became good\n");
+		return ret;
+	}
+
+	sdhci_writel(host, val | PHY_CNFG_RSTN_DEASSERT, PHY_CNFG_R);
+
+	/*
+	 * Stop the clocks while a tuning phase changes, avoids a glitch. Only
+	 * a reset clears the bit, and AT_CTRL_R must not be written while
+	 * SAMPLE_CLK_SEL is set, so write it only when it is missing.
+	 */
+	val = sdhci_readl(host, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
+	if (!(val & AT_CTRL_TUNE_CLK_STOP_EN))
+		sdhci_writel(host, val | AT_CTRL_TUNE_CLK_STOP_EN,
+			     dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
+
+	return 0;
+}
+
+static bool mt2824_wait_clk_stable(struct sdhci_host *host, u16 *clk,
+				   const char *what)
+{
+	u16 val;
+
+	if (read_poll_timeout_atomic(sdhci_readw, val,
+				     val & SDHCI_CLOCK_INT_STABLE, 10, 150000,
+				     false, host, SDHCI_CLOCK_CONTROL)) {
+		dev_err(mmc_dev(host->mmc), "%s never stabilised\n", what);
+		sdhci_err_stats_inc(host, CTRL_TIMEOUT);
+		sdhci_dumpregs(host);
+		return false;
+	}
+
+	*clk = val;
+	return true;
+}
+
+/*
+ * sdhci_enable_clk() with a settle time: the transmit clock is not stable
+ * yet when CLOCK_CONTROL reports the internal clock stable, and the first
+ * command after the SD Clock Enable then gets a bad response.
+ */
+static void mt2824_enable_clk(struct sdhci_host *host, u16 clk)
+{
+	clk |= SDHCI_CLOCK_INT_EN;
+	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+	if (!mt2824_wait_clk_stable(host, &clk, "internal clock"))
+		return;
+
+	if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
+		clk |= SDHCI_CLOCK_PLL_EN;
+		clk &= ~SDHCI_CLOCK_INT_STABLE;
+		sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+		if (!mt2824_wait_clk_stable(host, &clk, "PLL clock"))
+			return;
+	}
+
+	mdelay(1);
+	sdhci_writew(host, clk | SDHCI_CLOCK_CARD_EN, SDHCI_CLOCK_CONTROL);
+}
+
+static void mt2824_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
+	struct mmc_host *mmc = host->mmc;
+	u32 reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;
+	u8 ctrl;
+
+	/* The conflict check breaks tuning at 200 MHz */
+	ctrl = sdhci_readb(host, reg);
+	ctrl &= ~DWCMSHC_HOST_CTRL3_CMD_CONFLICT;
+	sdhci_writeb(host, ctrl, reg);
+
+	/* sdhci_set_clock() with mt2824_enable_clk() */
+	mmc->actual_clock = 0;
+	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+	if (clock)
+		mt2824_enable_clk(host, sdhci_calc_clk(host, clock,
+						       &mmc->actual_clock));
+}
+
+/* The controller must know that the card is an eMMC (EMMC_CTRL_R, 16 bit) */
+static void mt2824_update_card_is_emmc(struct sdhci_host *host, bool is_emmc)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
+	u32 reg = dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL;
+	u16 ctrl = sdhci_readw(host, reg);
+
+	if (is_emmc)
+		ctrl |= DWCMSHC_CARD_IS_EMMC;
+	else
+		ctrl &= ~DWCMSHC_CARD_IS_EMMC;
+	sdhci_writew(host, ctrl, reg);
+}
+
+/*
+ * The SD Bus Voltage Select of POWER_CONTROL also sets the EMMC_VSEL output,
+ * which picks the board rail of the card signal pull-ups: 3.3 V for an SD
+ * card, 1.8 V for an eMMC or a UHS SD card. The core asks for the VDD voltage
+ * (3.3 V), so ask for 1.8 V when the pads use 1.8 V. On an SD card this only
+ * moves the pull-ups: the SD VDD rail stays at 3.3 V on this board.
+ */
+static void mt2824_set_power(struct sdhci_host *host, unsigned char mode,
+			     unsigned short vdd)
+{
+	if (mode != MMC_POWER_OFF && mt2824_pads_1v8(host))
+		vdd = ilog2(MMC_VDD_165_195);
+
+	sdhci_set_power(host, mode, vdd);
+}
+
+/*
+ * The PHY pads follow every signal voltage change, in both directions:
+ * the core switches back to 3.3 V on each power up.
+ */
+static int mt2824_start_signal_voltage_switch(struct mmc_host *mmc,
+					      struct mmc_ios *ios)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	u16 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+	int ret;
+
+	/*
+	 * The pull-up rail must change before the generic switch enables the
+	 * new signaling otherwise the lines see an invalid voltage.
+	 */
+	mt2824_set_power(host, ios->power_mode, ios->vdd);
+
+	ret = sdhci_start_signal_voltage_switch(mmc, ios);
+	if (ret)
+		return ret;
+
+	/* a changed 1.8V Signal Enable breaks the next response */
+	if (sdhci_readw(host, SDHCI_HOST_CONTROL2) != ctrl2)
+		dwcmshc_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+
+	ret = mt2824_phy_init(host, mt2824_pads_1v8(host));
+	if (!ret)
+		mt2824_update_card_is_emmc(host, mt2824_card_is_emmc(host));
+
+	return ret;
+}
+
+static void mt2824_reset(struct sdhci_host *host, u8 mask)
+{
+	dwcmshc_reset(host, mask);
+
+	if (mask & SDHCI_RESET_ALL) {
+		u16 old = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+		u16 ctrl2 = old;
+
+		mt2824_phy_init(host, mt2824_pads_1v8(host));
+
+		/*
+		 * A reset clears HOST_CONTROL2. Write the bits that the core
+		 * would set later now, in one write followed by a reset of the
+		 * CMD and DATA lines: the core writes them in the request path,
+		 * right before a command. The core sets Host Version 4 Enable
+		 * after each reset of all, and 64-bit Addressing before the
+		 * first DMA request. CMD23 Enable has no effect until a request
+		 * uses CMD23. 1.8 V pads need 1.8V Signal Enable.
+		 */
+		if (host->v4_mode)
+			ctrl2 |= SDHCI_CTRL_V4_MODE;
+		if (host->flags & SDHCI_USE_64_BIT_DMA)
+			ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
+		ctrl2 |= SDHCI_CMD23_ENABLE;
+		if (mt2824_pads_1v8(host))
+			ctrl2 |= SDHCI_CTRL_VDD_180;
+		if (ctrl2 != old) {
+			sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
+			dwcmshc_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+		}
+
+		/* the reset also cleared CARD_IS_EMMC */
+		mt2824_update_card_is_emmc(host, mt2824_card_is_emmc(host));
+	}
+}
+
+static void mt2824_hw_reset(struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
+	u32 reg = dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL;
+	u16 ctrl, clk;
+
+	/* only an eMMC has RST_n: known from the DT, or from the card */
+	if (!(host->mmc->caps2 & MMC_CAP2_NO_SD) &&
+	    (!host->mmc->card || !mmc_card_mmc(host->mmc->card)))
+		return;
+
+	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+	clk &= ~SDHCI_CLOCK_CARD_EN;
+	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+	/* EMMC_CTRL_R is a 16 bit register */
+	ctrl = sdhci_readw(host, reg);
+	sdhci_writew(host, ctrl & ~DWCMSHC_EMMC_RST_N, reg);
+	usleep_range(10000, 11000);
+	sdhci_writew(host, ctrl | DWCMSHC_EMMC_RST_N, reg);
+	/* tRSCA: the device needs 200 us after RST_n before a command */
+	usleep_range(300, 1000);
+
+	sdhci_enable_clk(host, clk);
+}
+
+/*
+ * With no card type from the DT, look for an eMMC only, at 1.8 V: an eMMC
+ * answers CMD1, an SD card does not, so no 3.3 V signal reaches an eMMC.
+ * The board jumper is only changed between boots. After a few power cycles
+ * without a card, switch to the SD slot at 3.3 V and latch that type for the
+ * rest of the boot. An empty slot goes to the SD search at once.
+ */
+static void mt2824_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	struct mt2824_priv *priv = mt2824_get_priv(host);
+	bool no_card;
+
+	if (ios->power_mode != MMC_POWER_OFF || mmc->card ||
+	    priv->card_type != MT2824_CARD_UNKNOWN) {
+		sdhci_set_ios(mmc, ios);
+		return;
+	}
+
+	no_card = mmc->ops->get_cd && !mmc->ops->get_cd(mmc);
+	if (no_card || ++priv->probe_attempts >= MT2824_PROBE_ATTEMPTS) {
+		priv->card_type = MT2824_CARD_SD;
+		host->mmc_host_ops.set_ios = sdhci_set_ios;
+		mmc->caps2 &= ~MMC_CAP2_NO_SD;
+		mmc->caps2 |= MMC_CAP2_NO_MMC;
+		host->flags |= SDHCI_SIGNALING_330;
+		dev_dbg(mmc_dev(mmc), "no eMMC at 1.8 V, looking for an SD card\n");
+	}
+
+	sdhci_set_ios(mmc, ios);
+}
+
+/*
+ * The device tree did not name the card, and the core identified one
+ * (mmc.c and sd.c call init_card after CMD2). Latch the type for the rest of
+ * the boot and set the pads and CARD_IS_EMMC for it.
+ */
+static void mt2824_init_card(struct mmc_host *mmc, struct mmc_card *card)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
+	struct mt2824_priv *priv = dwc_priv->priv;
+	bool is_emmc = mmc_card_mmc(card);
+
+	/* mmc->card is still NULL on the first init of this card */
+	if (!mmc->card)
+		dev_info(mmc_dev(mmc), "%s found\n", is_emmc ? "eMMC" : "SD card");
+
+	priv->card_type = is_emmc ? MT2824_CARD_EMMC : MT2824_CARD_SD;
+	priv->probe_attempts = 0;
+	host->mmc_host_ops.set_ios = sdhci_set_ios;
+
+	if (is_emmc) {
+		dwc_priv->flags |= FLAG_IO_FIXED_1V8;
+		mmc->caps |= MMC_CAP_NONREMOVABLE;
+		mmc->caps2 |= MMC_CAP2_NO_SD;
+		mmc->caps2 &= ~MMC_CAP2_NO_MMC;
+		host->flags &= ~SDHCI_SIGNALING_330;
+		host->flags |= SDHCI_SIGNALING_180;
+		mt2824_phy_init(host, true);
+	} else {
+		dwc_priv->flags &= ~FLAG_IO_FIXED_1V8;
+		mmc->caps &= ~MMC_CAP_NONREMOVABLE;
+		mmc->caps2 &= ~MMC_CAP2_NO_SD;
+		mmc->caps2 |= MMC_CAP2_NO_MMC;
+		host->flags |= SDHCI_SIGNALING_330;
+		mt2824_phy_init(host, mt2824_pads_1v8(host));
+	}
+
+	mt2824_update_card_is_emmc(host, is_emmc);
+}
+
+/*
+ * The controller can drive an SD card slot or an eMMC. A board jumper
+ * selects one; it is only changed between boots. "no-sd" (eMMC) or
+ * "no-mmc" (SD card) in the device tree fixes the card type. Without them,
+ * probe the eMMC at 1.8 V first, then fall back to the SD slot at 3.3 V.
+ */
+static int mt2824_init(struct device *dev, struct sdhci_host *host,
+		       struct dwcmshc_priv *dwc_priv)
+{
+	struct mmc_host *mmc = host->mmc;
+	struct mt2824_priv *priv;
+	bool is_emmc;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+	dwc_priv->priv = priv;
+
+	mmc->caps2 |= MMC_CAP2_NO_SDIO;
+	host->mmc_host_ops.start_signal_voltage_switch =
+		mt2824_start_signal_voltage_switch;
+
+	if (mmc->caps2 & MMC_CAP2_NO_SD) {
+		priv->card_type = MT2824_CARD_EMMC;
+		is_emmc = true;
+	} else if (mmc->caps2 & MMC_CAP2_NO_MMC) {
+		priv->card_type = MT2824_CARD_SD;
+		is_emmc = false;
+	} else {
+		/* look for an eMMC first, with no 3.3 V signaling */
+		dev_info(dev, "card type detection, eMMC first at 1.8 V\n");
+		priv->card_type = MT2824_CARD_UNKNOWN;
+		mmc->caps2 |= MMC_CAP2_NO_SD;
+		host->flags &= ~SDHCI_SIGNALING_330;
+		host->mmc_host_ops.init_card = mt2824_init_card;
+		host->mmc_host_ops.set_ios = mt2824_set_ios;
+		return 0;
+	}
+
+	dev_info(dev, "%s interface from the device tree\n",
+		 is_emmc ? "eMMC" : "SD");
+	if (is_emmc) {
+		/* an eMMC is soldered to a fixed 1.8 V rail */
+		dwc_priv->flags |= FLAG_IO_FIXED_1V8;
+		mmc->caps |= MMC_CAP_NONREMOVABLE;
+		mmc->caps2 &= ~MMC_CAP2_NO_MMC;
+		host->flags &= ~SDHCI_SIGNALING_330;
+		host->flags |= SDHCI_SIGNALING_180;
+	}
+
+	return 0;
+}
+
 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_pdata = {
 	.pdata = {
 		.ops = &sdhci_dwcmshc_ops,
@@ -2184,6 +2662,29 @@ static const struct rockchip_pltfm_data sdhci_dwcmshc_rk3588_pdata = {
 	.revision = 1,
 };
 
+static const struct sdhci_ops sdhci_dwcmshc_mt2824_ops = {
+	.write_w		= mt2824_write_w,
+	.set_clock		= mt2824_set_clock,
+	.set_power		= mt2824_set_power,
+	.set_bus_width		= sdhci_set_bus_width,
+	.set_uhs_signaling	= mt2824_set_uhs_signaling,
+	.get_max_clock		= dwcmshc_get_max_clock,
+	.reset			= mt2824_reset,
+	.hw_reset		= mt2824_hw_reset,
+	.adma_write_desc	= dwcmshc_adma_write_desc,
+};
+
+static const struct dwcmshc_pltfm_data sdhci_dwcmshc_mt2824_pdata = {
+	.pdata = {
+		.ops = &sdhci_dwcmshc_mt2824_ops,
+		.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+			  SDHCI_QUIRK_BROKEN_DMA |
+			  SDHCI_QUIRK_BROKEN_ADMA,
+		.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
+	},
+	.init = mt2824_init,
+};
+
 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_th1520_pdata = {
 	.pdata = {
 		.ops = &sdhci_dwcmshc_th1520_ops,
@@ -2350,6 +2851,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
 		.compatible = "canaan,k230-sdio",
 		.data = &k230_sdio_data.dwcmshc_pdata,
 	},
+	{
+		.compatible = "metanoia,mt2824-dwcmshc",
+		.data = &sdhci_dwcmshc_mt2824_pdata,
+	},
 	{
 		.compatible = "rockchip,rk3588-dwcmshc",
 		.data = &sdhci_dwcmshc_rk3588_pdata,

-- 
2.56.0

[PATCH 21/25] mmc: sdhci-of-dwcmshc: add MT2824 tuning and HS400 support

[Benoît Monin]

The MT2824 databook names SDR104 and HS200 as the modes that need
tuning. The controller has a 128-tap sampling delay line, so scan every
center phase code, find the longest run of phases that return a good
tuning block, and select the middle phase. Do not tune at DDR50, where
the scan fails at every phase and the fixed sampling clock works.

During the scan, a CMD19 timeout at a bad phase can be followed by a
data CRC interrupt after the request has completed. Drop data interrupts
that arrive with no data request while scanning.

HS400 needs the PHY DLL locked on the card clock. Configure and enable
the DLL by hand after the clock is set, and reset the CMD and DATA
lines.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/mmc/host/sdhci-of-dwcmshc.c | 201 +++++++++++++++++++++++++++++++++++-
 1 file changed, 200 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index cb248fc572e2..324ae93295af 100644
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -10,6 +10,7 @@
 #include <linux/acpi.h>
 #include <linux/arm-smccc.h>
 #include <linux/bitfield.h>
+#include <linux/bitmap.h>
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
 #include <linux/dma-mapping.h>
@@ -86,8 +87,12 @@
 #define CV18XX_TUNE_STEP			1
 #define CV18XX_RETRY_TUNING_MAX			50
 
-/* Metanoia MT2824: HOST_CTRL3 sampling edge and PHY pad settings */
+/* Metanoia MT2824: HOST_CTRL3 sampling edge bits and software tuning */
 #define MT2824_HOST_CTRL3_NEGEDGE_DATAOUT	BIT(1)
+#define MT2824_AT_STAT_CENTER_PH_MASK		GENMASK(6, 0)
+#define MT2824_TUNING_PHASES			128	/* DWC_MSHC_DL_CW = 7 */
+/* narrowest passing window accepted, ~8 % of the 128-tap delay line */
+#define MT2824_TUNING_MIN_WINDOW		10
 /* 1.8 V eMMC probe attempts before falling back to the SD slot */
 #define MT2824_PROBE_ATTEMPTS			2
 /* PHY pad settings of the MT2824 pad ring */
@@ -98,6 +103,10 @@
 #define MT2824_PHY_TXSLEW_P_STROBE		0x3
 #define MT2824_PHY_SMPLDL_CNFG			0x0c
 #define MT2824_PHY_ATDL_CNFG			0x0c
+#define MT2824_PHY_DLL_CNFG1			0x20
+#define MT2824_PHY_DLLDL_CNFG			0x60
+#define MT2824_PHY_DLL_LOCKED			BIT(0)
+#define MT2824_PHY_DLL_LOCK_ERR			BIT(1)
 
 /* Rockchip specific Registers */
 #define DWCMSHC_EMMC_DLL_CTRL		0x800
@@ -245,6 +254,7 @@
 #define DLL_ERROR_STS			BIT(1)
 
 #define FLAG_IO_FIXED_1V8	BIT(0)
+#define FLAG_SW_TUNING		BIT(1)	/* MT2824: tuning scan in progress */
 
 #define BOUNDARY_OK(addr, len) \
 	((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
@@ -2271,6 +2281,38 @@ static int mt2824_phy_init(struct sdhci_host *host, bool v1v8)
 	return 0;
 }
 
+/* HS400 needs the PHY DLL locked on the card clock; lock it by hand */
+static void mt2824_set_dll(struct sdhci_host *host)
+{
+	u16 clk;
+	u8 status;
+	int ret;
+
+	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+	clk &= ~SDHCI_CLOCK_CARD_EN;
+	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+	sdhci_writeb(host, MT2824_PHY_DLL_CNFG1, PHY_DLL_CNFG1_R);
+	sdhci_writeb(host, MT2824_PHY_DLLDL_CNFG, PHY_DLLDL_CNFG_R);
+
+	sdhci_enable_clk(host, clk);
+	usleep_range(10, 20);
+
+	sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R);
+	ret = read_poll_timeout(sdhci_readb, status,
+				status & MT2824_PHY_DLL_LOCKED, 10, 150000,
+				false, host, PHY_DLL_STATUS_R);
+	if (ret) {
+		dev_err(mmc_dev(host->mmc), "PHY DLL did not lock: 0x%02x\n",
+			status);
+		return;
+	}
+
+	if (status & MT2824_PHY_DLL_LOCK_ERR)
+		dev_err(mmc_dev(host->mmc), "PHY DLL locked with error: 0x%02x\n",
+			status);
+}
+
 static bool mt2824_wait_clk_stable(struct sdhci_host *host, u16 *clk,
 				   const char *what)
 {
@@ -2332,6 +2374,11 @@ static void mt2824_set_clock(struct sdhci_host *host, unsigned int clock)
 	if (clock)
 		mt2824_enable_clk(host, sdhci_calc_clk(host, clock,
 						       &mmc->actual_clock));
+
+	if (clock && host->timing == MMC_TIMING_MMC_HS400) {
+		mt2824_set_dll(host);
+		dwcmshc_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+	}
 }
 
 /* The controller must know that the card is an eMMC (EMMC_CTRL_R, 16 bit) */
@@ -2460,6 +2507,156 @@ static void mt2824_hw_reset(struct sdhci_host *host)
 	sdhci_enable_clk(host, clk);
 }
 
+/*
+ * Software tuning: try every center phase code of the tuning delay line,
+ * find the longest run of phases that return a good tuning block and
+ * select its middle. The sampling clock only follows the delay line while
+ * SAMPLE_CLK_SEL (SDHCI_CTRL_TUNED_CLK) is set, so set it for the scan and
+ * keep it; SW_TUNE_EN also stays set, so the selected phase code stays in
+ * control of the delay line.
+ */
+static int mt2824_set_center_phase(struct sdhci_host *host, u32 at_stat_reg,
+				   unsigned int phase)
+{
+	u32 at_stat;
+	int ret;
+	u16 clk;
+
+	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+	clk &= ~SDHCI_CLOCK_CARD_EN;
+	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+	at_stat = sdhci_readl(host, at_stat_reg);
+	at_stat &= ~MT2824_AT_STAT_CENTER_PH_MASK;
+	at_stat |= FIELD_PREP(MT2824_AT_STAT_CENTER_PH_MASK, phase);
+	sdhci_writel(host, at_stat, at_stat_reg);
+	/*
+	 * This configuration has no DL2 busy flag: read the phase code back,
+	 * then wait for the worst case of 180 hclk cycles of the delay line
+	 * (2 us covers an hclk of 90 MHz or more).
+	 */
+	ret = read_poll_timeout(sdhci_readl, at_stat,
+				FIELD_GET(MT2824_AT_STAT_CENTER_PH_MASK, at_stat) == phase,
+				0, 100, false, host, at_stat_reg);
+	if (ret)
+		dev_err(mmc_dev(host->mmc), "tuning phase %u not taken\n", phase);
+	udelay(2);
+
+	sdhci_enable_clk(host, clk);
+
+	return ret;
+}
+
+static int mt2824_execute_tuning(struct sdhci_host *host, u32 opcode)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
+	u32 at_ctrl_reg = dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL;
+	u32 at_stat_reg = dwc_priv->vendor_specific_area1 + DWCMSHC_AT_STAT;
+	DECLARE_BITMAP(good, MT2824_TUNING_PHASES);
+	unsigned int start, end, phase, best_start = 0, best_len = 0;
+	u32 at_ctrl;
+	u16 ctrl2;
+	int ret;
+
+	/*
+	 * The controller databook names SDR104 (and HS200) as the modes that
+	 * need tuning. At DDR50 the scan fails at every phase on this
+	 * controller, while the fixed sampling clock works: do not tune.
+	 */
+	if (host->timing == MMC_TIMING_UHS_DDR50)
+		return 0;
+
+	WRITE_ONCE(dwc_priv->flags, dwc_priv->flags | FLAG_SW_TUNING);
+
+	sdhci_reset_tuning(host);
+	bitmap_zero(good, MT2824_TUNING_PHASES);
+
+	/*
+	 * AT_CTRL_R must not be written while SAMPLE_CLK_SEL is set: enable
+	 * software tuning first, then select the tuned sampling clock.
+	 */
+	at_ctrl = sdhci_readl(host, at_ctrl_reg);
+	sdhci_writel(host, at_ctrl | AT_CTRL_SW_TUNE_EN, at_ctrl_reg);
+	ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+	sdhci_writew(host, ctrl2 | SDHCI_CTRL_TUNED_CLK, SDHCI_HOST_CONTROL2);
+	/*
+	 * That HOST_CONTROL2 write breaks the response of the next command:
+	 * send one tuning command for nothing before the scan.
+	 */
+	mmc_send_tuning(host->mmc, opcode, NULL);
+	host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+
+	for (phase = 0; phase < MT2824_TUNING_PHASES; phase++) {
+		ret = mt2824_set_center_phase(host, at_stat_reg, phase);
+		if (ret)
+			goto fail;
+		if (!mmc_send_tuning(host->mmc, opcode, NULL))
+			set_bit(phase, good);
+		host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+	}
+
+	/* the sample delay line is linear, so the phase codes do not wrap */
+	for_each_set_bitrange(start, end, good, MT2824_TUNING_PHASES) {
+		if (end - start > best_len) {
+			best_start = start;
+			best_len = end - start;
+		}
+	}
+	if (best_len < MT2824_TUNING_MIN_WINDOW) {
+		dev_err(mmc_dev(host->mmc), "tuning failed, best window %u\n",
+			best_len);
+		ret = -EIO;
+		goto fail;
+	}
+	phase = best_start + best_len / 2;
+	/* a window at an end of the delay line may be wider than measured */
+	if (!best_start || best_start + best_len == MT2824_TUNING_PHASES)
+		dev_dbg(mmc_dev(host->mmc), "tuning window %u+%u ends at the delay line end\n",
+			best_start, best_len);
+
+	ret = mt2824_set_center_phase(host, at_stat_reg, phase);
+	if (ret)
+		goto fail;
+	dev_dbg(mmc_dev(host->mmc), "tuning phase %u (window %u+%u), AT_STAT %08x\n",
+		phase, best_start, best_len, sdhci_readl(host, at_stat_reg));
+	sdhci_end_tuning(host);
+	WRITE_ONCE(dwc_priv->flags, dwc_priv->flags & ~FLAG_SW_TUNING);
+
+	return 0;
+
+fail:
+	/* clear SAMPLE_CLK_SEL before AT_CTRL_R is written again */
+	sdhci_reset_tuning(host);
+	sdhci_writel(host, at_ctrl, at_ctrl_reg);
+	host->ops->reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+	sdhci_end_tuning(host);
+	WRITE_ONCE(dwc_priv->flags, dwc_priv->flags & ~FLAG_SW_TUNING);
+	return ret;
+}
+
+/*
+ * A tuning command at a bad phase can time out while the card still sends
+ * the tuning block. Its data interrupt then comes when no data transfer is
+ * in progress (host->data is NULL); once the request reset cleared
+ * pending_reset, sdhci counts it as an unexpected interrupt. Drop such
+ * data interrupts while the tuning scan runs. A late interrupt that comes
+ * after the next tuning command started fails that phase only.
+ */
+static u32 mt2824_irq(struct sdhci_host *host, u32 intmask)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
+	u32 stray = intmask & SDHCI_INT_DATA_MASK;
+
+	if (!(READ_ONCE(dwc_priv->flags) & FLAG_SW_TUNING) || host->data || !stray)
+		return intmask;
+
+	sdhci_writel(host, stray, SDHCI_INT_STATUS);
+
+	return intmask & ~stray;
+}
+
 /*
  * With no card type from the DT, look for an eMMC only, at 1.8 V: an eMMC
  * answers CMD1, an SD card does not, so no 3.3 V signal reaches an eMMC.
@@ -2672,6 +2869,8 @@ static const struct sdhci_ops sdhci_dwcmshc_mt2824_ops = {
 	.reset			= mt2824_reset,
 	.hw_reset		= mt2824_hw_reset,
 	.adma_write_desc	= dwcmshc_adma_write_desc,
+	.platform_execute_tuning = mt2824_execute_tuning,
+	.irq			= mt2824_irq,
 };
 
 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_mt2824_pdata = {

-- 
2.56.0

[PATCH 22/25] phy: metanoia: add USB2 PHY driver

[Benoît Monin]

Add a minimal reset-only PHY provider for the Metanoia MT2824 USB2 PHY.
It deasserts the PHY reset required by the DWC2 USB controller on init
and asserts it again on exit.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/phy/Kconfig             |  1 +
 drivers/phy/Makefile            |  1 +
 drivers/phy/metanoia/Kconfig    | 16 ++++++++
 drivers/phy/metanoia/Makefile   |  3 ++
 drivers/phy/metanoia/phy-usb2.c | 88 +++++++++++++++++++++++++++++++++++++++++
 5 files changed, 109 insertions(+)

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 105fbe408aa2..73ef61f1f53d 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -184,6 +184,7 @@ source "drivers/phy/intel/Kconfig"
 source "drivers/phy/lantiq/Kconfig"
 source "drivers/phy/marvell/Kconfig"
 source "drivers/phy/mediatek/Kconfig"
+source "drivers/phy/metanoia/Kconfig"
 source "drivers/phy/microchip/Kconfig"
 source "drivers/phy/motorola/Kconfig"
 source "drivers/phy/mscc/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index c6dd02003bbe..57991b50978c 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_GENERIC_PHY)		+= allwinner/	\
 					   lantiq/	\
 					   marvell/	\
 					   mediatek/	\
+					   metanoia/	\
 					   microchip/	\
 					   motorola/	\
 					   mscc/	\
diff --git a/drivers/phy/metanoia/Kconfig b/drivers/phy/metanoia/Kconfig
new file mode 100644
index 000000000000..b8a49085bb95
--- /dev/null
+++ b/drivers/phy/metanoia/Kconfig
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Phy drivers for Metanoia platforms
+#
+
+config PHY_METANOIA_USB2
+	tristate "Metanoia USB2 PHY reset support"
+	depends on OF && (ARCH_METANOIA || COMPILE_TEST)
+	depends on RESET_CONTROLLER
+	select GENERIC_PHY
+	help
+	  Enable this to support the USB2 PHY reset block that is part
+	  of Metanoia SoCs.
+
+	  This driver only toggles the reset line of the PHY needed by
+	  the DWC2 USB controller.
diff --git a/drivers/phy/metanoia/Makefile b/drivers/phy/metanoia/Makefile
new file mode 100644
index 000000000000..ce1b5f8af15d
--- /dev/null
+++ b/drivers/phy/metanoia/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_PHY_METANOIA_USB2)	+= phy-usb2.o
diff --git a/drivers/phy/metanoia/phy-usb2.c b/drivers/phy/metanoia/phy-usb2.c
new file mode 100644
index 000000000000..b06d423eada7
--- /dev/null
+++ b/drivers/phy/metanoia/phy-usb2.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2026 Metanoia Communications Inc.
+ *
+ * Author: Jun Chang <jun.chang@metanoia-comm.com>
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+struct metanoia_usb2phy {
+	struct reset_control *reset;
+};
+
+static int metanoia_usb2phy_init(struct phy *phy)
+{
+	struct metanoia_usb2phy *priv = phy_get_drvdata(phy);
+	int ret;
+
+	ret = reset_control_deassert(priv->reset);
+	if (ret)
+		dev_err(&phy->dev, "failed to reset phy: %d\n", ret);
+
+	return ret;
+}
+
+static int metanoia_usb2phy_exit(struct phy *phy)
+{
+	struct metanoia_usb2phy *priv = phy_get_drvdata(phy);
+
+	return reset_control_assert(priv->reset);
+}
+
+static const struct phy_ops metanoia_usb2phy_ops = {
+	.init = metanoia_usb2phy_init,
+	.exit = metanoia_usb2phy_exit,
+	.owner = THIS_MODULE,
+};
+
+static int metanoia_usb2phy_probe(struct platform_device *pdev)
+{
+	struct phy_provider *phy_provider;
+	struct device *dev = &pdev->dev;
+	struct metanoia_usb2phy *priv;
+	struct phy *phy;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->reset = devm_reset_control_get_exclusive(dev, "usb2-phy");
+	if (IS_ERR(priv->reset))
+		return dev_err_probe(dev, PTR_ERR(priv->reset),
+				     "failed to get usb2-phy reset\n");
+
+	phy = devm_phy_create(dev, NULL, &metanoia_usb2phy_ops);
+	if (IS_ERR(phy))
+		return dev_err_probe(dev, PTR_ERR(phy),
+				     "failed to create usb2 phy\n");
+
+	phy_set_drvdata(phy, priv);
+
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id metanoia_usb2phy_of_match[] = {
+	{ .compatible = "metanoia,mt2824-usb2-phy" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, metanoia_usb2phy_of_match);
+
+static struct platform_driver metanoia_usb2phy_driver = {
+	.probe = metanoia_usb2phy_probe,
+	.driver = {
+		.name = "metanoia-usb2-phy",
+		.of_match_table = metanoia_usb2phy_of_match,
+	},
+};
+module_platform_driver(metanoia_usb2phy_driver);
+
+MODULE_DESCRIPTION("Metanoia USB2 PHY driver");
+MODULE_AUTHOR("Jun Chang <jun.chang@metanoia-comm.com>");
+MODULE_LICENSE("GPL");

-- 
2.56.0

[PATCH 23/25] usb: dwc2: add support for Metanoia MT2824

[Benoît Monin]

Add core parameters for the Metanoia MT2824 DWC2 controller: high-speed
UTMI PHY, no host DMA, and no OTG HNP/SRP support.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/usb/dwc2/params.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 091bfcfef753..d6a6a581d021 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -303,6 +303,17 @@ static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
 	p->hird_threshold_en = false;
 }
 
+static void dwc2_set_metanoia_mt2824_params(struct dwc2_hsotg *hsotg)
+{
+	struct dwc2_core_params *p = &hsotg->params;
+
+	p->otg_caps.hnp_support = false;
+	p->otg_caps.srp_support = false;
+	p->speed = DWC2_SPEED_PARAM_HIGH;
+	p->host_dma = false;
+	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
+}
+
 const struct of_device_id dwc2_of_match_table[] = {
 	{ .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
 	{ .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
@@ -347,6 +358,8 @@ const struct of_device_id dwc2_of_match_table[] = {
 	  .data = dwc2_set_stm32mp15_hsotg_params },
 	{ .compatible = "intel,socfpga-agilex-hsotg",
 	  .data = dwc2_set_socfpga_agilex_params },
+	{ .compatible = "metanoia,mt2824-usb",
+	  .data = dwc2_set_metanoia_mt2824_params },
 	{},
 };
 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);

-- 
2.56.0

[PATCH 24/25] riscv: add Metanoia MT2824 SoC and MT5824 EVB support

[Benoît Monin]

Add the device tree for the Metanoia MT2824, a dual-core Andes
AX45MP-based SoC, and for the MT5824 evaluation board.

The SoC device tree describes the CPUs and their L2 cache, the PLIC,
PLICSW and PLMT, the reset controller, the reboot controller, the
watchdog, two UARTs, the QSPI and eight SPI controllers, the DWC
MSHC MMC controller, and the USB2 controller.

The MT5824 EVB enables the watchdog, the two UARTs, the MMC
controller, the QSPI port with its SPI-NOR flash, the first three SPI
controllers, and the USB controller.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 arch/riscv/boot/dts/Makefile                |   1 +
 arch/riscv/boot/dts/metanoia/Makefile       |   2 +
 arch/riscv/boot/dts/metanoia/mt2824.dtsi    | 330 ++++++++++++++++++++++++++++
 arch/riscv/boot/dts/metanoia/mt5824-evb.dts |  81 +++++++
 4 files changed, 414 insertions(+)

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 69d8751fb17c..8e1e987ea089 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -4,6 +4,7 @@ subdir-y += andes
 subdir-y += anlogic
 subdir-y += canaan
 subdir-y += eswin
+subdir-y += metanoia
 subdir-y += microchip
 subdir-y += renesas
 subdir-y += sifive
diff --git a/arch/riscv/boot/dts/metanoia/Makefile b/arch/riscv/boot/dts/metanoia/Makefile
new file mode 100644
index 000000000000..7a685798d5a4
--- /dev/null
+++ b/arch/riscv/boot/dts/metanoia/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_METANOIA) += mt5824-evb.dtb
diff --git a/arch/riscv/boot/dts/metanoia/mt2824.dtsi b/arch/riscv/boot/dts/metanoia/mt2824.dtsi
new file mode 100644
index 000000000000..5f73c6d3760b
--- /dev/null
+++ b/arch/riscv/boot/dts/metanoia/mt2824.dtsi
@@ -0,0 +1,330 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2026 Metanoia Communications Inc.. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	#address-cells = <0x02>;
+	#size-cells = <0x02>;
+	compatible = "metanoia,mt2824";
+
+	cpus: cpus {
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		timebase-frequency = <20000000>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			reg = <0x00>;
+			compatible = "andestech,ax45mp", "riscv";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "zicntr", "zicsr", "zifencei",
+					       "zihpm", "xandespmu";
+			mmu-type = "riscv,sv39";
+			clock-frequency = <900000000>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <0x100>;
+			i-cache-line-size = <0x40>;
+			i-cache-block-size = <0x40>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <0x80>;
+			d-cache-line-size = <0x40>;
+			d-cache-block-size = <0x40>;
+			next-level-cache = <&l2_cache>;
+
+			cpu0intc: interrupt-controller {
+				#interrupt-cells = <0x01>;
+				interrupt-controller;
+				compatible = "andestech,cpu-intc", "riscv,cpu-intc";
+			};
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			reg = <0x01>;
+			compatible = "andestech,ax45mp", "riscv";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "zicntr", "zicsr", "zifencei",
+					       "zihpm", "xandespmu";
+			mmu-type = "riscv,sv39";
+			clock-frequency = <900000000>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <0x100>;
+			i-cache-line-size = <0x40>;
+			i-cache-block-size = <0x40>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <0x80>;
+			d-cache-line-size = <0x40>;
+			d-cache-block-size = <0x40>;
+			next-level-cache = <&l2_cache>;
+
+			cpu1intc: interrupt-controller {
+				#interrupt-cells = <0x01>;
+				interrupt-controller;
+				compatible = "andestech,cpu-intc", "riscv,cpu-intc";
+			};
+		};
+	};
+
+	clocks {
+		ext_clk: ext-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <20000000>;
+			clock-output-names = "ext-clk";
+		};
+
+		pclk_div4: platform-clock-div4 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <225000000>;
+			clock-output-names = "platform-clock-div4";
+		};
+
+		pll_soc_out3: pll-soc-out3 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <180000000>;
+			clock-output-names = "pll-soc-out3";
+		};
+
+		usb_otg_ahb_clk: clock-usb-otg-ahb {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <60000000>;
+			clock-output-names = "otg";
+		};
+	};
+
+	soc: soc {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		compatible = "simple-bus";
+		interrupt-parent = <&plic>;
+		ranges;
+
+		usb0: usb@4000000 {
+			compatible = "metanoia,mt2824-usb", "snps,dwc2";
+			reg = <0x0 0x04000000 0x0 0x100000>;
+			interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&usb_otg_ahb_clk>;
+			clock-names = "otg";
+			dr_mode = "host";
+			resets = <&rst 19>, <&rst 20>;
+			reset-names = "dwc2", "dwc2-ecc";
+			phys = <&usb2phy>;
+			phy-names = "usb2-phy";
+			hnp-disable;
+			srp-disable;
+			disable-over-current;
+			status = "disabled";
+		};
+
+		mmcsd: mmc@4100000 {
+			compatible = "metanoia,mt2824-dwcmshc";
+			clocks = <&pll_soc_out3>;
+			clock-names = "core";
+			reg = <0x0 0x04100000 0x0 0x00100000>;
+			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		l2_cache: cache-controller@a000000 {
+			compatible = "metanoia,mt2824-ax45mp-cache",
+				     "andestech,ax45mp-cache", "cache";
+			reg = <0x0 0x0a000000 0x0 0x40000>;
+			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+			cache-line-size = <64>;
+			cache-level = <2>;
+			cache-sets = <1024>;
+			cache-size = <0x40000>;
+			cache-unified;
+		};
+
+		plic: interrupt-controller@c000000 {
+			compatible = "metanoia,mt2824-plic", "andestech,nceplic100";
+			reg = <0x0 0x0c000000 0x0 0x400000>;
+			interrupts-extended = <&cpu0intc 0x0b>, <&cpu0intc 0x09>,
+					      <&cpu1intc 0x0b>, <&cpu1intc 0x09>;
+			interrupt-controller;
+			#address-cells = <0x00>;
+			#interrupt-cells = <0x02>;
+			riscv,ndev = <0x47>;
+		};
+
+		plmt: timer@c400000 {
+			compatible = "metanoia,mt2824-plmt", "andestech,plmt0";
+			reg = <0x0 0x0c400000 0x0 0x00400000>;
+			interrupts-extended = <&cpu0intc 0x07>,
+					      <&cpu1intc 0x07>;
+		};
+
+		plicsw: interrupt-controller@c800000 {
+			compatible = "metanoia,mt2824-plicsw", "andestech,plicsw";
+			reg = <0x0 0x0c800000 0x0 0x400000>;
+			interrupts-extended = <&cpu0intc 0x03>,
+					      <&cpu1intc 0x03>;
+		};
+
+		reboot: reboot@10000004 {
+			compatible = "metanoia,mt2824-reboot";
+			reg = <0x0 0x10000004 0x0 0x08>;
+		};
+
+		rst: reset-controller@1000000c {
+			#reset-cells = <1>;
+			compatible = "metanoia,mt2824-reset";
+			reg = <0x0 0x1000000c 0x0 0x04>;
+		};
+
+		watchdog: watchdog@10090000 {
+			compatible = "metanoia,mt2824-wdt", "andestech,ae350-wdt";
+			reg = <0x0 0x10090000 0x0 0x10000>;
+			clocks = <&ext_clk>;
+			andestech,clock-source = <0>;
+			timeout-sec = <10>;
+			status = "disabled";
+		};
+
+		serial0: serial@100e0000 {
+			compatible = "ns16550a";
+			reg = <0x0 0x100e0000 0x0 0x1000>;
+			interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pclk_div4>;
+			current-speed = <115200>;
+			reg-shift = <0x02>;
+			reg-offset = <0x20>;
+			reg-io-width = <0x04>;
+			no-loopback-test;
+			status = "disabled";
+		};
+
+		serial1: serial@100f0000 {
+			compatible = "ns16550a";
+			reg = <0x0 0x100f0000 0x0 0x1000>;
+			interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pclk_div4>;
+			current-speed = <115200>;
+			reg-shift = <0x02>;
+			reg-offset = <0x20>;
+			reg-io-width = <0x04>;
+			no-loopback-test;
+			status = "disabled";
+		};
+
+		qspi: spi@10120000 {
+			compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
+			reg = <0x0 0x10120000 0x0 0x10000>;
+			interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			num-cs = <0x01>;
+			clocks = <&pll_soc_out3>;
+			status = "disabled";
+		};
+
+		spi0: spi@10130000 {
+			compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
+			reg = <0x0 0x10130000 0x0 0x10000>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			num-cs = <0x01>;
+			clocks = <&pll_soc_out3>;
+			status = "disabled";
+		};
+
+		spi1: spi@10140000 {
+			compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
+			reg = <0x0 0x10140000 0x0 0x10000>;
+			interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			num-cs = <0x01>;
+			clocks = <&pll_soc_out3>;
+			status = "disabled";
+		};
+
+		spi2: spi@10150000 {
+			compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
+			reg = <0x0 0x10150000 0x0 0x10000>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			num-cs = <0x01>;
+			clocks = <&pll_soc_out3>;
+			status = "disabled";
+		};
+
+		spi3: spi@10160000 {
+			compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
+			reg = <0x0 0x10160000 0x0 0x10000>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			num-cs = <0x01>;
+			clocks = <&pll_soc_out3>;
+			status = "disabled";
+		};
+
+		spi4: spi@10170000 {
+			compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
+			reg = <0x0 0x10170000 0x0 0x10000>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			num-cs = <0x01>;
+			clocks = <&pll_soc_out3>;
+			status = "disabled";
+		};
+
+		spi5: spi@10180000 {
+			compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
+			reg = <0x0 0x10180000 0x0 0x10000>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			num-cs = <0x01>;
+			clocks = <&pll_soc_out3>;
+			status = "disabled";
+		};
+
+		spi6: spi@10190000 {
+			compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
+			reg = <0x0 0x10190000 0x0 0x10000>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			num-cs = <0x01>;
+			clocks = <&pll_soc_out3>;
+			status = "disabled";
+		};
+
+		spi7: spi@101a0000 {
+			compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
+			reg = <0x0 0x101a0000 0x0 0x10000>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			num-cs = <0x01>;
+			clocks = <&pll_soc_out3>;
+			status = "disabled";
+		};
+	};
+
+	usb2phy: usb2-phy {
+		compatible = "metanoia,mt2824-usb2-phy";
+		#phy-cells = <0>;
+		resets = <&rst 18>;
+		reset-names = "usb2-phy";
+	};
+
+	reserved-memory {
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		ranges;
+
+		/* for the DSPs, configured as non-cacheable in openSBI */
+		rsc_table: rsc-table@81000000 {
+			reg = <0x0 0x81000000 0x0 0x10000>;
+			no-map;
+		};
+	};
+};
diff --git a/arch/riscv/boot/dts/metanoia/mt5824-evb.dts b/arch/riscv/boot/dts/metanoia/mt5824-evb.dts
new file mode 100644
index 000000000000..d0e8eb0a49a4
--- /dev/null
+++ b/arch/riscv/boot/dts/metanoia/mt5824-evb.dts
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2026 Metanoia Communications Inc.. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "mt2824.dtsi"
+
+/ {
+	model = "Metanoia MT5824 EVB";
+	compatible = "metanoia,mt5824-evb", "metanoia,mt2824";
+
+	aliases {
+		uart0 = &serial0;
+		uart1 = &serial1;
+		spi0 = &spi0;
+		spi1 = &spi1;
+		spi2 = &spi2;
+	};
+
+	chosen {
+		stdout-path = "uart0:115200n8";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x80000000>,
+		      <0x1 0x00000000 0x0 0x80000000>;
+	};
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&mmcsd {
+	bus-width = <8>;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	no-sdio;
+	disable-wp;
+	cap-mmc-hw-reset;
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&serial0 {
+	status = "okay";
+};
+
+&serial1 {
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		spi-rx-bus-width = <0x4>;
+		spi-tx-bus-width = <0x4>;
+		spi-max-frequency = <100000000>;
+		reg = <0x0>;
+	};
+};
+
+&spi0 {
+	status = "okay";
+};
+
+&spi1 {
+	status = "okay";
+};
+
+&spi2 {
+	status = "okay";
+};

-- 
2.56.0

[PATCH 25/25] MAINTAINERS: add RISC-V Metanoia SoC support

[Benoît Monin]

Add a maintainer entry for the Metanoia MT2824 SoC, covering the
SoC-specific DT bindings, the SoC and the evaluation board device trees,
and the phy driver.

Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 MAINTAINERS | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 93abbb315065..310544f96204 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -24072,6 +24072,17 @@ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux.git
 F:	Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
 F:	drivers/iommu/riscv/
 
+RISC-V METANOIA SoC SUPPORT
+M:	Jun Chang <jun.chang@metanoia-comm.com>
+L:	linux-riscv@lists.infradead.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/phy/metanoia,usb2-phy.yaml
+F:	Documentation/devicetree/bindings/power/reset/metanoia,reboot.yaml
+F:	Documentation/devicetree/bindings/reset/metanoia,reset.yaml
+F:	Documentation/devicetree/bindings/riscv/metanoia.yaml
+F:	arch/riscv/boot/dts/metanoia/
+F:	drivers/phy/metanoia/
+
 RISC-V MICROCHIP SUPPORT
 M:	Conor Dooley <conor.dooley@microchip.com>
 R:	Valentina Fernandez <valentina.fernandezalanis@microchip.com>

-- 
2.56.0

Re: [PATCH 22/25] phy: metanoia: add USB2 PHY driver

[Philipp Zabel]

On Fr, 2026-11-06 at 10:30 +0100, Benoît Monin wrote:
> Add a minimal reset-only PHY provider for the Metanoia MT2824 USB2 PHY.
> It deasserts the PHY reset required by the DWC2 USB controller on init
> and asserts it again on exit.
> 
> Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
> ---
>  drivers/phy/Kconfig             |  1 +
>  drivers/phy/Makefile            |  1 +
>  drivers/phy/metanoia/Kconfig    | 16 ++++++++
>  drivers/phy/metanoia/Makefile   |  3 ++
>  drivers/phy/metanoia/phy-usb2.c | 88 +++++++++++++++++++++++++++++++++++++++++
>  5 files changed, 109 insertions(+)
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 105fbe408aa2..73ef61f1f53d 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -184,6 +184,7 @@ source "drivers/phy/intel/Kconfig"
>  source "drivers/phy/lantiq/Kconfig"
>  source "drivers/phy/marvell/Kconfig"
>  source "drivers/phy/mediatek/Kconfig"
> +source "drivers/phy/metanoia/Kconfig"
>  source "drivers/phy/microchip/Kconfig"
>  source "drivers/phy/motorola/Kconfig"
>  source "drivers/phy/mscc/Kconfig"
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index c6dd02003bbe..57991b50978c 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -36,6 +36,7 @@ obj-$(CONFIG_GENERIC_PHY)		+= allwinner/	\
>  					   lantiq/	\
>  					   marvell/	\
>  					   mediatek/	\
> +					   metanoia/	\
>  					   microchip/	\
>  					   motorola/	\
>  					   mscc/	\
> diff --git a/drivers/phy/metanoia/Kconfig b/drivers/phy/metanoia/Kconfig
> new file mode 100644
> index 000000000000..b8a49085bb95
> --- /dev/null
> +++ b/drivers/phy/metanoia/Kconfig
> @@ -0,0 +1,16 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +#
> +# Phy drivers for Metanoia platforms
> +#
> +
> +config PHY_METANOIA_USB2
> +	tristate "Metanoia USB2 PHY reset support"
> +	depends on OF && (ARCH_METANOIA || COMPILE_TEST)
> +	depends on RESET_CONTROLLER

No, it doesn't. This is only required for reset controller drivers.
The reset control API is stubbed out when RESET_CONTROLLER is not set.


regards
Philipp

Re: [PATCH 24/25] riscv: add Metanoia MT2824 SoC and MT5824 EVB support

[Philipp Zabel]

On Fr, 2026-11-06 at 10:30 +0100, Benoît Monin wrote:
> Add the device tree for the Metanoia MT2824, a dual-core Andes
> AX45MP-based SoC, and for the MT5824 evaluation board.
> 
> The SoC device tree describes the CPUs and their L2 cache, the PLIC,
> PLICSW and PLMT, the reset controller, the reboot controller, the
> watchdog, two UARTs, the QSPI and eight SPI controllers, the DWC
> MSHC MMC controller, and the USB2 controller.
> 
> The MT5824 EVB enables the watchdog, the two UARTs, the MMC
> controller, the QSPI port with its SPI-NOR flash, the first three SPI
> controllers, and the USB controller.
> 
> Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
> ---
>  arch/riscv/boot/dts/Makefile                |   1 +
>  arch/riscv/boot/dts/metanoia/Makefile       |   2 +
>  arch/riscv/boot/dts/metanoia/mt2824.dtsi    | 330 ++++++++++++++++++++++++++++
>  arch/riscv/boot/dts/metanoia/mt5824-evb.dts |  81 +++++++
>  4 files changed, 414 insertions(+)
> 
[...]
> diff --git a/arch/riscv/boot/dts/metanoia/mt2824.dtsi b/arch/riscv/boot/dts/metanoia/mt2824.dtsi
> new file mode 100644
> index 000000000000..5f73c6d3760b
> --- /dev/null
> +++ b/arch/riscv/boot/dts/metanoia/mt2824.dtsi
> @@ -0,0 +1,330 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2026 Metanoia Communications Inc.. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
[...]
> +	soc: soc {
[...]
> +
> +		reboot: reboot@10000004 {
> +			compatible = "metanoia,mt2824-reboot";
> +			reg = <0x0 0x10000004 0x0 0x08>;
> +		};
> +
> +		rst: reset-controller@1000000c {
> +			#reset-cells = <1>;
> +			compatible = "metanoia,mt2824-reset";
> +			reg = <0x0 0x1000000c 0x0 0x04>;
> +		};

This looks unusual. Are you sure these are not both part of a single
device @10000000 ?

regards
Philipp 

Re: [PATCH 11/25] dt-bindings: spi: andestech,ae350-spi: make DMA and interrupts optional

[Mark Brown]

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On Fri, Nov 06, 2026 at 10:30:08AM +0100, Benoît Monin wrote:
> The ATCSPI200 controller can be used in PIO mode, without DMA, and PIO
> transfers can optionally use the controller's interrupt. Make dmas,
> dma-names and interrupts optional, and require dma-names if dmas is
> specified.

Please submit patches using subject lines reflecting the style for the
subsystem, this makes it easier for people to identify relevant patches.
Look at what existing commits in the area you're changing are doing and
make sure your subject lines visually resemble what they're doing.
There's no need to resubmit to fix this alone.

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Re: [PATCH 00/25] riscv: add support for the Metanoia MT2824 SoC and MT5824 EVB

[Mark Brown]

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On Fri, Nov 06, 2026 at 10:29:57AM +0100, Benoît Monin wrote:

> The series is organised as:

> - patches 1-14 add the device tree bindings, the Metanoia vendor prefix,
>   the RISC-V board schema and the SoC block compatibles
> - patch 15 adds ARCH_METANOIA and selects the AX45MP errata
> - patches 16-23 add the reset, SPI, watchdog, MMC, PHY and USB changes
>   needed to build and probe on this SoC
> - patch 24 adds the MT2824 SoC and MT5824 EVB device trees
> - patch 25 adds the MAINTAINERS entry

This sort of thing tends to work better if you submit the patches for
subsystems as separate serieses, it avoids enormous CC lists and keeps
the individual serieses a managable size.

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Re: [PATCH 01/25] dt-bindings: vendor-prefixes: add Metanoia Communications

[Krzysztof Kozlowski]

On 06/11/2026 10:29, Benoît Monin wrote:
> Add the vendor prefix for Metanoia Communications Inc., a fabless
> semiconductor company specializing in wireline and 5G radio access
> networking chips.
> 
> Link: https://metanoia-comm.com/about-us/company-overview/
> 
> Originally-by: Jun Chang <jun.chang@metanoia-comm.com>

We do not have such tag (because we are not TIP). Drop everywhere,
except for subsystems which explicitly accept it.

Best regards,
Krzysztof

Re: [PATCH 03/25] dt-bindings: reset: add Metanoia MT2824

[Krzysztof Kozlowski]

On 06/11/2026 10:30, Benoît Monin wrote:
> +  - compatible
> +  - reg
> +  - "#reset-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    rst: rst-controller@1000000c {

Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
If you cannot find a name matching your device, please check in kernel
sources for similar cases or you can grow the spec (via pull request to
DT spec repo).

Also drop unused label.

> +        compatible = "metanoia,mt2824-reset";
> +        reg = <0x1000000c 0x4>;

I don't think one word of registers is a device. You split one device
into several fake subparts, that's not correct.


Best regards,
Krzysztof

Re: [PATCH 24/25] riscv: add Metanoia MT2824 SoC and MT5824 EVB support

[Krzysztof Kozlowski]

On 06/11/2026 10:30, Benoît Monin wrote:
> Add the device tree for the Metanoia MT2824, a dual-core Andes
> AX45MP-based SoC, and for the MT5824 evaluation board.
> 
> The SoC device tree describes the CPUs and their L2 cache, the PLIC,
> PLICSW and PLMT, the reset controller, the reboot controller, the
> watchdog, two UARTs, the QSPI and eight SPI controllers, the DWC
> MSHC MMC controller, and the USB2 controller.
> 
> The MT5824 EVB enables the watchdog, the two UARTs, the MMC
> controller, the QSPI port with its SPI-NOR flash, the first three SPI
> controllers, and the USB controller.
> 
> Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
> ---
>  arch/riscv/boot/dts/Makefile                |   1 +
>  arch/riscv/boot/dts/metanoia/Makefile       |   2 +
>  arch/riscv/boot/dts/metanoia/mt2824.dtsi    | 330 ++++++++++++++++++++++++++++
>  arch/riscv/boot/dts/metanoia/mt5824-evb.dts |  81 +++++++
>  4 files changed, 414 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index 69d8751fb17c..8e1e987ea089 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -4,6 +4,7 @@ subdir-y += andes
>  subdir-y += anlogic
>  subdir-y += canaan
>  subdir-y += eswin
> +subdir-y += metanoia
>  subdir-y += microchip
>  subdir-y += renesas
>  subdir-y += sifive
> diff --git a/arch/riscv/boot/dts/metanoia/Makefile b/arch/riscv/boot/dts/metanoia/Makefile
> new file mode 100644
> index 000000000000..7a685798d5a4
> --- /dev/null
> +++ b/arch/riscv/boot/dts/metanoia/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_METANOIA) += mt5824-evb.dtb
> diff --git a/arch/riscv/boot/dts/metanoia/mt2824.dtsi b/arch/riscv/boot/dts/metanoia/mt2824.dtsi
> new file mode 100644
> index 000000000000..5f73c6d3760b
> --- /dev/null
> +++ b/arch/riscv/boot/dts/metanoia/mt2824.dtsi
> @@ -0,0 +1,330 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2026 Metanoia Communications Inc.. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +	#address-cells = <0x02>;
> +	#size-cells = <0x02>;
> +	compatible = "metanoia,mt2824";
> +
> +	cpus: cpus {
> +		#address-cells = <0x01>;
> +		#size-cells = <0x00>;
> +		timebase-frequency = <20000000>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			reg = <0x00>;
> +			compatible = "andestech,ax45mp", "riscv";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> +					       "zicntr", "zicsr", "zifencei",
> +					       "zihpm", "xandespmu";
> +			mmu-type = "riscv,sv39";
> +			clock-frequency = <900000000>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <0x100>;
> +			i-cache-line-size = <0x40>;
> +			i-cache-block-size = <0x40>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <0x80>;
> +			d-cache-line-size = <0x40>;
> +			d-cache-block-size = <0x40>;
> +			next-level-cache = <&l2_cache>;
> +
> +			cpu0intc: interrupt-controller {
> +				#interrupt-cells = <0x01>;
> +				interrupt-controller;
> +				compatible = "andestech,cpu-intc", "riscv,cpu-intc";
> +			};
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			reg = <0x01>;
> +			compatible = "andestech,ax45mp", "riscv";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> +					       "zicntr", "zicsr", "zifencei",
> +					       "zihpm", "xandespmu";
> +			mmu-type = "riscv,sv39";
> +			clock-frequency = <900000000>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <0x100>;
> +			i-cache-line-size = <0x40>;
> +			i-cache-block-size = <0x40>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <0x80>;
> +			d-cache-line-size = <0x40>;
> +			d-cache-block-size = <0x40>;
> +			next-level-cache = <&l2_cache>;
> +
> +			cpu1intc: interrupt-controller {
> +				#interrupt-cells = <0x01>;
> +				interrupt-controller;
> +				compatible = "andestech,cpu-intc", "riscv,cpu-intc";
> +			};
> +		};
> +	};
> +
> +	clocks {
> +		ext_clk: ext-clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <20000000>;
> +			clock-output-names = "ext-clk";
> +		};
> +
> +		pclk_div4: platform-clock-div4 {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <225000000>;
> +			clock-output-names = "platform-clock-div4";
> +		};
> +
> +		pll_soc_out3: pll-soc-out3 {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <180000000>;
> +			clock-output-names = "pll-soc-out3";
> +		};
> +
> +		usb_otg_ahb_clk: clock-usb-otg-ahb {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <60000000>;
> +			clock-output-names = "otg";
> +		};
> +	};
> +
> +	soc: soc {
> +		#address-cells = <0x02>;
> +		#size-cells = <0x02>;
> +		compatible = "simple-bus";
> +		interrupt-parent = <&plic>;
> +		ranges;
> +
> +		usb0: usb@4000000 {
> +			compatible = "metanoia,mt2824-usb", "snps,dwc2";
> +			reg = <0x0 0x04000000 0x0 0x100000>;
> +			interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&usb_otg_ahb_clk>;
> +			clock-names = "otg";
> +			dr_mode = "host";
> +			resets = <&rst 19>, <&rst 20>;
> +			reset-names = "dwc2", "dwc2-ecc";
> +			phys = <&usb2phy>;
> +			phy-names = "usb2-phy";
> +			hnp-disable;
> +			srp-disable;
> +			disable-over-current;
> +			status = "disabled";
> +		};
> +
> +		mmcsd: mmc@4100000 {
> +			compatible = "metanoia,mt2824-dwcmshc";
> +			clocks = <&pll_soc_out3>;
> +			clock-names = "core";
> +			reg = <0x0 0x04100000 0x0 0x00100000>;

Please follow coding style and dt-checkstyle.

Also 0x00100000 is 0x100000

Anywya, look at size of address space. 0x100000, right?

...

> +		reboot: reboot@10000004 {
> +			compatible = "metanoia,mt2824-reboot";
> +			reg = <0x0 0x10000004 0x0 0x08>;

Now look here - 0x8

> +		};
> +
> +		rst: reset-controller@1000000c {
> +			#reset-cells = <1>;

Random coding style.

> +			compatible = "metanoia,mt2824-reset";
> +			reg = <0x0 0x1000000c 0x0 0x04>;

and 0x4.

Do you see the problem?

Why do you pad some numbers?

> +		};
> +
> +		watchdog: watchdog@10090000 {
> +			compatible = "metanoia,mt2824-wdt", "andestech,ae350-wdt";
> +			reg = <0x0 0x10090000 0x0 0x10000>;
> +			clocks = <&ext_clk>;
> +			andestech,clock-source = <0>;
> +			timeout-sec = <10>;
> +			status = "disabled";

Why? It's always there, no?


> +
> +	usb2phy: usb2-phy {

Follow DTS coding style.


Best regards,
Krzysztof

Re: [PATCH 25/25] MAINTAINERS: add RISC-V Metanoia SoC support

[Krzysztof Kozlowski]

On 06/11/2026 10:30, Benoît Monin wrote:
> Add a maintainer entry for the Metanoia MT2824 SoC, covering the
> SoC-specific DT bindings, the SoC and the evaluation board device trees,
> and the phy driver.
> 
> Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
> ---
>  MAINTAINERS | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 93abbb315065..310544f96204 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -24072,6 +24072,17 @@ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux.git
>  F:	Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
>  F:	drivers/iommu/riscv/
>  
> +RISC-V METANOIA SoC SUPPORT
> +M:	Jun Chang <jun.chang@metanoia-comm.com>

So Jun will handle the patches? Can we get an Ack for this?


Best regards,
Krzysztof

Re: [PATCH 04/25] dt-bindings: power: reset: add Metanoia MT2824 reboot

[Krzysztof Kozlowski]

On 06/11/2026 10:30, Benoît Monin wrote:
> Document the Metanoia MT2824 reboot register, which the firmware writes
> in machine mode to perform a warm system reboot. OpenSBI has a system
> reset driver for it.
> 
> Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
> ---
>  .../bindings/power/reset/metanoia,reboot.yaml      | 34 ++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/power/reset/metanoia,reboot.yaml b/Documentation/devicetree/bindings/power/reset/metanoia,reboot.yaml
> new file mode 100644
> index 000000000000..2670fe7ab93f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/reset/metanoia,reboot.yaml
> @@ -0,0 +1,34 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/power/reset/metanoia,reboot.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Metanoia MT2824 Reboot Controller
> +
> +maintainers:
> +  - Jun Chang <jun.chang@metanoia-comm.com>
> +
> +description:
> +  The Metanoia MT2824 reboot controller provides a system warm reboot through
> +  a memory-mapped register. It is used by the firmware in machine mode.
> +
> +properties:
> +  compatible:
> +    const: metanoia,mt2824-reboot
> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    reboot: reboot@10000004 {
> +      compatible = "metanoia,mt2824-reboot";
> +      reg = <0x10000004 0x8>;

Two words is also not a device, especially that rest of your devices are
at aligned to 0x10000.


Best regards,
Krzysztof

Re: [PATCH 01/25] dt-bindings: vendor-prefixes: add Metanoia Communications

[Mark Brown]

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On Fri, Nov 06, 2026 at 12:17:36PM +0100, Krzysztof Kozlowski wrote:
> On 06/11/2026 10:29, Benoît Monin wrote:

> > Originally-by: Jun Chang <jun.chang@metanoia-comm.com>

> We do not have such tag (because we are not TIP). Drop everywhere,
> except for subsystems which explicitly accept it.

You might be thinking of Co-authored-by.

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Re: [PATCH 11/25] dt-bindings: spi: andestech,ae350-spi: make DMA and interrupts optional

[Krzysztof Kozlowski]

On Fri, Nov 06, 2026 at 10:30:08AM +0100, Benoît Monin wrote:
> The ATCSPI200 controller can be used in PIO mode, without DMA, and PIO

Maybe the ae350-spi cannot and only your variant can?

> transfers can optionally use the controller's interrupt. Make dmas,
> dma-names and interrupts optional, and require dma-names if dmas is
> specified.
> 
> Originally-by: Jun Chang <jun.chang@metanoia-comm.com>

Please drop, as mentioned in earlier message.

Best regards,
Krzysztof

Re: [PATCH 01/25] dt-bindings: vendor-prefixes: add Metanoia Communications

[Krzysztof Kozlowski]

On 06/11/2026 12:39, Mark Brown wrote:
> On Fri, Nov 06, 2026 at 12:17:36PM +0100, Krzysztof Kozlowski wrote:
>> On 06/11/2026 10:29, Benoît Monin wrote:
> 
>>> Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
> 
>> We do not have such tag (because we are not TIP). Drop everywhere,
>> except for subsystems which explicitly accept it.
> 
> You might be thinking of Co-authored-by.

Which would go with Signed-off-by then.

Best regards,
Krzysztof

Re: [PATCH 23/25] usb: dwc2: add support for Metanoia MT2824

[Krzysztof Kozlowski]

On Fri, Nov 06, 2026 at 10:30:20AM +0100, Benoît Monin wrote:
> Add core parameters for the Metanoia MT2824 DWC2 controller: high-speed
> UTMI PHY, no host DMA, and no OTG HNP/SRP support.
> 
> Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
> ---
>  drivers/usb/dwc2/params.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
> index 091bfcfef753..d6a6a581d021 100644
> --- a/drivers/usb/dwc2/params.c
> +++ b/drivers/usb/dwc2/params.c
> @@ -303,6 +303,17 @@ static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
>  	p->hird_threshold_en = false;
>  }
>  
> +static void dwc2_set_metanoia_mt2824_params(struct dwc2_hsotg *hsotg)
> +{
> +	struct dwc2_core_params *p = &hsotg->params;
> +
> +	p->otg_caps.hnp_support = false;
> +	p->otg_caps.srp_support = false;
> +	p->speed = DWC2_SPEED_PARAM_HIGH;
> +	p->host_dma = false;
> +	p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
> +}
> +
>  const struct of_device_id dwc2_of_match_table[] = {
>  	{ .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
>  	{ .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
> @@ -347,6 +358,8 @@ const struct of_device_id dwc2_of_match_table[] = {
>  	  .data = dwc2_set_stm32mp15_hsotg_params },
>  	{ .compatible = "intel,socfpga-agilex-hsotg",
>  	  .data = dwc2_set_socfpga_agilex_params },
> +	{ .compatible = "metanoia,mt2824-usb",

Please organize the patch documenting the compatible (DT bindings)
before the patch using that compatible.
See also: https://elixir.bootlin.com/linux/v6.14-rc6/source/Documentation/devicetree/bindings/submitting-patches.rst#L46


Best regards,
Krzysztof

Re: [PATCH 23/25] usb: dwc2: add support for Metanoia MT2824

[Krzysztof Kozlowski]

On 06/11/2026 12:52, Krzysztof Kozlowski wrote:
> On Fri, Nov 06, 2026 at 10:30:20AM +0100, Benoît Monin wrote:
>>  const struct of_device_id dwc2_of_match_table[] = {
>>  	{ .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
>>  	{ .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
>> @@ -347,6 +358,8 @@ const struct of_device_id dwc2_of_match_table[] = {
>>  	  .data = dwc2_set_stm32mp15_hsotg_params },
>>  	{ .compatible = "intel,socfpga-agilex-hsotg",
>>  	  .data = dwc2_set_socfpga_agilex_params },
>> +	{ .compatible = "metanoia,mt2824-usb",
> 
> Please organize the patch documenting the compatible (DT bindings)
> before the patch using that compatible.
> See also: https://elixir.bootlin.com/linux/v6.14-rc6/source/Documentation/devicetree/bindings/submitting-patches.rst#L46
> 

Oh, apologies, patchset is fine, wrongly ordered in mutt.

Best regards,
Krzysztof

Re: [PATCH 13/25] dt-bindings: usb: dwc2: add Metanoia MT2824

[Krzysztof Kozlowski]

On Fri, Nov 06, 2026 at 10:30:10AM +0100, Benoît Monin wrote:
> Document the metanoia,mt2824-usb compatible, which falls back to the
> generic snps,dwc2 binding, so that the DWC2 USB controller on the Metanoia
> MT2824 SoC can be described in device trees.

This is completely redundant commit msg. You repeat subject and diff, so
obvious things, while completely skipping non-obvious part - why do you
thing they are compatible.

> 
> Originally-by: Jun Chang <jun.chang@metanoia-comm.com>

Please drop (or read submitting patches if you need other tags)

> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
> ---
>  Documentation/devicetree/bindings/usb/dwc2.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml
> index 6c3a10991b8b..898c83e57843 100644
> --- a/Documentation/devicetree/bindings/usb/dwc2.yaml
> +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
> @@ -55,6 +55,7 @@ properties:
>                - amlogic,meson-g12a-usb
>                - amlogic,meson-a1-usb
>                - intel,socfpga-agilex-hsotg
> +              - metanoia,mt2824-usb
>            - const: snps,dwc2

Is it then compatible with DWC2? Your driver code suggests not.

>        - const: amcc,dwc-otg
>        - const: apm,apm82181-dwc-otg
> 
> -- 
> 2.56.0
> 

Re: [PATCH 25/25] MAINTAINERS: add RISC-V Metanoia SoC support

[Conor Dooley]

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On Fri, Nov 06, 2026 at 12:22:15PM +0100, Krzysztof Kozlowski wrote:
> On 06/11/2026 10:30, Benoît Monin wrote:
> > Add a maintainer entry for the Metanoia MT2824 SoC, covering the
> > SoC-specific DT bindings, the SoC and the evaluation board device trees,
> > and the phy driver.
> > 
> > Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
> > Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
> > ---
> >  MAINTAINERS | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> > 
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 93abbb315065..310544f96204 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -24072,6 +24072,17 @@ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux.git
> >  F:	Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
> >  F:	drivers/iommu/riscv/
> >  
> > +RISC-V METANOIA SoC SUPPORT
> > +M:	Jun Chang <jun.chang@metanoia-comm.com>
> 
> So Jun will handle the patches? Can we get an Ack for this?

There's no tree listed, so probably Jun is not handling any patches...

I /could/ apply patches for this platform alongside the other one that I
manage, but I don't really want to and someone that actually cares for
this platform should be the one applying patches for it.

Benoít/Jun, please see Documentation/process/maintainer-soc.rst !

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Re: [PATCH 24/25] riscv: add Metanoia MT2824 SoC and MT5824 EVB support

[Conor Dooley]

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On Fri, Nov 06, 2026 at 10:30:21AM +0100, Benoît Monin wrote:
> Add the device tree for the Metanoia MT2824, a dual-core Andes
> AX45MP-based SoC, and for the MT5824 evaluation board.
> 
> The SoC device tree describes the CPUs and their L2 cache, the PLIC,
> PLICSW and PLMT, the reset controller, the reboot controller, the
> watchdog, two UARTs, the QSPI and eight SPI controllers, the DWC
> MSHC MMC controller, and the USB2 controller.
> 
> The MT5824 EVB enables the watchdog, the two UARTs, the MMC
> controller, the QSPI port with its SPI-NOR flash, the first three SPI
> controllers, and the USB controller.
> 
> Originally-by: Jun Chang <jun.chang@metanoia-comm.com>
> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
> ---
>  arch/riscv/boot/dts/Makefile                |   1 +
>  arch/riscv/boot/dts/metanoia/Makefile       |   2 +
>  arch/riscv/boot/dts/metanoia/mt2824.dtsi    | 330 ++++++++++++++++++++++++++++
>  arch/riscv/boot/dts/metanoia/mt5824-evb.dts |  81 +++++++
>  4 files changed, 414 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index 69d8751fb17c..8e1e987ea089 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -4,6 +4,7 @@ subdir-y += andes
>  subdir-y += anlogic
>  subdir-y += canaan
>  subdir-y += eswin
> +subdir-y += metanoia
>  subdir-y += microchip
>  subdir-y += renesas
>  subdir-y += sifive
> diff --git a/arch/riscv/boot/dts/metanoia/Makefile b/arch/riscv/boot/dts/metanoia/Makefile
> new file mode 100644
> index 000000000000..7a685798d5a4
> --- /dev/null
> +++ b/arch/riscv/boot/dts/metanoia/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_METANOIA) += mt5824-evb.dtb
> diff --git a/arch/riscv/boot/dts/metanoia/mt2824.dtsi b/arch/riscv/boot/dts/metanoia/mt2824.dtsi
> new file mode 100644
> index 000000000000..5f73c6d3760b
> --- /dev/null
> +++ b/arch/riscv/boot/dts/metanoia/mt2824.dtsi
> @@ -0,0 +1,330 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2026 Metanoia Communications Inc.. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +	#address-cells = <0x02>;
> +	#size-cells = <0x02>;
> +	compatible = "metanoia,mt2824";
> +
> +	cpus: cpus {
> +		#address-cells = <0x01>;
> +		#size-cells = <0x00>;

Non-hex here please.

> +		timebase-frequency = <20000000>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			reg = <0x00>;

0x0 etc

> +			compatible = "andestech,ax45mp", "riscv";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> +					       "zicntr", "zicsr", "zifencei",
> +					       "zihpm", "xandespmu";
> +			mmu-type = "riscv,sv39";
> +			clock-frequency = <900000000>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <0x100>;
> +			i-cache-line-size = <0x40>;
> +			i-cache-block-size = <0x40>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <0x80>;
> +			d-cache-line-size = <0x40>;
> +			d-cache-block-size = <0x40>;
> +			next-level-cache = <&l2_cache>;
> +
> +			cpu0intc: interrupt-controller {
> +				#interrupt-cells = <0x01>;
> +				interrupt-controller;
> +				compatible = "andestech,cpu-intc", "riscv,cpu-intc";
> +			};
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			reg = <0x01>;
> +			compatible = "andestech,ax45mp", "riscv";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> +					       "zicntr", "zicsr", "zifencei",
> +					       "zihpm", "xandespmu";
> +			mmu-type = "riscv,sv39";
> +			clock-frequency = <900000000>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <0x100>;
> +			i-cache-line-size = <0x40>;
> +			i-cache-block-size = <0x40>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <0x80>;
> +			d-cache-line-size = <0x40>;
> +			d-cache-block-size = <0x40>;
> +			next-level-cache = <&l2_cache>;
> +
> +			cpu1intc: interrupt-controller {
> +				#interrupt-cells = <0x01>;
> +				interrupt-controller;
> +				compatible = "andestech,cpu-intc", "riscv,cpu-intc";
> +			};
> +		};
> +	};
> +
> +	clocks {
> +		ext_clk: ext-clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <20000000>;
> +			clock-output-names = "ext-clk";
> +		};

Is the frequency here actually set by the soc, or actually by the board?
If it says "ext", I assume it's not part of the soc.

> +
> +		pclk_div4: platform-clock-div4 {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <225000000>;
> +			clock-output-names = "platform-clock-div4";
> +		};
> +
> +		pll_soc_out3: pll-soc-out3 {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <180000000>;
> +			clock-output-names = "pll-soc-out3";
> +		};
> +
> +		usb_otg_ahb_clk: clock-usb-otg-ahb {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <60000000>;
> +			clock-output-names = "otg";
> +		};

I'd much rather this not be merged until things like this are replaced
by an actual clock controller, lest it appear in u-boot etc and then
have the support break because it got swapped out for a clock
controller.

> +	};
> +
> +	soc: soc {
> +		#address-cells = <0x02>;
> +		#size-cells = <0x02>;
> +		compatible = "simple-bus";
> +		interrupt-parent = <&plic>;
> +		ranges;
> +
> +		usb0: usb@4000000 {
> +			compatible = "metanoia,mt2824-usb", "snps,dwc2";
> +			reg = <0x0 0x04000000 0x0 0x100000>;
> +			interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&usb_otg_ahb_clk>;
> +			clock-names = "otg";
> +			dr_mode = "host";
> +			resets = <&rst 19>, <&rst 20>;
> +			reset-names = "dwc2", "dwc2-ecc";
> +			phys = <&usb2phy>;
> +			phy-names = "usb2-phy";
> +			hnp-disable;
> +			srp-disable;
> +			disable-over-current;
> +			status = "disabled";
> +		};
> +
> +		mmcsd: mmc@4100000 {
> +			compatible = "metanoia,mt2824-dwcmshc";
> +			clocks = <&pll_soc_out3>;
> +			clock-names = "core";
> +			reg = <0x0 0x04100000 0x0 0x00100000>;

ordering should be compatible -> reg

> +			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +		};
> +
> +		l2_cache: cache-controller@a000000 {
> +			compatible = "metanoia,mt2824-ax45mp-cache",
> +				     "andestech,ax45mp-cache", "cache";
> +			reg = <0x0 0x0a000000 0x0 0x40000>;
> +			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
> +			cache-line-size = <64>;
> +			cache-level = <2>;
> +			cache-sets = <1024>;
> +			cache-size = <0x40000>;
> +			cache-unified;
> +		};
> +
> +		plic: interrupt-controller@c000000 {
> +			compatible = "metanoia,mt2824-plic", "andestech,nceplic100";
> +			reg = <0x0 0x0c000000 0x0 0x400000>;
> +			interrupts-extended = <&cpu0intc 0x0b>, <&cpu0intc 0x09>,
> +					      <&cpu1intc 0x0b>, <&cpu1intc 0x09>;
> +			interrupt-controller;
> +			#address-cells = <0x00>;
> +			#interrupt-cells = <0x02>;
> +			riscv,ndev = <0x47>;
> +		};
> +
> +		plmt: timer@c400000 {
> +			compatible = "metanoia,mt2824-plmt", "andestech,plmt0";
> +			reg = <0x0 0x0c400000 0x0 0x00400000>;
> +			interrupts-extended = <&cpu0intc 0x07>,
> +					      <&cpu1intc 0x07>;
> +		};
> +
> +		plicsw: interrupt-controller@c800000 {
> +			compatible = "metanoia,mt2824-plicsw", "andestech,plicsw";
> +			reg = <0x0 0x0c800000 0x0 0x400000>;
> +			interrupts-extended = <&cpu0intc 0x03>,
> +					      <&cpu1intc 0x03>;
> +		};
> +

> +		reboot: reboot@10000004 {
> +			compatible = "metanoia,mt2824-reboot";
> +			reg = <0x0 0x10000004 0x0 0x08>;
> +		};
> +
> +		rst: reset-controller@1000000c {
> +			#reset-cells = <1>;
> +			compatible = "metanoia,mt2824-reset";
> +			reg = <0x0 0x1000000c 0x0 0x04>;
> +		};

As pointed out, these are probably part of a syscon that I would imagine
also includes some clocks or other features.

By and large I think this is fine though..

Thanks,
Conor.

> +
> +		watchdog: watchdog@10090000 {
> +			compatible = "metanoia,mt2824-wdt", "andestech,ae350-wdt";
> +			reg = <0x0 0x10090000 0x0 0x10000>;
> +			clocks = <&ext_clk>;
> +			andestech,clock-source = <0>;
> +			timeout-sec = <10>;
> +			status = "disabled";
> +		};
> +
> +		serial0: serial@100e0000 {
> +			compatible = "ns16550a";
> +			reg = <0x0 0x100e0000 0x0 0x1000>;
> +			interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pclk_div4>;
> +			current-speed = <115200>;
> +			reg-shift = <0x02>;
> +			reg-offset = <0x20>;
> +			reg-io-width = <0x04>;
> +			no-loopback-test;
> +			status = "disabled";
> +		};
> +
> +		serial1: serial@100f0000 {
> +			compatible = "ns16550a";
> +			reg = <0x0 0x100f0000 0x0 0x1000>;
> +			interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pclk_div4>;
> +			current-speed = <115200>;
> +			reg-shift = <0x02>;
> +			reg-offset = <0x20>;
> +			reg-io-width = <0x04>;
> +			no-loopback-test;
> +			status = "disabled";
> +		};
> +
> +		qspi: spi@10120000 {
> +			compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
> +			reg = <0x0 0x10120000 0x0 0x10000>;
> +			interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <0x01>;
> +			#size-cells = <0x00>;
> +			num-cs = <0x01>;
> +			clocks = <&pll_soc_out3>;
> +			status = "disabled";
> +		};
> +
> +		spi0: spi@10130000 {
> +			compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
> +			reg = <0x0 0x10130000 0x0 0x10000>;
> +			#address-cells = <0x01>;
> +			#size-cells = <0x00>;
> +			num-cs = <0x01>;
> +			clocks = <&pll_soc_out3>;
> +			status = "disabled";
> +		};
> +
> +		spi1: spi@10140000 {
> +			compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
> +			reg = <0x0 0x10140000 0x0 0x10000>;
> +			interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <0x01>;
> +			#size-cells = <0x00>;
> +			num-cs = <0x01>;
> +			clocks = <&pll_soc_out3>;
> +			status = "disabled";
> +		};
> +
> +		spi2: spi@10150000 {
> +			compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
> +			reg = <0x0 0x10150000 0x0 0x10000>;
> +			#address-cells = <0x01>;
> +			#size-cells = <0x00>;
> +			num-cs = <0x01>;
> +			clocks = <&pll_soc_out3>;
> +			status = "disabled";
> +		};
> +
> +		spi3: spi@10160000 {
> +			compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
> +			reg = <0x0 0x10160000 0x0 0x10000>;
> +			#address-cells = <0x01>;
> +			#size-cells = <0x00>;
> +			num-cs = <0x01>;
> +			clocks = <&pll_soc_out3>;
> +			status = "disabled";
> +		};
> +
> +		spi4: spi@10170000 {
> +			compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
> +			reg = <0x0 0x10170000 0x0 0x10000>;
> +			#address-cells = <0x01>;
> +			#size-cells = <0x00>;
> +			num-cs = <0x01>;
> +			clocks = <&pll_soc_out3>;
> +			status = "disabled";
> +		};
> +
> +		spi5: spi@10180000 {
> +			compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
> +			reg = <0x0 0x10180000 0x0 0x10000>;
> +			#address-cells = <0x01>;
> +			#size-cells = <0x00>;
> +			num-cs = <0x01>;
> +			clocks = <&pll_soc_out3>;
> +			status = "disabled";
> +		};
> +
> +		spi6: spi@10190000 {
> +			compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
> +			reg = <0x0 0x10190000 0x0 0x10000>;
> +			#address-cells = <0x01>;
> +			#size-cells = <0x00>;
> +			num-cs = <0x01>;
> +			clocks = <&pll_soc_out3>;
> +			status = "disabled";
> +		};
> +
> +		spi7: spi@101a0000 {
> +			compatible = "metanoia,mt2824-spi", "andestech,ae350-spi";
> +			reg = <0x0 0x101a0000 0x0 0x10000>;
> +			#address-cells = <0x01>;
> +			#size-cells = <0x00>;
> +			num-cs = <0x01>;
> +			clocks = <&pll_soc_out3>;
> +			status = "disabled";
> +		};
> +	};
> +
> +	usb2phy: usb2-phy {
> +		compatible = "metanoia,mt2824-usb2-phy";
> +		#phy-cells = <0>;
> +		resets = <&rst 18>;
> +		reset-names = "usb2-phy";
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <0x2>;
> +		#size-cells = <0x2>;
> +		ranges;
> +
> +		/* for the DSPs, configured as non-cacheable in openSBI */
> +		rsc_table: rsc-table@81000000 {
> +			reg = <0x0 0x81000000 0x0 0x10000>;
> +			no-map;
> +		};
> +	};
> +};
> diff --git a/arch/riscv/boot/dts/metanoia/mt5824-evb.dts b/arch/riscv/boot/dts/metanoia/mt5824-evb.dts
> new file mode 100644
> index 000000000000..d0e8eb0a49a4
> --- /dev/null
> +++ b/arch/riscv/boot/dts/metanoia/mt5824-evb.dts
> @@ -0,0 +1,81 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2026 Metanoia Communications Inc.. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "mt2824.dtsi"
> +
> +/ {
> +	model = "Metanoia MT5824 EVB";
> +	compatible = "metanoia,mt5824-evb", "metanoia,mt2824";
> +
> +	aliases {
> +		uart0 = &serial0;
> +		uart1 = &serial1;
> +		spi0 = &spi0;
> +		spi1 = &spi1;
> +		spi2 = &spi2;
> +	};
> +
> +	chosen {
> +		stdout-path = "uart0:115200n8";
> +	};
> +
> +	memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x80000000 0x0 0x80000000>,
> +		      <0x1 0x00000000 0x0 0x80000000>;
> +	};
> +};
> +
> +&usb0 {
> +	status = "okay";
> +};
> +
> +&mmcsd {
> +	bus-width = <8>;
> +	mmc-ddr-1_8v;
> +	mmc-hs200-1_8v;
> +	mmc-hs400-1_8v;
> +	no-sdio;
> +	disable-wp;
> +	cap-mmc-hw-reset;
> +	status = "okay";
> +};
> +
> +&watchdog {
> +	status = "okay";
> +};
> +
> +&serial0 {
> +	status = "okay";
> +};
> +
> +&serial1 {
> +	status = "okay";
> +};
> +
> +&qspi {
> +	status = "okay";
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		spi-rx-bus-width = <0x4>;
> +		spi-tx-bus-width = <0x4>;
> +		spi-max-frequency = <100000000>;
> +		reg = <0x0>;
> +	};
> +};
> +
> +&spi0 {
> +	status = "okay";
> +};
> +
> +&spi1 {
> +	status = "okay";
> +};
> +
> +&spi2 {
> +	status = "okay";
> +};
> 
> -- 
> 2.56.0
> 

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Re: [PATCH 00/25] riscv: add support for the Metanoia MT2824 SoC and MT5824 EVB

[Conor Dooley]

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On Fri, Nov 06, 2026 at 10:29:57AM +0100, Benoît Monin wrote:
> Hi all,
> 
> This series adds initial upstream support for the Metanoia MT2824 SoC
> and its MT5824 evaluation board.
> 
> The MT2824 is a dual-core RISC-V SoC built on Andes AX45MP cores. It
> integrates two 8250-compatible UARTs, the Andes PLIC/PLICSW/PLMT interrupt
> and timer blocks, the AX45MP L2 cache controller, a simple reset controller
> and a system reboot controller, the ATCWDT200 watchdog, one QSPI and eight
> ATCSPI200 SPI controllers, a Synopsys DWC MSHC 2.00a eMMC/SD controller,
> and a Synopsys DWC2 USB2 host controller with a reset-only USB2 PHY.
> 
> The series is organised as:
> 
> - patches 1-14 add the device tree bindings, the Metanoia vendor prefix,
>   the RISC-V board schema and the SoC block compatibles
> - patch 15 adds ARCH_METANOIA and selects the AX45MP errata
> - patches 16-23 add the reset, SPI, watchdog, MMC, PHY and USB changes
>   needed to build and probe on this SoC
> - patch 24 adds the MT2824 SoC and MT5824 EVB device trees
> - patch 25 adds the MAINTAINERS entry
> 
> The ATCSPI200 driver gains optional interrupt support for PIO transfers:
> when the controller IRQ is wired, the FIFOs and the end of transfer
> are serviced from the handler, with a fallback to polling when no IRQ
> is available.
> 
> The DWC MSHC controller on the evaluation board is wired to either an
> SD slot or an eMMC through a board jumper that the SoC cannot read. In
> the absence of a fixed card type in the device tree, the driver probes
> the eMMC first at 1.8 V and falls back to the SD slot at 3.3 V. The
> controller also needs custom tuning and HS400 PHY DLL handling, which
> is why it has its own sdhci_ops.
> 
> The MT2824 SoC contains other controllers not yet exposed (I2C, GPIO,
> pinctrl, Ethernet, DSP, ...). This first series allows accessing the
> evaluation board via its serial console, and all its storage options
> (SPI-NOR, eMMC, SD card). The watchdog and the USB port are also
> available.
> 
> The driver changes do not depend on the DTS at build time and are gated
> on the new compatible strings. For merge ordering, the DTS depends on the
> ARCH_METANOIA Kconfig entry (patch 15) and on the binding compatibles
> being accepted. The patches can therefore go through their respective
> subsystem trees, with the Kconfig, DTS and MAINTAINERS patches going
> through the RISC-V tree once the driver and binding patches have landed.

I kinda pointed it out elsewhere, but that's not actually the path for
the Kconfig, dts and MAINTAINERS bits. They go via the soc tree, after
being applied by a metanoia specific maintainer.

> 
> The series is based on v7.4-rc1.
> 
> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
> ---
> Benoît Monin (25):
>       dt-bindings: vendor-prefixes: add Metanoia Communications
>       dt-bindings: riscv: add Metanoia SoC-based boards
>       dt-bindings: reset: add Metanoia MT2824
>       dt-bindings: power: reset: add Metanoia MT2824 reboot
>       dt-bindings: phy: add Metanoia USB2 PHY
>       dt-bindings: cache: andestech,ax45mp-cache: add MT2824 compatible
>       dt-bindings: interrupt-controller: sifive,plic-1.0.0: add Metanoia MT2824
>       dt-bindings: interrupt-controller: andestech,plicsw: add Metanoia MT2824
>       dt-bindings: timer: andestech,plmt0: add Metanoia MT2824
>       dt-bindings: mmc: snps,dwcmshc-sdhci: add Metanoia MT2824
>       dt-bindings: spi: andestech,ae350-spi: make DMA and interrupts optional
>       dt-bindings: spi: andestech,ae350-spi: add Metanoia MT2824
>       dt-bindings: usb: dwc2: add Metanoia MT2824
>       dt-bindings: watchdog: andestech,ae350-wdt: add Metanoia MT2824

Other than the tag issues in most of these, riscv and dt wise this looks
mostly fine. The reset/reboot stuff and probably missing clock support
are the only real problems.

Probably, I would split this series up into multiple smaller
submissions. spi, mmc, phy, usb, watchdog at least should be their own
mini series. clock/reset should probably be another, presumably also
with the reboot thing. What's left (interrupts, timer, cache I think)
can stay part of the dts series and probably go through the soc tree
together. For interrupts and timer, the maintainers are usually not
super responsive in terms of binding only series which is why they may
go via soc.

Cheers,
Conor.

>       riscv: add ARCH_METANOIA Kconfig entry
>       reset: simple: add Metanoia MT2824 support
>       spi: atcspi200: add optional interrupt support
>       spi: atcspi200: allow building for Metanoia SoCs
>       watchdog: atcwdt200: allow building for Metanoia SoCs
>       mmc: sdhci-of-dwcmshc: add MT2824 support
>       mmc: sdhci-of-dwcmshc: add MT2824 tuning and HS400 support
>       phy: metanoia: add USB2 PHY driver
>       usb: dwc2: add support for Metanoia MT2824
>       riscv: add Metanoia MT2824 SoC and MT5824 EVB support
>       MAINTAINERS: add RISC-V Metanoia SoC support

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