* [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support
@ 2026-10-21 16:10 Cunhao Lu via B4 Relay
2026-10-21 16:10 ` [PATCH 01/27] dt-bindings: clock: rockchip: Add RK3572 CRU Cunhao Lu via B4 Relay
` (27 more replies)
0 siblings, 28 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:10 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
This series adds initial support for the RK3572 SoC and the Forlinx
OK3572-C board. It includes the bindings, drivers, and device trees
needed to bring up a minimal system.
The RK3572 SoC has eight CPU cores: two Cortex-A73 cores and six
Cortex-A53 cores. It also integrates an Arm Mali-G310V2 MC1 GPU.
The OK3572-C board provides two Gigabit Ethernet ports, three USB3 Type-A
ports, a Type-C dual-role port, eMMC, microSD, and UART.
Testing was performed with Debian 13 minimal and Linux 7.3 on the
OK3572-C with the FET3572-C module. Shared peripheral tests were run with
the system booted from SD, while eMMC validation covered the complete
boot chain.
Passed functionality:
- SD and eMMC complete the firmware, kernel, and root filesystem
boot chain.
- UART console works at 1500000 baud.
- SD read/write and data persistence checks pass.
- All eight CPUs start; CPU frequency scaling and hotplug checks pass.
- Both Ethernet ports obtain IPv4 addresses and pass bidirectional file
transfers.
- All three Type-A ports pass USB2 and USB3 enumeration, data transfers,
and reconnect persistence checks.
- Type-C host and device modes pass in both plug orientations. Physical
reconnects correctly select the expected device, host, and device roles
in sequence.
Stability:
- Repeated cold and software reboots complete on SD and eMMC without data
integrity failures.
- A combined CPU, memory, network, SD, and USB3 stress test completes
without a crash, lockup, CPU offline event, or thermal shutdown.
- Ethernet error and drop counters do not increase during bidirectional
network tests.
Build and checks:
- The kernel, modules, and board DTB build successfully.
- The series passes checkpatch with --strict; only generic reminders about
new MAINTAINERS entries remain.
Untested hardware and paths:
- NPU
- PCIe
- GPU, video output, and audio
- CPU rates above 1.2 GHz and voltage scaling
- Other low-speed external interfaces
Some files in this series are derived from the Forlinx OK3572-C BSP
Alpha1. Thanks to Forlinx for their support.
AI assistance:
- Codex / DeepSeek V4.1 Flash were used for:
- Collecting data
- Automating tests
- Reviewing and adjusting code to follow community conventions
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
Raw dmesg from the OK3572-C boot:
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[ 0.000000] Linux version 7.3.0-bleedingedge-rk3572 (build@armbian) (aarch64-linux-gnu-gcc (Ubuntu 11.4.0-1ubuntu1~22.04.3) 11.4.0, GNU ld (GNU Binutils for Ubuntu) 2.38) #1 SMP PREEMPT Wed Oct 21 14:04:07 CST 2026
[ 0.000000] Machine model: Forlinx OK3572-C
[ 0.000000] efi: UEFI not found.
[ 0.000000] OF: reserved mem: Reserved memory: No reserved-memory node in the DT
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: PSCIv1.1 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
[ 0.000000] psci: SMC Calling Convention v1.5
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x0000000040200000-0x00000000ffffffff]
[ 0.000000] DMA32 empty
[ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000040200000-0x000000013fffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000040200000-0x000000013fffffff]
[ 0.000000] On node 0, zone DMA: 512 pages in unavailable ranges
[ 0.000000] percpu: Embedded 30 pages/cpu s82136 r8192 d32552 u122880
[ 0.000000] pcpu-alloc: s82136 r8192 d32552 u122880 alloc=30*4096
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5 [0] 6 [0] 7
[ 0.000000] CPU features: detected: ARM erratum 845719
[ 0.000000] alternatives: applying boot alternatives
[ 0.000000] Kernel command line: root=UUID=2520cc50-b3ea-430f-ba9b-552afa4b6f82 rootwait rootfstype=ext4 splash=verbose console=ttyS0,1500000 console=tty1 consoleblank=0 loglevel=1 ubootpart=48cd0da4-4dfb-4b7c-b03f-e4a0c57ddacd usb-storage.quirks=0x2537:0x1066:u,0x2537:0x1068:u cgroup_enable=cpuset cgroup_memory=1 cgroup_enable=memory
[ 0.000000] Unknown kernel command line parameters "splash=verbose ubootpart=48cd0da4-4dfb-4b7c-b03f-e4a0c57ddacd cgroup_enable=memory cgroup_memory=1", will be passed to user space.
[ 0.000000] printk: log buffer data + meta data: 131072 + 458752 = 589824 bytes
[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[ 0.000000] software IO TLB: area num 8.
[ 0.000000] software IO TLB: mapped [mem 0x00000000f7f47000-0x00000000fbf47000] (64MB)
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1048064
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
[ 0.000000] ftrace: allocating 40216 entries in 158 pages
[ 0.000000] ftrace: allocated 158 pages with 5 groups
[ 0.000000] rcu: Hierarchical RCU implementation.
[ 0.000000] rcu: RCU event tracing is enabled.
[ 0.000000] Trampoline variant of Tasks RCU enabled.
[ 0.000000] Rude variant of Tasks RCU enabled.
[ 0.000000] Tracing variant of Tasks RCU enabled.
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=8.
[ 0.000000] RCU Tasks Rude: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=8.
[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[ 0.000000] Root IRQ handler: gic_handle_irq
[ 0.000000] GIC: Using split EOI/Deactivate mode
[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
[ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 0.000000] arch_timer: cp15 timer running at 24.00MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
[ 0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
[ 0.000502] Console: colour dummy device 80x25
[ 0.000516] printk: legacy console [tty1] enabled
[ 0.000637] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
[ 0.000652] pid_max: default: 32768 minimum: 301
[ 0.000874] Yama: becoming mindful.
[ 0.001075] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[ 0.001097] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
[ 0.001450] VFS: Finished mounting rootfs on nullfs
[ 0.004025] rcu: Hierarchical SRCU implementation.
[ 0.004042] rcu: Max phase no-delay instances is 1000.
[ 0.004294] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
[ 0.004820] EFI services will not be available.
[ 0.005261] smp: Bringing up secondary CPUs ...
[ 0.006096] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[ 0.006991] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
[ 0.007847] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
[ 0.008787] CPU4: Booted secondary processor 0x0000000100 [0x410fd034]
[ 0.009715] CPU5: Booted secondary processor 0x0000000101 [0x410fd034]
[ 0.010446] CPU features: detected: Spectre-BHB
[ 0.010459] CPU features: detected: ARM erratum 858921
[ 0.010576] arch_timer: Enabling local workaround for ARM erratum 858921
[ 0.010590] arch_timer: CPU6: Trapping CNTVCT access
[ 0.010600] CPU6: Booted secondary processor 0x0000000200 [0x411fd090]
[ 0.011335] arch_timer: Enabling local workaround for ARM erratum 858921
[ 0.011346] arch_timer: CPU7: Trapping CNTVCT access
[ 0.011354] CPU7: Booted secondary processor 0x0000000201 [0x411fd090]
[ 0.011443] smp: Brought up 1 node, 8 CPUs
[ 0.011468] SMP: Total of 8 processors activated.
[ 0.011473] CPU: All CPU(s) started at EL2
[ 0.011480] CPU features: detected: 32-bit EL0 Support
[ 0.011487] CPU features: detected: CRC32 instructions
[ 0.011563] alternatives: applying system-wide alternatives
[ 0.013503] Memory: 3994400K/4192256K available (12800K kernel code, 1804K rwdata, 8020K rodata, 4800K init, 367K bss, 188600K reserved, 0K cma-reserved)
[ 0.014586] devtmpfs: initialized
[ 0.023256] posixtimers hash table entries: 4096 (order: 4, 65536 bytes, linear)
[ 0.023390] futex hash table entries: 2048 (131072 bytes on 1 NUMA nodes, total 128 KiB, linear).
[ 0.023497] 25760 pages in range for non-PLT usage
[ 0.023504] 517280 pages in range for PLT usage
[ 0.024485] DMI: not present or invalid.
[ 0.027105] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[ 0.027775] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
[ 0.027873] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
[ 0.027917] audit: initializing netlink subsys (disabled)
[ 0.028106] audit: type=2000 audit(0.024:1): state=initialized audit_enabled=0 res=1
[ 0.063844] thermal_sys: Registered thermal governor 'step_wise'
[ 0.063969] ASID allocator initialised with 65536 entries
[ 0.066221] /soc/i2c@2c040000/usb-typec@22/connector: Fixed dependency cycle(s) with /soc/usb@24000000
[ 0.066238] /soc/usb@24000000: Fixed dependency cycle(s) with /soc/i2c@2c040000/usb-typec@22/connector
[ 0.066401] /soc/interrupt-controller@2a601000: Fixed dependency cycle(s) with /soc/interrupt-controller@2a601000
[ 0.074302] rockchip-gpio 26300000.gpio: probed /pinctrl/gpio@26300000
[ 0.074859] rockchip-gpio 2b200000.gpio: probed /pinctrl/gpio@2b200000
[ 0.075467] rockchip-gpio 2b300000.gpio: probed /pinctrl/gpio@2b300000
[ 0.076065] rockchip-gpio 2b400000.gpio: probed /pinctrl/gpio@2b400000
[ 0.076577] rockchip-gpio 2b500000.gpio: probed /pinctrl/gpio@2b500000
[ 0.079569] iommu: Default domain type: Translated
[ 0.079581] iommu: DMA domain TLB invalidation policy: strict mode
[ 0.087665] SCSI subsystem initialized
[ 0.087800] usbcore: registered new interface driver usbfs
[ 0.087825] usbcore: registered new interface driver hub
[ 0.087851] usbcore: registered new device driver usb
[ 0.087962] pps_core: LinuxPPS API ver. 1 registered
[ 0.087967] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 0.087977] PTP clock support registered
[ 0.088046] scmi_core: SCMI protocol bus registered
[ 0.088816] vgaarb: loaded
[ 0.089111] clocksource: Switched to clocksource arch_sys_counter
[ 0.095252] NET: Registered PF_INET protocol family
[ 0.095435] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
[ 0.098401] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
[ 0.098444] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[ 0.098456] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
[ 0.098599] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
[ 0.099208] TCP: Hash tables configured (established 32768 bind 32768)
[ 0.099320] UDP hash table entries: 2048 (order: 5, 131072 bytes, linear)
[ 0.099566] NET: Registered PF_UNIX/PF_LOCAL protocol family
[ 0.099609] PCI: CLS 0 bytes, default 64
[ 0.099809] Unpacking initramfs...
[ 0.113777] Initialise system trusted keyrings
[ 0.114004] workingset: timestamp_bits=46 (anon: 41) max_order=20 bucket_order=0 (anon: 0)
[ 0.114534] fuse: init (API version 7.46)
[ 0.114817] NET: Registered PF_ALG protocol family
[ 0.114828] Key type asymmetric registered
[ 0.114833] Asymmetric key parser 'x509' registered
[ 0.114866] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249)
[ 0.115027] io scheduler mq-deadline registered
[ 0.115033] io scheduler kyber registered
[ 0.115065] io scheduler bfq registered
[ 0.603726] Freeing initrd memory: 13024K
[ 0.641317] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 0.642938] printk: console [ttyS0] disabled
[ 0.643204] 2c130000.serial: ttyS0 MMIO32:0x000000002c130000 (irq = 36, base_baud = 1500000) is a 16550A
[ 0.643447] printk: console [ttyS0] enabled
[ 0.649403] loop: module loaded
[ 0.650488] tun: Universal TUN/TAP device driver, 1.6
[ 0.657994] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
[ 0.658022] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
[ 0.658098] xhci-hcd xhci-hcd.0.auto: hcc params 0x0220fe64 hci version 0x110 quirks 0x0000808002000010
[ 0.658139] xhci-hcd xhci-hcd.0.auto: irq 38, io mem 0x24400000
[ 0.658251] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
[ 0.658261] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
[ 0.658273] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
[ 0.658925] hub 1-0:1.0: USB hub found
[ 0.658955] hub 1-0:1.0: 1 port detected
[ 0.659569] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[ 0.659953] hub 2-0:1.0: USB hub found
[ 0.659977] hub 2-0:1.0: 1 port detected
[ 0.660444] usbcore: registered new interface driver uas
[ 0.660501] usbcore: registered new interface driver usb-storage
[ 0.660521] usbcore: registered new device driver onboard-usb-dev
[ 0.677538] vdda_hdmi_s0: Bringing 750000uV into 837500-837500uV
[ 0.691929] pca953x 2-0023: using auto increment
[ 0.704405] dwmmc_rockchip 2a090000.mmc: IDMAC supports 32-bit address mode.
[ 0.704405] arm-scmi arm-scmi.4.auto: Using scmi_smc_transport
[ 0.704420] arm-scmi arm-scmi.4.auto: SCMI max-rx-timeout: 30ms / max-msg-size: 104bytes / max-msg: 20
[ 0.704437] dwmmc_rockchip 2a090000.mmc: Using internal DMA controller.
[ 0.704446] dwmmc_rockchip 2a090000.mmc: Version ID is 270a
[ 0.704482] dwmmc_rockchip 2a090000.mmc: DW MMC controller at irq 62,32 bit host data width,256 deep fifo
[ 0.704546] scmi_protocol scmi_dev.1: Enabled polling mode TX channel - prot_id:16
[ 0.704919] arm-scmi arm-scmi.4.auto: SCMI Notifications - Core Enabled.
[ 0.704981] arm-scmi arm-scmi.4.auto: SCMI Protocol v2.0 'rockchip:' Firmware version 0x0
[ 0.705018] arm-scmi arm-scmi.4.auto: Enabling SCMI Quirk [quirk_clock_rates_triplet_out_of_spec]
[ 0.705787] mmc0: CQHCI version 5.10
[ 0.708680] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[ 0.708975] usbcore: registered new interface driver usbhid
[ 0.708982] usbhid: USB HID core driver
[ 0.709386] NET: Registered PF_INET6 protocol family
[ 0.710254] Segment Routing with IPv6
[ 0.710294] In-situ OAM (IOAM) with IPv6
[ 0.710341] NET: Registered PF_PACKET protocol family
[ 0.710370] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
[ 0.715466] Loading compiled-in X.509 certificates
[ 0.717882] mmc_host mmc1: Bus speed = 400000Hz (req 400000Hz, actual 400000HZ div = 0)
[ 0.721073] Key type encrypted registered
[ 0.732592] mmc0: SDHCI controller on 2a010000.mmc [2a010000.mmc] using ADMA 64-bit
[ 0.737594] dwc3-generic-plat 24400000.usb: Failed to create device link (0x180) with supplier regulator-usb-hub-1v2 for /soc/usb@24400000/hub@2
[ 0.737903] rk_gmac-dwmac 29d20000.ethernet: IRQ sfty not found
[ 0.738262] rk_gmac-dwmac 29d20000.ethernet: clock input or output? (output).
[ 0.738271] rk_gmac-dwmac 29d20000.ethernet: TX delay(0x21).
[ 0.738279] rk_gmac-dwmac 29d20000.ethernet: Can not read property: rx_delay.
[ 0.738284] rk_gmac-dwmac 29d20000.ethernet: set rx_delay to 0x10
[ 0.738298] rk_gmac-dwmac 29d20000.ethernet: integrated PHY? (no).
[ 0.743326] rk_gmac-dwmac 29d20000.ethernet: init for RGMII_RXID
[ 0.743496] rk_gmac-dwmac 29d20000.ethernet: User ID: 0x50, Synopsys ID: 0x51
[ 0.743506] rk_gmac-dwmac 29d20000.ethernet: DWMAC4/5
[ 0.743513] rk_gmac-dwmac 29d20000.ethernet: DMA HW capability register supported
[ 0.743519] rk_gmac-dwmac 29d20000.ethernet: Active PHY interface: RGMII (1)
[ 0.743525] rk_gmac-dwmac 29d20000.ethernet: RX Checksum Offload Engine supported
[ 0.743530] rk_gmac-dwmac 29d20000.ethernet: TX Checksum insertion supported
[ 0.743535] rk_gmac-dwmac 29d20000.ethernet: Wake-Up On Lan supported
[ 0.743580] rk_gmac-dwmac 29d20000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[ 0.743587] rk_gmac-dwmac 29d20000.ethernet: Enabled L3L4 Flow TC (entries=2)
[ 0.743594] rk_gmac-dwmac 29d20000.ethernet: Enabled RFS Flow TC (entries=10)
[ 0.743599] rk_gmac-dwmac 29d20000.ethernet: TSO supported
[ 0.743604] rk_gmac-dwmac 29d20000.ethernet: TSO feature enabled
[ 0.743609] rk_gmac-dwmac 29d20000.ethernet: SPH feature enabled
[ 0.743614] rk_gmac-dwmac 29d20000.ethernet: Using 40/40 bits DMA host/device width
[ 0.801924] sdhci-dwcmshc 2a010000.mmc: Can't reduce the clock below 52MHz in HS200/HS400 mode
[ 0.802190] mmc0: Command Queue Engine enabled
[ 0.802216] mmc0: new HS400 Enhanced strobe MMC card at address 0001
[ 0.802867] mmcblk0: mmc0:0001 C9A611 58.3 GiB
[ 0.806837] mmcblk0: p1
[ 0.807374] mmcblk0boot0: mmc0:0001 C9A611 4.00 MiB
[ 0.809014] mmcblk0boot1: mmc0:0001 C9A611 4.00 MiB
[ 0.810526] mmcblk0rpmb: mmc0:0001 C9A611 16.0 MiB, chardev (248:0)
[ 0.884811] rk_gmac-dwmac 2a040000.ethernet: IRQ sfty not found
[ 0.885249] rk_gmac-dwmac 2a040000.ethernet: clock input or output? (output).
[ 0.885262] rk_gmac-dwmac 2a040000.ethernet: TX delay(0x20).
[ 0.885269] rk_gmac-dwmac 2a040000.ethernet: Can not read property: rx_delay.
[ 0.885275] rk_gmac-dwmac 2a040000.ethernet: set rx_delay to 0x10
[ 0.885362] rk_gmac-dwmac 2a040000.ethernet: integrated PHY? (no).
[ 0.890392] rk_gmac-dwmac 2a040000.ethernet: init for RGMII_RXID
[ 0.890584] rk_gmac-dwmac 2a040000.ethernet: User ID: 0x50, Synopsys ID: 0x51
[ 0.890595] rk_gmac-dwmac 2a040000.ethernet: DWMAC4/5
[ 0.890603] rk_gmac-dwmac 2a040000.ethernet: DMA HW capability register supported
[ 0.890608] rk_gmac-dwmac 2a040000.ethernet: Active PHY interface: RGMII (1)
[ 0.890615] rk_gmac-dwmac 2a040000.ethernet: RX Checksum Offload Engine supported
[ 0.890620] rk_gmac-dwmac 2a040000.ethernet: TX Checksum insertion supported
[ 0.890625] rk_gmac-dwmac 2a040000.ethernet: Wake-Up On Lan supported
[ 0.890675] rk_gmac-dwmac 2a040000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[ 0.890682] rk_gmac-dwmac 2a040000.ethernet: Enabled L3L4 Flow TC (entries=2)
[ 0.890693] rk_gmac-dwmac 2a040000.ethernet: Enabled RFS Flow TC (entries=10)
[ 0.890699] rk_gmac-dwmac 2a040000.ethernet: TSO supported
[ 0.890704] rk_gmac-dwmac 2a040000.ethernet: TSO feature enabled
[ 0.890709] rk_gmac-dwmac 2a040000.ethernet: SPH feature enabled
[ 0.890714] rk_gmac-dwmac 2a040000.ethernet: Using 40/40 bits DMA host/device width
[ 0.913126] usb 1-1: new high-speed USB device number 2 using xhci-hcd
[ 1.048394] clk: Disabling unused clocks
[ 1.048873] PM: genpd: Disabling unused power domains
[ 1.051000] Freeing unused kernel memory: 4800K
[ 1.051125] Run /init as init process
[ 1.051130] with arguments:
[ 1.051134] /init
[ 1.051137] with environment:
[ 1.051139] HOME=/
[ 1.051141] TERM=linux
[ 1.051144] splash=verbose
[ 1.051146] ubootpart=48cd0da4-4dfb-4b7c-b03f-e4a0c57ddacd
[ 1.051149] cgroup_enable=memory
[ 1.051151] cgroup_memory=1
[ 1.106465] hub 1-1:1.0: USB hub found
[ 1.106513] hub 1-1:1.0: 4 ports detected
[ 1.177969] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
[ 1.218522] hub 2-1:1.0: USB hub found
[ 1.218968] hub 2-1:1.0: 4 ports detected
[ 1.505447] usb 2-1.2: new SuperSpeed USB device number 3 using xhci-hcd
[ 1.528547] usb-storage 2-1.2:1.0: USB Mass Storage device detected
[ 1.529653] scsi host0: usb-storage 2-1.2:1.0
[ 1.536346] rk_gmac-dwmac 29d20000.ethernet end0: renamed from eth0
[ 1.537766] rk_gmac-dwmac 2a040000.ethernet end1: renamed from eth1
[ 1.686075] raid6: using neon recovery algorithm
[ 1.717069] raid6: int64x1 gen() 847 MB/s
[ 1.737837] raid6: int64x2 gen() 1264 MB/s
[ 1.752864] raid6: int64x4 gen() 1747 MB/s
[ 1.763929] raid6: int64x8 gen() 2371 MB/s
[ 1.773319] raid6: neonx1 gen() 2796 MB/s
[ 1.781011] raid6: neonx2 gen() 3409 MB/s
[ 1.786289] raid6: neonx4 gen() 4970 MB/s
[ 1.791806] raid6: neonx8 gen() 4753 MB/s
[ 1.791809] raid6: using algorithm neonx4 gen() 4970 MB/s
[ 1.794906] raid6: .... xor() 4236 MB/s, rmw enabled
[ 1.796085] xor: measuring software checksum speed
[ 1.797076] neon : 13380 MB/sec
[ 1.798330] 32regs : 10491 MB/sec
[ 1.799540] 8regs : 10874 MB/sec
[ 1.799542] xor: using function: neon (13380 MB/sec)
[ 1.849991] Btrfs loaded, zoned=no, fsverity=no
[ 1.937396] EXT4-fs (mmcblk0p1): mounted filesystem 2520cc50-b3ea-430f-ba9b-552afa4b6f82 ro with writeback data mode. Quota mode: disabled.
[ 2.097144] usb 1-1.3: new high-speed USB device number 3 using xhci-hcd
[ 2.124255] systemd[1]: System time advanced to timestamp on /var/lib/systemd/timesync/clock: Wed 2026-10-21 09:39:33 UTC
[ 2.159722] systemd[1]: systemd 257.13-1~deb13u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +IPE +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBCRYPTSETUP_PLUGINS +LIBFDISK +PCRE2 +PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD +BPF_FRAMEWORK +BTF -XKBCOMMON -UTMP +SYSVINIT +LIBARCHIVE)
[ 2.159752] systemd[1]: Detected architecture arm64.
[ 2.187497] usb-storage 1-1.3:1.0: USB Mass Storage device detected
[ 2.187840] scsi host1: usb-storage 1-1.3:1.0
[ 2.304474] systemd[1]: bpf-restrict-fs: BPF LSM hook not enabled in the kernel, BPF LSM not supported.
[ 2.333489] dw-apb-uart 2c130000.serial: forbid DMA for kernel console
[ 2.561278] scsi 0:0:0:0: Direct-Access Generic MassStorageClass 2962 PQ: 0 ANSI: 6
[ 2.562581] sd 0:0:0:0: [sda] Media removed, stopped polling
[ 2.563353] systemd[1]: Queued start job for default target graphical.target.
[ 2.564595] scsi 0:0:0:1: Direct-Access Generic MassStorageClass 2962 PQ: 0 ANSI: 6
[ 2.568510] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
[ 2.570149] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
[ 2.571561] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
[ 2.572692] systemd[1]: Created slice user.slice - User and Session Slice.
[ 2.573163] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
[ 2.573510] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
[ 2.573797] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point skipped, unmet condition check ConditionPathExists=/proc/sys/fs/binfmt_misc
[ 2.573881] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
[ 2.574097] systemd[1]: Reached target paths.target - Path Units.
[ 2.574254] systemd[1]: Reached target remote-fs.target - Remote File Systems.
[ 2.574386] systemd[1]: Reached target slices.target - Slice Units.
[ 2.574522] systemd[1]: Reached target swap.target - Swaps.
[ 2.575001] systemd[1]: Listening on syslog.socket - Syslog Socket.
[ 2.577411] systemd[1]: Listening on systemd-creds.socket - Credential Encryption/Decryption.
[ 2.577941] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
[ 2.578412] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
[ 2.578959] systemd[1]: Listening on systemd-journald.socket - Journal Sockets.
[ 2.579632] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
[ 2.579893] systemd[1]: systemd-pcrextend.socket - TPM PCR Measurements skipped, unmet condition check ConditionSecurity=measured-uki
[ 2.579945] systemd[1]: systemd-pcrlock.socket - Make TPM PCR Policy skipped, unmet condition check ConditionSecurity=measured-uki
[ 2.580276] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
[ 2.580707] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
[ 2.581241] systemd[1]: dev-hugepages.mount - Huge Pages File System skipped, unmet condition check ConditionPathExists=/sys/kernel/mm/hugepages
[ 2.584057] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
[ 2.586938] systemd[1]: Mounting run-lock.mount - Legacy Locks Directory /run/lock...
[ 2.589826] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
[ 2.592783] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
[ 2.593548] sd 0:0:0:0: [sda] Attached SCSI removable disk
[ 2.596003] systemd[1]: Starting fake-hwclock-load.service - Restore the current clock...
[ 2.600570] systemd[1]: Starting keyboard-setup.service - Set the console keyboard layout...
[ 2.604814] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
[ 2.613686] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
[ 2.617598] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
[ 2.626158] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
[ 2.633752] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
[ 2.634121] systemd[1]: netplan-ovs-cleanup.service - OpenVSwitch configuration for cleanup skipped, unmet condition check ConditionFileIsExecutable=/usr/bin/ovs-vsctl
[ 2.634358] systemd[1]: systemd-hibernate-clear.service - Clear Stale Hibernate Storage Info skipped, unmet condition check ConditionPathExists=/sys/firmware/efi/efivars/HibernateLocation-8cf2644b-4b0b-428f-9387-6d876050dc67
[ 2.639834] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
[ 2.643700] systemd[1]: Starting systemd-network-generator.service - Generate Network Units from Kernel Command Line...
[ 2.644139] systemd[1]: systemd-pcrmachine.service - TPM PCR Machine ID Measurement skipped, unmet condition check ConditionSecurity=measured-uki
[ 2.644383] systemd[1]: systemd-tpm2-setup-early.service - Early TPM SRK Setup skipped, unmet condition check ConditionSecurity=measured-uki
[ 2.648310] systemd[1]: Starting systemd-udev-load-credentials.service - Load udev Rules from Credentials...
[ 2.652281] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
[ 2.661621] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
[ 2.663368] systemd[1]: Mounted run-lock.mount - Legacy Locks Directory /run/lock.
[ 2.664501] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
[ 2.665462] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
[ 2.666583] systemd[1]: fake-hwclock-load.service: Deactivated successfully.
[ 2.667169] systemd[1]: Finished fake-hwclock-load.service - Restore the current clock.
[ 2.668734] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
[ 2.669954] systemd[1]: modprobe@configfs.service: Deactivated successfully.
[ 2.670577] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
[ 2.671875] systemd[1]: modprobe@drm.service: Deactivated successfully.
[ 2.672499] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
[ 2.673859] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
[ 2.674460] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
[ 2.675669] systemd[1]: modprobe@fuse.service: Deactivated successfully.
[ 2.676291] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
[ 2.683474] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
[ 2.686792] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
[ 2.687022] systemd[1]: systemd-fsck-root.service - File System Check on Root Device skipped, unmet condition check ConditionPathExists=!/run/initramfs/fsck-root
[ 2.697694] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
[ 2.705654] systemd[1]: Starting systemd-tmpfiles-setup-dev-early.service - Create Static Device Nodes in /dev gracefully...
[ 2.708619] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
[ 2.714637] systemd[1]: Finished systemd-network-generator.service - Generate Network Units from Kernel Command Line.
[ 2.719008] systemd[1]: Finished systemd-udev-load-credentials.service - Load udev Rules from Credentials.
[ 2.721423] systemd[1]: Mounted sys-fs-fuse-connections.mount - FUSE Control File System.
[ 2.722109] systemd[1]: Reached target network-pre.target - Preparation for Network.
[ 2.725804] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
[ 2.727801] systemd[1]: Mounted sys-kernel-config.mount - Kernel Configuration File System.
[ 2.772223] systemd[1]: Finished systemd-tmpfiles-setup-dev-early.service - Create Static Device Nodes in /dev gracefully.
[ 2.773872] EXT4-fs (mmcblk0p1): re-mounted 2520cc50-b3ea-430f-ba9b-552afa4b6f82 r/w.
[ 2.777912] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
[ 2.779673] systemd[1]: systemd-hwdb-update.service - Rebuild Hardware Database skipped, unmet condition check ConditionNeedsUpdate=/etc
[ 2.779919] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival skipped, unmet condition check ConditionDirectoryNotEmpty=/sys/fs/pstore
[ 2.783365] systemd[1]: Starting systemd-random-seed.service - Load/Save OS Random Seed...
[ 2.783733] systemd[1]: systemd-sysusers.service - Create System Users skipped, no trigger condition checks were met.
[ 2.790652] systemd[1]: Starting systemd-timesyncd.service - Network Time Synchronization...
[ 2.793619] systemd[1]: Starting systemd-tmpfiles-setup-dev.service - Create Static Device Nodes in /dev...
[ 2.793932] systemd[1]: systemd-tpm2-setup.service - TPM SRK Setup skipped, unmet condition check ConditionSecurity=measured-uki
[ 2.795274] systemd[1]: Finished keyboard-setup.service - Set the console keyboard layout.
[ 2.796841] systemd[1]: Finished systemd-sysctl.service - Apply Kernel Variables.
[ 2.803118] systemd[1]: Starting systemd-resolved.service - Network Name Resolution...
[ 2.852608] systemd[1]: Finished systemd-tmpfiles-setup-dev.service - Create Static Device Nodes in /dev.
[ 2.853310] systemd[1]: Reached target local-fs-pre.target - Preparation for Local File Systems.
[ 2.857305] systemd[1]: Starting systemd-udevd.service - Rule-based Manager for Device Events and Files...
[ 2.956019] systemd[1]: Started systemd-timesyncd.service - Network Time Synchronization.
[ 2.957257] systemd[1]: Reached target time-set.target - System Time Set.
[ 3.028829] systemd[1]: Started systemd-udevd.service - Rule-based Manager for Device Events and Files.
[ 3.037801] systemd[1]: Starting systemd-networkd.service - Network Configuration...
[ 3.108456] sd 0:0:0:1: [sdb] Spinning up disk...
[ 3.157455] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
[ 3.185174] random: crng init done
[ 3.193688] systemd[1]: Finished systemd-random-seed.service - Load/Save OS Random Seed.
[ 3.194566] systemd[1]: first-boot-complete.target - First Boot Complete skipped, unmet condition check ConditionFirstBoot=yes
[ 3.204351] scsi 1:0:0:0: Direct-Access HIKSEMI PSSD 0100 PQ: 0 ANSI: 6
[ 3.210912] sd 1:0:0:0: [sdc] 2000409264 512-byte logical blocks: (1.02 TB/954 GiB)
[ 3.212772] sd 1:0:0:0: [sdc] Write Protect is off
[ 3.212811] sd 1:0:0:0: [sdc] Mode Sense: 43 00 00 00
[ 3.213208] sd 1:0:0:0: [sdc] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[ 3.234251] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[ 3.239605] systemd[1]: Found device dev-ttyS0.device - /dev/ttyS0.
[ 3.270004] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[ 3.271763] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
[ 3.277656] systemd[1]: Started systemd-resolved.service - Network Name Resolution.
[ 3.288182] sdc: sdc1 sdc2
[ 3.288736] sd 1:0:0:0: [sdc] Attached SCSI disk
[ 3.857154] systemd[1]: Reached target nss-lookup.target - Host and Network Name Lookups.
[ 3.857424] systemd[1]: Reached target usb-gadget.target - Hardware activated USB gadget.
[ 3.862630] systemd[1]: Mounting tmp.mount - /tmp...
[ 3.891645] systemd[1]: Mounted tmp.mount - /tmp.
[ 3.892193] systemd[1]: Reached target local-fs.target - Local File Systems.
[ 3.894856] systemd[1]: Listening on systemd-sysext.socket - System Extension Image Management.
[ 3.897761] systemd[1]: Starting armbian-zram-config.service - Armbian ZRAM config...
[ 3.900711] systemd[1]: Starting console-setup.service - Set console font and keymap...
[ 3.901703] systemd[1]: systemd-binfmt.service - Set Up Additional Binary Formats skipped, unmet condition check ConditionPathIsMountPoint=/proc/sys/fs/binfmt_misc
[ 3.901895] systemd[1]: systemd-machine-id-commit.service - Save Transient machine-id to Disk skipped, unmet condition check ConditionPathIsMountPoint=/etc/machine-id
[ 3.935051] systemd[1]: Finished console-setup.service - Set console font and keymap.
[ 4.125129] .ready
[ 4.496526] sd 0:0:0:1: [sdb] 122167296 512-byte logical blocks: (62.5 GB/58.3 GiB)
[ 4.497199] sd 0:0:0:1: [sdb] Write Protect is off
[ 4.497208] sd 0:0:0:1: [sdb] Mode Sense: 21 00 00 00
[ 4.497863] sd 0:0:0:1: [sdb] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 4.526869] sdb: sdb1
[ 4.527177] sd 0:0:0:1: [sdb] Attached SCSI removable disk
[ 4.536274] zram: Added device: zram0
[ 4.536958] zram: Added device: zram1
[ 4.537502] zram: Added device: zram2
[ 4.560724] zswap: loaded using pool lzo
[ 4.583622] zram0: detected capacity change from 0 to 4021480
[ 4.602878] Adding 2010736k swap on /dev/zram0. Priority:5 extents:1 across:2010736k SS
[ 4.618289] systemd[1]: Started systemd-networkd.service - Network Configuration.
[ 4.620664] rk_gmac-dwmac 2a040000.ethernet end1: Register MEM_TYPE_PAGE_POOL RxQ-0
[ 4.623308] systemd[1]: Starting systemd-networkd-persistent-storage.service - Enable Persistent Storage in systemd-networkd...
[ 4.635307] zram1: detected capacity change from 0 to 102400
[ 4.649148] rk_gmac-dwmac 2a040000.ethernet end1: PHY [stmmac-1:01] driver [RTL8211F Gigabit Ethernet] (irq=POLL)
[ 4.651091] dwmac4: Master AXI performs any burst length
[ 4.651105] rk_gmac-dwmac 2a040000.ethernet end1: No Safety Features support found
[ 4.651449] rk_gmac-dwmac 2a040000.ethernet end1: IEEE 1588-2008 Advanced Timestamp supported
[ 4.651645] rk_gmac-dwmac 2a040000.ethernet end1: registered PTP clock
[ 4.651652] rk_gmac-dwmac 2a040000.ethernet end1: configuring for phy/rgmii-rxid link mode
[ 4.672612] systemd[1]: Finished armbian-zram-config.service - Armbian ZRAM config.
[ 4.675764] systemd[1]: Starting armbian-ramlog.service - Armbian memory supported logging...
[ 4.679240] rk_gmac-dwmac 29d20000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
[ 4.705167] rk_gmac-dwmac 29d20000.ethernet end0: PHY [stmmac-0:02] driver [RTL8211F Gigabit Ethernet] (irq=POLL)
[ 4.717129] dwmac4: Master AXI performs any burst length
[ 4.717166] rk_gmac-dwmac 29d20000.ethernet end0: No Safety Features support found
[ 4.717690] rk_gmac-dwmac 29d20000.ethernet end0: IEEE 1588-2008 Advanced Timestamp supported
[ 4.718006] rk_gmac-dwmac 29d20000.ethernet end0: registered PTP clock
[ 4.718031] rk_gmac-dwmac 29d20000.ethernet end0: configuring for phy/rgmii-rxid link mode
[ 4.747457] systemd[1]: Finished systemd-networkd-persistent-storage.service - Enable Persistent Storage in systemd-networkd.
[ 4.748565] EXT4-fs (zram1): mounted filesystem 839fe5ef-a8e2-4adc-b9a0-0c76a7cc60b4 r/w without journal. Quota mode: disabled.
[ 5.000713] systemd[1]: Finished armbian-ramlog.service - Armbian memory supported logging.
[ 5.007005] systemd[1]: Starting systemd-journald.service - Journal Service...
[ 5.093778] systemd-journald[438]: Collecting audit messages is disabled.
[ 5.173135] systemd[1]: Started systemd-journald.service - Journal Service.
[ 5.231994] systemd-journald[438]: Received client request to flush runtime journal.
[ 5.588283] systemd-journald[438]: Received client request to relinquish /var/log/journal/958cd540f0e041c6b855006cbba7667a access.
[ 6.241260] NOTICE: Automounting of tracing to debugfs is deprecated and will be removed in 2030
[ 7.806604] rk_gmac-dwmac 29d20000.ethernet end0: Link is Up - 1Gbps/Full - flow control rx/tx
[ 8.766543] rk_gmac-dwmac 2a040000.ethernet end1: Link is Up - 1Gbps/Full - flow control rx/tx
[ 31.709317] vdd_npu_s0: disabling
To: Stephen Boyd <sboyd@kernel.org>
To: Brian Masney <bmasney+clk@redhat.com>
To: Jerome Brunet <jbrunet+clk@baylibre.com>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Heiko Stuebner <heiko@sntech.de>
To: Philipp Zabel <p.zabel@pengutronix.de>
To: Elaine Zhang <zhangqing@rock-chips.com>
To: Lee Jones <lee@kernel.org>
To: Linus Walleij <linusw@kernel.org>
To: Bartosz Golaszewski <brgl@kernel.org>
To: Richard Cochran <richardcochran@gmail.com>
To: Ulf Hansson <ulfh@kernel.org>
To: Andi Shyti <andi.shyti@kernel.org>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: Jiri Slaby <jirislaby@kernel.org>
To: Jisheng Zhang <jszhang@kernel.org>
To: Andrew Lunn <andrew+netdev@lunn.ch>
To: "David S. Miller" <davem@davemloft.net>
To: Eric Dumazet <edumazet@kernel.org>
To: Jakub Kicinski <kuba@kernel.org>
To: Paolo Abeni <pabeni@redhat.com>
To: David Wu <david.wu@rock-chips.com>
To: "Rafael J. Wysocki" <rafael@kernel.org>
To: Daniel Lezcano <daniel.lezcano@kernel.org>
To: Zhang Rui <rui.zhang@intel.com>
To: Lukasz Luba <lukasz.luba@arm.com>
To: Maxime Chevallier <maxime.chevallier@bootlin.com>
To: Maxime Coquelin <mcoquelin.stm32@gmail.com>
To: Alexandre Torgue <alexandre.torgue@foss.st.com>
To: Vinod Koul <vkoul@kernel.org>
To: Neil Armstrong <neil.armstrong@linaro.org>
To: Manivannan Sadhasivam <mani@kernel.org>
To: Cunhao Lu <1579567540@qq.com>
To: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
To: Jaehoon Chung <jh80.chung@samsung.com>
To: Shawn Lin <shawn.lin@rock-chips.com>
Cc: linux-clk@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: mfd@lists.linux.dev
Cc: linux-gpio@vger.kernel.org
Cc: netdev@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: linux-i2c@vger.kernel.org
Cc: linux-serial@vger.kernel.org
Cc: linux-mmc@vger.kernel.org
Cc: linux-stm32@st-md-mailman.stormreply.com
Cc: linux-phy@lists.infradead.org
Cc: linux-usb@vger.kernel.org
---
Cunhao Lu (27):
dt-bindings: clock: rockchip: Add RK3572 CRU
dt-bindings: power: rockchip: Add RK3572 power domains
dt-bindings: soc: rockchip: Add RK3572 PMU and GRF
dt-bindings: mfd: syscon: Add RK3572 QoS register compatible
dt-bindings: pinctrl: rockchip: Add RK3572
dt-bindings: gpio: rockchip: Add RK3572 GPIO banks
clk: rockchip: Add RK3572 clock and reset support
pinctrl: rockchip: Add RK3572 support
gpio: rockchip: Add RK3572 GPIO support
pmdomain: rockchip: Add RK3572 boot peripheral domains
dt-bindings: i2c: rk3x: Add RK3572
dt-bindings: serial: snps-dw-apb-uart: Add RK3572
dt-bindings: mmc: rockchip: Add RK3572 controllers
dt-bindings: net: rockchip-dwmac: Add RK3572
dt-bindings: thermal: rockchip: Add RK3572
net: stmmac: dwmac-rk: Add RK3572 support
thermal: rockchip: Add RK3572 support
dt-bindings: phy: rockchip-inno-usb2: Add RK3572
dt-bindings: phy: rockchip-naneng-combphy: Add RK3572
dt-bindings: usb: rockchip: Add RK3572 DWC3 controller
phy: rockchip-inno-usb2: Add RK3572 support
phy: rockchip-naneng-combphy: Add RK3572 support
usb: dwc3: Configure RK3572 PIPE port before discovery
mmc: dw_mmc-rockchip: Keep RK3572 NVM domain powered
dt-bindings: arm: rockchip: Add Forlinx OK3572-C
arm64: dts: rockchip: Add RK3572 SoC
arm64: dts: rockchip: Add initial support for Forlinx OK3572-C
.../devicetree/bindings/arm/rockchip.yaml | 6 +
.../devicetree/bindings/arm/rockchip/pmu.yaml | 2 +
.../bindings/clock/rockchip,rk3572-cru.yaml | 57 +
.../bindings/gpio/rockchip,gpio-bank.yaml | 24 +-
.../devicetree/bindings/i2c/i2c-rk3x.yaml | 1 +
Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
.../devicetree/bindings/mmc/rockchip-dw-mshc.yaml | 1 +
.../bindings/mmc/snps,dwcmshc-sdhci.yaml | 3 +
.../devicetree/bindings/net/rockchip-dwmac.yaml | 3 +
.../bindings/phy/phy-rockchip-naneng-combphy.yaml | 23 +
.../bindings/phy/rockchip,inno-usb2phy.yaml | 14 +
.../bindings/pinctrl/rockchip,pinctrl.yaml | 1 +
.../bindings/power/rockchip,power-controller.yaml | 17 +
.../bindings/serial/snps-dw-apb-uart.yaml | 1 +
.../devicetree/bindings/soc/rockchip/grf.yaml | 12 +
.../bindings/thermal/rockchip-thermal.yaml | 2 +
.../bindings/usb/rockchip,rk3572-dwc3.yaml | 100 +
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../dts/rockchip/rk3572-forlinx-fet3572-c.dtsi | 369 ++
.../boot/dts/rockchip/rk3572-forlinx-ok3572-c.dts | 286 ++
arch/arm64/boot/dts/rockchip/rk3572-opp.dtsi | 165 +
arch/arm64/boot/dts/rockchip/rk3572-pinctrl.dtsi | 3935 ++++++++++++++++++++
arch/arm64/boot/dts/rockchip/rk3572.dtsi | 1325 +++++++
drivers/clk/rockchip/Kconfig | 7 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-rk3572.c | 1972 ++++++++++
drivers/clk/rockchip/clk.h | 36 +
drivers/clk/rockchip/rst-rk3572.c | 739 ++++
drivers/gpio/gpio-rockchip.c | 91 +-
drivers/mmc/host/dw_mmc-rockchip.c | 24 +
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 53 +
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 136 +
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 201 +
drivers/pinctrl/pinctrl-rockchip.c | 230 +-
drivers/pinctrl/pinctrl-rockchip.h | 9 +-
drivers/pmdomain/rockchip/pm-domains.c | 141 +-
drivers/thermal/rockchip_thermal.c | 28 +
drivers/usb/dwc3/dwc3-generic-plat.c | 31 +
include/dt-bindings/clock/rockchip,rk3572-cru.h | 560 +++
.../power/rockchip,rk3572-power-controller.h | 30 +
include/dt-bindings/reset/rockchip,rk3572-cru.h | 713 ++++
include/soc/rockchip/rockchip_sip.h | 5 +
42 files changed, 11332 insertions(+), 24 deletions(-)
---
base-commit: a804c5742bff224d4cb4d25dd383554d598be32b
change-id: 20261021-add-board-ok3572-c-8ed18b9065da
Best regards,
--
Cunhao Lu <1579567540@qq.com>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 01/27] dt-bindings: clock: rockchip: Add RK3572 CRU
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
@ 2026-10-21 16:10 ` Cunhao Lu via B4 Relay
2026-10-21 16:10 ` [PATCH 02/27] dt-bindings: power: rockchip: Add RK3572 power domains Cunhao Lu via B4 Relay
` (26 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:10 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
The CRU uses the PMU0 GRF for PLL status and the AUPLL reference mux.
Describe the controller and define its clock and reset IDs.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
.../bindings/clock/rockchip,rk3572-cru.yaml | 57 ++
include/dt-bindings/clock/rockchip,rk3572-cru.h | 560 ++++++++++++++++
include/dt-bindings/reset/rockchip,rk3572-cru.h | 713 +++++++++++++++++++++
3 files changed, 1330 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3572-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3572-cru.yaml
new file mode 100644
index 000000000000..89e360ccb884
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3572-cru.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3572-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3572 Family Clock and Reset Control Module
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description:
+ The RK3572 CRU supplies peripheral clocks and resets.
+
+properties:
+ compatible:
+ const: rockchip,rk3572-cru
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: xin24m
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: PMU0 GRF register block.
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+ - rockchip,grf
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@26090000 {
+ compatible = "rockchip,rk3572-cru";
+ reg = <0x26090000 0x60000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ rockchip,grf = <&pmu0_grf>;
+ };
diff --git a/include/dt-bindings/clock/rockchip,rk3572-cru.h b/include/dt-bindings/clock/rockchip,rk3572-cru.h
new file mode 100644
index 000000000000..9c586d9e9ae9
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rk3572-cru.h
@@ -0,0 +1,560 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3572_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3572_H
+
+/* PLLs */
+#define PLL_PPLL 0
+#define PLL_BPLL 1
+#define PLL_LPLL 2
+#define PLL_AUPLL 3
+#define PLL_CPLL 4
+#define PLL_GPLL 5
+#define PLL_VPLL 6
+#define ARMCLK_L0 7
+#define ARMCLK_L1 8
+#define ARMCLK_B 9
+
+#define CLK_CPLL_DIV20 10
+#define CLK_CPLL_DIV10 11
+#define CLK_GPLL_DIV8 12
+#define CLK_GPLL_DIV6 13
+#define CLK_CPLL_DIV4 14
+#define CLK_GPLL_DIV4 15
+#define CLK_GPLL_DIV3 16
+#define CLK_CPLL_DIV2 17
+#define CLK_GPLL_DIV2 18
+#define CLK_DDRPHY_TOP_SRC 19
+#define PCLK_TOP_ROOT 20
+#define ACLK_TOP 21
+#define ACLK_TOP_MID 22
+#define ACLK_SECURE_HIGH 23
+#define CLK_BPLL_DIV 24
+#define CLK_AUDIO_FRAC_0 25
+#define CLK_AUDIO_FRAC_1 26
+#define CLK_AUDIO_FRAC_2 27
+#define CLK_AUDIO_FRAC_3 28
+#define CLK_AUDIO_FRAC_0_SRC 29
+#define CLK_AUDIO_FRAC_1_SRC 30
+#define CLK_AUDIO_FRAC_2_SRC 31
+#define CLK_AUDIO_FRAC_3_SRC 32
+#define HCLK_TOP 33
+#define CLK_UART_FRAC_0 34
+#define CLK_UART_FRAC_1 35
+#define CLK_UART_FRAC_2 36
+#define CLK_UART_FRAC_0_SRC 37
+#define CLK_UART_FRAC_1_SRC 38
+#define CLK_UART_FRAC_2_SRC 39
+
+#define CLK_UART1_SRC_TOP 40
+#define CLK_AUDIO_INT_0 41
+#define CLK_AUDIO_INT_1 42
+#define CLK_AUDIO_INT_2 43
+#define CLK_PDM0_SRC_TOP 44
+#define CLK_GMAC0_125M_SRC 45
+#define CLK_GMAC1_125M_SRC 46
+#define MCLK_ASRC0_SRC_0 47
+#define MCLK_ASRC1_SRC_1 48
+#define REF_CLK0_OUT_PLL 49
+#define REF_CLK1_OUT_PLL 50
+#define REF_CLK2_OUT_PLL 51
+#define REF_PULSE_CLK_AUDIO_FRAC_0 52
+#define REF_PULSE_CLK_AUDIO_FRAC_1 53
+#define REF_PULSE_CLK_AUDIO_FRAC_2 54
+#define REF_PULSE_FRACDIV_3 55
+#define REF_PULSE_AUPLL 56
+#define CLK_SAI1_MCLKOUT 57
+#define CLK_SAI2_MCLKOUT 58
+#define CLK_SAI3_MCLKOUT 59
+#define CLK_SAI0_MCLKOUT 60
+#define REFCLKO25M_GMAC0_OUT 61
+#define REFCLKO25M_GMAC1_OUT 62
+#define CLK_CIFOUT_OUT 63
+#define CLK_GMAC0_RMII_CRU 64
+#define CLK_GMAC1_RMII_CRU 65
+#define CLK_OTPC_AUTO_RD_G 66
+#define CAM_CLK0_OUT_IOUT 67
+#define CAM_CLK1_OUT_IOUT 68
+#define CAM_CLK2_OUT_IOUT 69
+#define MCLK_PDM0_SRC_TOP 70
+#define HCLK_AUDIO_ROOT 71
+#define HCLK_ASRC_2CH_0 72
+#define HCLK_ASRC_2CH_1 73
+#define CLK_ASRC_2CH_0 74
+#define CLK_ASRC_2CH_1 75
+#define MCLK_SAI0 76
+#define HCLK_SAI0 77
+#define HCLK_SPDIF_RX0 78
+#define MCLK_SPDIF_RX0 79
+#define MCLK_SAI1 80
+#define HCLK_SAI1 81
+#define MCLK_SAI2 82
+#define HCLK_SAI2 83
+#define MCLK_SAI3 84
+#define HCLK_SAI3 85
+#define LRCK_ASRC_2CH0_SRC 86
+#define LRCK_ASRC_2CH0_DST 87
+#define LRCK_ASRC_2CH1_SRC 88
+#define LRCK_ASRC_2CH1_DST 89
+#define HCLK_ACDCDIG_DSM 90
+#define MCLK_ACDCDIG_DSM 91
+#define PCLK_AUDIO_ROOT 92
+#define HCLK_SPDIF_TX0 93
+#define MCLK_SPDIF_TX0 94
+#define HCLK_SPDIF_TX1 95
+#define MCLK_SPDIF_TX1 96
+#define ASRC_REF_PULSE 97
+#define HCLK_BUS_ROOT 98
+#define PCLK_BUS_ROOT 99
+#define ACLK_BUS_ROOT 100
+#define HCLK_CAN0 101
+#define CLK_CAN0 102
+#define HCLK_CAN1 103
+#define CLK_CAN1 104
+#define HCLK_CAN2 105
+#define CLK_CAN2 106
+#define HCLK_CAN3 107
+#define CLK_CAN3 108
+#define ACLK_DECOM_ROOT 109
+#define AUPLL_REF 110
+#define PCLK_I2C1 111
+#define PCLK_I2C2 112
+#define PCLK_I2C3 113
+#define PCLK_I2C4 114
+#define PCLK_I2C5 115
+#define PCLK_I2C6 116
+#define PCLK_I2C7 117
+#define PCLK_I2C8 118
+#define PCLK_I2C9 119
+#define PCLK_WDT_BUSMCU 120
+#define TCLK_WDT_BUSMCU 121
+#define ACLK_GIC 122
+#define CLK_I2C1 123
+#define CLK_I2C2 124
+#define CLK_I2C3 125
+#define CLK_I2C4 126
+#define CLK_I2C5 127
+#define CLK_I2C6 128
+#define CLK_I2C7 129
+#define CLK_I2C8 130
+#define CLK_I2C9 131
+#define PCLK_SARADC 132
+#define CLK_SARADC 133
+#define PCLK_TSADC 134
+#define CLK_TSADC 135
+#define PCLK_UART0 136
+#define PCLK_UART2 137
+#define PCLK_UART3 138
+#define PCLK_UART4 139
+#define PCLK_UART5 140
+#define PCLK_UART6 141
+#define PCLK_UART7 142
+#define PCLK_UART8 143
+#define PCLK_UART9 144
+#define PCLK_UART10 145
+#define PCLK_UART11 146
+#define SCLK_UART0 147
+#define SCLK_UART2 148
+#define SCLK_UART3 149
+#define SCLK_UART4 150
+#define SCLK_UART5 151
+#define SCLK_UART6 152
+#define SCLK_UART7 153
+#define SCLK_UART8 154
+#define SCLK_UART9 155
+#define SCLK_UART10 156
+#define SCLK_UART11 157
+#define PCLK_SPI0 158
+#define PCLK_SPI1 159
+#define PCLK_SPI2 160
+#define PCLK_SPI3 161
+#define PCLK_SPI4 162
+#define CLK_SPI0 163
+#define CLK_SPI1 164
+#define CLK_SPI2 165
+#define CLK_SPI3 166
+#define CLK_SPI4 167
+#define PCLK_WDT0 168
+#define TCLK_WDT0 169
+#define PCLK_PWM1 170
+#define CLK_PWM1 171
+#define CLK_OSC_PWM1 172
+#define CLK_RC_PWM1 173
+#define CLK_FREQ_PWM1 174
+#define CLK_COUNTER_PWM1 175
+#define PCLK_PWM2 176
+#define CLK_PWM2 177
+#define CLK_RC_PWM2 178
+#define CLK_OSC_PWM2 179
+#define SAI_SCLKIN_FREQ 180
+#define SAI_SCLKIN_COUNTER 181
+#define PCLK_BUSTIMER0 182
+#define PCLK_BUSTIMER1 183
+#define CLK_TIMER0_ROOT 184
+#define CLK_TIMER0 185
+#define CLK_TIMER1 186
+#define CLK_TIMER2 187
+#define CLK_TIMER3 188
+#define CLK_TIMER4 189
+#define CLK_TIMER5 190
+#define PCLK_MAILBOX0 191
+#define PCLK_GPIO1 192
+#define DBCLK_GPIO1 193
+#define PCLK_GPIO2 194
+#define DBCLK_GPIO2 195
+#define PCLK_GPIO3 196
+#define DBCLK_GPIO3 197
+#define PCLK_GPIO4 198
+#define DBCLK_GPIO4 199
+#define ACLK_DECOM 200
+#define PCLK_DECOM 201
+#define DCLK_DECOM 202
+#define CLK_TIMER1_ROOT 203
+#define CLK_TIMER6 204
+#define CLK_TIMER7 205
+#define CLK_TIMER8 206
+#define CLK_TIMER9 207
+#define CLK_TIMER10 208
+#define CLK_TIMER11 209
+#define ACLK_RKDMA0 210
+#define PCLK_RKDMA0 211
+#define ACLK_RKDMA1 212
+#define PCLK_RKDMA1 213
+#define ACLK_RKDMA2 214
+#define PCLK_RKDMA2 215
+#define ACLK_RKDMA3 216
+#define PCLK_RKDMA3 217
+#define PCLK_SPINLOCK 218
+#define CLK_I3C 219
+#define HCLK_I3C 220
+#define CLK_BUSMCU_ROOT 221
+#define CLK_BUSMCU_CORE_AON 222
+#define CLK_MTIME_TOGGLE_A 223
+#define CLK_DBG_TOGGLE_A 224
+#define CLK_MCU_AXI_INTEGRITY 225
+#define PCLK_PMU2 226
+#define CLK_HDMITXHPD 227
+#define PCLK_APB2ASB_HDMITX 228
+#define SCLK_APB2ASB_HDMITX 229
+#define PCLK_APB2ASB_MIPICSI 230
+#define SCLK_APB2ASB_MIPICSI 231
+#define PCLK_APB2ASB_VCCIO0_3 232
+#define SCLK_APB2ASB_VCCIO0_3 233
+#define PCLK_APB2ASB_VCCIO1_2_4 234
+#define SCLK_APB2ASB_VCCIO1_2_4 235
+#define PCLK_APB2ASB_VCCIO5_6 236
+#define SCLK_APB2ASB_VCCIO5_6 237
+#define PCLK_DDR_ROOT 238
+#define ACLK_DDR_ROOT 239
+#define LCLK_DDRSCH_BIU 240
+#define CLK_DDR_TIMER_ROOT 241
+#define CLK_DDR_TIMER0 242
+#define CLK_DDR_TIMER1 243
+#define TCLK_DDR_WDT 244
+#define PCLK_WDT 245
+#define PCLK_TIMER 246
+#define CLK_DDRMCU_ROOT 247
+#define CLK_DDRMCU_CORE_AON 248
+#define CLK_MTIME_TOGGLE_A_DDR 249
+#define CLK_DBG_TOGGLE_A_DDR 250
+#define ACLK_RKNN_ROOT 251
+#define ACLK_RKNN_ROOT_SRC 252
+#define ACLK_RKNN 253
+#define PCLK_RKNN_ROOT 254
+#define CLK_24M_RKNN 255
+#define CLK_NPUTIMER_ROOT 256
+#define CLK_NPUTIMER0 257
+#define CLK_NPUTIMER1 258
+#define PCLK_NPU_TIMER 259
+#define PCLK_NPU_WDT 260
+#define TCLK_NPU_WDT 261
+#define PCLK_PHP0_ROOT 262
+#define ACLK_PHP0_ROOT 263
+#define PCLK_PCIE1 264
+#define CLK_PCIE1_AUX 265
+#define ACLK_PCIE1_MSTR 266
+#define ACLK_PCIE1_SLV 267
+#define ACLK_PCIE1_DBI 268
+#define PCLK_PCIE0 269
+#define CLK_PCIE0_AUX 270
+#define ACLK_PCIE0_MSTR 271
+#define ACLK_PCIE0_SLV 272
+#define ACLK_PCIE0_DBI 273
+#define ACLK_USB3OTG1 274
+#define CLK_REF_USB3OTG1 275
+#define CLK_SUSPEND_USB3OTG1 276
+#define ACLK_GMAC0 277
+#define PCLK_GMAC0 278
+#define ACLK_UFS_ROOT 279
+#define ACLK_USB3OTG0 280
+#define CLK_REF_USB3OTG0 281
+#define CLK_SUSPEND_USB3OTG0 282
+#define ACLK_UFS_SYS 283
+#define CLK_GMAC0_PTP_REF_PRE 284
+#define CLK_GMAC0_PTP_REF_SRC 285
+#define CLK_RXOOB0 286
+#define CLK_PMALIVE0 287
+#define ACLK_SATA0 288
+#define CLK_RXOOB1 289
+#define CLK_PMALIVE1 290
+#define ACLK_SATA1 291
+#define CLK_EEE_XPCS 292
+#define PCLK_XPCS 293
+#define CLK_USB3OTG1_PIPE_PCLK 294
+#define CLK_USB3OTG1_UTMI 295
+#define CLK_USB3OTG0_PIPE_PCLK 296
+#define CLK_USB3OTG0_UTMI 297
+#define HCLK_NVM0_ROOT 298
+#define ACLK_NVM0_ROOT 299
+#define PCLK_NVM0_ROOT 300
+#define CCLK_SRC_EMMC 301
+#define HCLK_EMMC 302
+#define ACLK_EMMC 303
+#define BCLK_EMMC 304
+#define TCLK_EMMC 305
+#define CLK_GMAC1_PTP_REF_SRC 306
+#define CLK_GMAC1_PTP_REF 307
+#define ACLK_GMAC1 308
+#define PCLK_GMAC1 309
+#define SCLK_FSPI0_X2 310
+#define HCLK_FSPI0 311
+#define CCLK_SRC_SDMMC1 312
+#define HCLK_SDMMC1 313
+#define ACLK_DSMC_ROOT 314
+#define ACLK_DSMC 315
+#define HCLK_DSMC_ROOT 316
+#define HCLK_DSMC 317
+#define PCLK_DSMC_ROOT 318
+#define PCLK_DSMC 319
+#define CLK_DSMC_SYS 320
+#define HCLK_NVM1_ROOT 321
+#define PCLK_NVM1_ROOT 322
+#define CCLK_SRC_SDMMC0 323
+#define HCLK_SDMMC0 324
+#define SCLK_FSPI1_X2 325
+#define HCLK_FSPI1 326
+#define PCLK_PHPSUBSYS_ROOT 327
+#define PCLK_PCIE2_COMBOPHY0 328
+#define PCLK_PCIE2_COMBOPHY1 329
+#define PCLK_MPHY 330
+#define CLK_32K_USB2DEBUG 331
+#define PCLK_PCIEPHY2 332
+#define SCLK_APB2ASB_USBMPHY_PHPPHY 333
+#define PCLK_APB2ASB_USBMPHY_PHPPHY 334
+#define CLK_CPLL_DIV10_PHPPHY 335
+#define CLK_PHPPHY_REF 336
+#define CLK_PCIE_100M_SRC 337
+#define CLK_PCIE_100M_NDUTY_SRC 338
+#define CLK_REF_PCIEPHY2 339
+#define CLK_REF_PCIE0_INNER_PHY 340
+#define CLK_REF_PCIE1_INNER_PHY 341
+#define CLK_REF_MPHY_26M 342
+#define REF_CLK_FROM_PPLL 343
+#define HCLK_RKVDEC_ROOT 344
+#define HCLK_RKVDEC 345
+#define ACLK_RKVDEC_ROOT 346
+#define CLK_RKVDEC_HEVC_CA 347
+#define CLK_RKVDEC_CORE 348
+#define PCLK_VDEC_ROOT 349
+#define PCLK_VOSUBSYS_ROOT 350
+#define PCLK_APB2ASB_MIPI_HDMI_SUBVO 351
+#define SCLK_APB2ASB_MIPI_HDMI_SUBVO 352
+#define PCLK_APB2ASB_VCCIO0_3_SUBVO 353
+#define SCLK_APB2ASB_VCCIO0_3_SUBVO 354
+#define PCLK_HDPTXPHY 355
+#define PCLK_MIPI_DPHY0 356
+#define CLK_VOSUBSYS_REF 357
+#define PCLK_IOC_SUBVO 358
+#define PCLK_VISUBSYS_ROOT 359
+#define PCLK_APB2ASB_VCCIO1_2_4_SUBVI 360
+#define SCLK_APB2ASB_VCCIO1_2_4_SUBVI 361
+#define PCLK_APB2ASB_CSIPHY_SUBVI 362
+#define SCLK_APB2ASB_CSIPHY_SUBVI 363
+#define PCLK_CSIPHY0 364
+#define PCLK_CSIPHY1 365
+#define PCLK_IOC_SUBVI 366
+#define CLK_SDMMC_SWITCH_24M 367
+#define PCLK_DSMCSUBSYS_ROOT 368
+#define PCLK_APB2ASB_VCCIO5_6_SUBDSMC 369
+#define SCLK_APB2ASB_VCCIO5_6_SUBDSMC 370
+#define ACLK_IMG_ROOT 371
+#define ACLK_IMG_MID_ROOT 372
+#define HCLK_IMG_ROOT 373
+#define ACLK_JPEG_ROOT 374
+#define ACLK_IMG_LOW_ROOT 375
+#define PCLK_IMG_ROOT 376
+#define HCLK_RGA2E_0 377
+#define ACLK_RGA2E_0 378
+#define CLK_CORE_RGA2E_0 379
+#define ACLK_JPEG 380
+#define HCLK_JPEG 381
+#define HCLK_VDPP 382
+#define ACLK_VDPP 383
+#define CLK_CORE_VDPP 384
+#define DCLK_EBC_SRC_TOP 385
+#define DCLK_EBC_INT_SRC 386
+#define DCLK_EBC_FRAC_SRC 387
+#define HCLK_EBC 388
+#define ACLK_EBC 389
+#define DCLK_EBC 390
+#define HCLK_RKVENC_ROOT 391
+#define ACLK_RKVENC_ROOT 392
+#define HCLK_RKVENC 393
+#define ACLK_RKVENC 394
+#define CLK_RKVENC_CORE 395
+#define ACLK_VI_ROOT 396
+#define HCLK_VI_ROOT 397
+#define PCLK_VI_ROOT 398
+#define DCLK_VICAP 399
+#define ACLK_VICAP 400
+#define HCLK_VICAP 401
+#define CLK_ISP_CORE 402
+#define CLK_ISP_CORE_MARVIN 403
+#define CLK_ISP_CORE_VICAP 404
+#define ACLK_ISP 405
+#define HCLK_ISP 406
+#define ACLK_VPSS 407
+#define HCLK_VPSS 408
+#define CLK_CORE_VPSS 409
+#define PCLK_VI_GRF 410
+#define PCLK_CSI_HOST_0 411
+#define PCLK_CSI_HOST_1 412
+#define PCLK_CSI_HOST_2 413
+#define PCLK_CSI_HOST_3 414
+#define DCLK_VICAP_CSIHOST0 415
+#define DCLK_VICAP_CSIHOST1 416
+#define DCLK_VICAP_CSIHOST2 417
+#define DCLK_VICAP_CSIHOST3 418
+#define ACLK_VI_ROOT_INTER 419
+#define ACLK_VOP_ROOT 420
+#define HCLK_VOP_ROOT 421
+#define PCLK_VOP_ROOT 422
+#define HCLK_VOP 423
+#define ACLK_VOP 424
+#define DCLK_VP0_SRC 425
+#define DCLK_VP1_SRC 426
+#define DCLK_VP0 427
+#define DCLK_VP1 428
+#define CLK_EBC_VOP_DCLK2DSIHOST_0 429
+#define PCLK_DSIHOST0 430
+#define ACLK_VO_ROOT 431
+#define HCLK_VO_ROOT 432
+#define PCLK_VO_ROOT 433
+#define PCLK_HDCP0_TRNG_NS 434
+#define ACLK_HDCP0 435
+#define HCLK_HDCP0 436
+#define PCLK_HDCP0 437
+#define CLK_TRNG0_SKP 438
+#define PCLK_HDMITX0 439
+#define CLK_HDMITX0_EARC 440
+#define CLK_HDMITX0_REF 441
+#define CLK_EXTREF_TIMEOUT_VO 442
+#define PCLK_EDP0 443
+#define CLK_EDP0_24M 444
+#define CLK_EDP0_200M 445
+#define MCLK_SAI4_SRC 446
+#define MCLK_SAI4 447
+#define HCLK_SAI4 448
+#define MCLK_SAI5_SRC 449
+#define MCLK_SAI5 450
+#define HCLK_SAI5 451
+#define HCLK_SPDIF_TX2 452
+#define MCLK_SPDIF_TX2_SRC 453
+#define MCLK_SPDIF_TX2 454
+#define HCLK_SPDIF_RX1 455
+#define MCLK_SPDIF_RX1 456
+#define CLK_EBC_VOP_DCLK2HDMITX 457
+#define CLK_EBC_VOP_DCLK2EDP 458
+#define CLK_EBC_VOP_DCLK_INTER 459
+#define CLK_SAI4_MCLKOUT 460
+#define CLK_GPU_SRC 461
+#define CLK_GPU 462
+#define CLK_GPU_COREGROUP 463
+#define CLK_GPU_STACKS 464
+#define PCLK_GPU_ROOT 465
+#define ACLK_CENTER_ROOT 466
+#define ACLK_CENTER_LOW_ROOT 467
+#define HCLK_CENTER_ROOT 468
+#define PCLK_CENTER_ROOT 469
+#define ACLK_DMA2DDR 470
+#define ACLK_DDR_SHAREMEM 471
+#define PCLK_DMA2DDR 472
+#define CLK_LINK_EDP0 473
+#define CLK_CHTXD_EDP0 474
+#define CLK_DIV2_EDP0 475
+#define CLK_VOP2HDCP0_PIX_CLK 476
+#define CLK_LINKSYM_HDMITXPHY0 477
+#define CLK_XGXS_TXDIV20 478
+#define CLK_XGXS_TX 479
+#define CLK_XGXS_RXDIV20 480
+#define CLK_XGXS_RX 481
+#define HCLK_SECURE_NS_ROOT 482
+#define PCLK_SECURE_NS_ROOT 483
+#define HCLK_CRYPTO_NS 484
+#define HCLK_TRNG_NS 485
+#define PCLK_OTPC_NS 486
+#define CLK_OTPC_NS 487
+#define CLK_REF_OSC_MPHY 488
+#define CLK_REF_UFS_CLKOUT 489
+#define HCLK_PMU1_ROOT 490
+#define HCLK_PMU_CM0_ROOT 491
+#define PCLK_APB2ASB_PMU1 492
+#define SCLK_APB2ASB_PMU1 493
+#define CLK_PMUMCU_CORE_AON 494
+#define CLK_MTIME_TOGGLE_A_PMU 495
+#define PCLK_PMU1_ROOT 496
+#define PCLK_PMU1 497
+#define CLK_PMU1 498
+#define PCLK_PMU1WDT 499
+#define TCLK_PMU1WDT 500
+#define PCLK_PMUTIMER 501
+#define CLK_PMUTIMER_ROOT 502
+#define CLK_PMUTIMER0 503
+#define CLK_PMUTIMER1 504
+#define PCLK_PWM0 505
+#define CLK_PWM0 506
+#define CLK_PWM0_OSC 507
+#define PCLK_PMUPHY_ROOT 508
+#define PCLK_I2C0 509
+#define CLK_I2C0 510
+#define SCLK_UART1 511
+#define PCLK_UART1 512
+#define CLK_PWM0_RC 513
+#define CLK_PDM0 514
+#define HCLK_PDM0 515
+#define MCLK_PDM0 516
+#define HCLK_VAD 517
+#define CLK_PDM0_OUT 518
+#define PCLK_PMU0_ROOT 519
+#define PCLK_PMU0 520
+#define PCLK_GPIO0 521
+#define DBCLK_GPIO0 522
+#define SCLK_APB2ASB_SRC 523
+#define CLK_32K 524
+#define ACLK_CRYPTO_NS 525
+#define CLK_PKA_CRYPTO_NS 526
+#define PCLK_DDR_MON 527
+
+/* Secure clocks */
+#define ACLK_CCI 600
+#define SCLK_DDR 601
+#define CLK_STIMER0_ROOT 602
+#define PCLK_SECURE_S 603
+#define HCLK_SECURE_S 604
+#define ACLK_SECURE_S 605
+#define CLK_PKA_CRYPTO_S 606
+#define PCLK_KLAD 607
+#define HCLK_CRYPTO_S 608
+#define HCLK_KLAD 609
+#define ACLK_CRYPTO_S 610
+#define PCLK_OTPC_S 611
+#define CLK_OTPC_S 612
+#define PCLK_WDT_S 613
+#define TCLK_WDT_S 614
+#define HCLK_TRNG_S 615
+
+#define CLK_NR_CLKS (HCLK_TRNG_S + 1)
+#endif
diff --git a/include/dt-bindings/reset/rockchip,rk3572-cru.h b/include/dt-bindings/reset/rockchip,rk3572-cru.h
new file mode 100644
index 000000000000..a78947532681
--- /dev/null
+++ b/include/dt-bindings/reset/rockchip,rk3572-cru.h
@@ -0,0 +1,713 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3572_H
+#define _DT_BINDINGS_RESET_ROCKCHIP_RK3572_H
+
+/* CRU-->SOFTRST_CON01 */
+#define SRST_ARESETN_TOP_BIU 0
+#define SRST_PRESETN_TOP_BIU 1
+#define SRST_ARESETN_TOP_MID_BIU 2
+#define SRST_HRESETN_TOP_BIU 3
+
+/* CRU-->SOFTRST_CON02 */
+#define SRST_HRESETN_TOP_FW 4
+
+/* CRU-->SOFTRST_CON06 */
+#define SRST_RESETN_TEST_JUDGE_24M_TOP 5
+#define SRST_RESETN_TEST_JUDGE_TOP 6
+
+/* CRU-->SOFTRST_CON07 */
+#define SRST_HRESETN_AUDIO_BIU 7
+#define SRST_HRESETN_ASRC_2CH_0 8
+#define SRST_HRESETN_ASRC_2CH_1 9
+#define SRST_RESETN_ASRC_2CH_0 10
+#define SRST_RESETN_ASRC_2CH_1 11
+#define SRST_MRESETN_SAI0 12
+#define SRST_HRESETN_SAI0 13
+#define SRST_HRESETN_SPDIF_RX0 14
+#define SRST_MRESETN_SPDIF_RX0 15
+
+/* CRU-->SOFTRST_CON08 */
+#define SRST_MRESETN_SAI1 16
+#define SRST_HRESETN_SAI1 17
+#define SRST_MRESETN_SAI2 18
+#define SRST_HRESETN_SAI2 19
+#define SRST_MRESETN_SAI3 20
+#define SRST_HRESETN_SAI3 21
+#define SRST_HRESETN_ACDCDIG_DSM 22
+
+/* CRU-->SOFTRST_CON09 */
+#define SRST_MRESETN_ACDCDIG_DSM 23
+#define SRST_PRESETN_AUDIO_BIU 24
+#define SRST_PRESETN_AUDIO_GRF 25
+#define SRST_HRESETN_SPDIF_TX0 26
+#define SRST_MRESETN_SPDIF_TX0 27
+#define SRST_HRESETN_SPDIF_TX1 28
+#define SRST_MRESETN_SPDIF_TX1 29
+#define SRST_RESETN_TEST_JUDGE_24M_AUDIO 30
+#define SRST_RESETN_TEST_JUDGE_AUDIO 31
+
+/* CRU-->SOFTRST_CON11 */
+#define SRST_ARESETN_BUS_BIU 32
+#define SRST_ARESETN_BUS_FW 33
+#define SRST_PRESETN_BUS_BIU 34
+#define SRST_PRESETN_CRU 35
+#define SRST_HRESETN_CAN0 36
+#define SRST_RESETN_CAN0 37
+#define SRST_HRESETN_CAN1 38
+#define SRST_RESETN_CAN1 39
+#define SRST_HRESETN_CAN2 40
+#define SRST_RESETN_CAN2 41
+#define SRST_HRESETN_CAN3 42
+#define SRST_RESETN_CAN3 43
+
+/* CRU-->SOFTRST_CON12 */
+#define SRST_ARESETN_DECOM_BIU 44
+#define SRST_HRESETN_BUS_BIU 45
+#define SRST_RESETN_KEY_SHIFT 46
+#define SRST_PRESETN_I2C1 47
+#define SRST_PRESETN_I2C2 48
+#define SRST_PRESETN_I2C3 49
+#define SRST_PRESETN_I2C4 50
+#define SRST_PRESETN_I2C5 51
+#define SRST_PRESETN_I2C6 52
+#define SRST_PRESETN_I2C7 53
+#define SRST_PRESETN_I2C8 54
+#define SRST_PRESETN_I2C9 55
+#define SRST_PRESETN_WDT_BUSMCU 56
+#define SRST_TRESETN_WDT_BUSMCU 57
+
+/* CRU-->SOFTRST_CON13 */
+#define SRST_ARESETN_GIC 58
+#define SRST_RESETN_I2C1 59
+#define SRST_RESETN_I2C2 60
+#define SRST_RESETN_I2C3 61
+#define SRST_RESETN_I2C4 62
+#define SRST_RESETN_I2C5 63
+#define SRST_RESETN_I2C6 64
+#define SRST_RESETN_I2C7 65
+#define SRST_RESETN_I2C8 66
+#define SRST_RESETN_I2C9 67
+#define SRST_PRESETN_SARADC 68
+
+/* CRU-->SOFTRST_CON14 */
+#define SRST_RESETN_SARADC 69
+#define SRST_RESETN_SARADC_32K 70
+#define SRST_PRESETN_TSADC 71
+#define SRST_RESETN_TSADC 72
+#define SRST_PRESETN_UART0 73
+#define SRST_PRESETN_UART2 74
+#define SRST_PRESETN_UART3 75
+#define SRST_PRESETN_UART4 76
+#define SRST_PRESETN_UART5 77
+#define SRST_PRESETN_UART6 78
+#define SRST_PRESETN_UART7 79
+#define SRST_PRESETN_UART8 80
+#define SRST_PRESETN_UART9 81
+#define SRST_PRESETN_UART10 82
+#define SRST_PRESETN_UART11 83
+#define SRST_SRESETN_UART0 84
+
+/* CRU-->SOFTRST_CON15 */
+#define SRST_SRESETN_UART2 85
+#define SRST_SRESETN_UART3 86
+#define SRST_SRESETN_UART4 87
+#define SRST_SRESETN_UART5 88
+#define SRST_SRESETN_UART6 89
+#define SRST_SRESETN_UART7 90
+
+/* CRU-->SOFTRST_CON16 */
+#define SRST_SRESETN_UART8 91
+#define SRST_SRESETN_UART9 92
+#define SRST_SRESETN_UART10 93
+#define SRST_SRESETN_UART11 94
+#define SRST_PRESETN_SPI0 95
+#define SRST_PRESETN_SPI1 96
+#define SRST_PRESETN_SPI2 97
+#define SRST_PRESETN_SPI3 98
+#define SRST_PRESETN_SPI4 99
+#define SRST_RESETN_SPI0 100
+#define SRST_RESETN_SPI1 101
+#define SRST_RESETN_SPI2 102
+#define SRST_RESETN_SPI3 103
+
+/* CRU-->SOFTRST_CON17 */
+#define SRST_RESETN_SPI4 104
+#define SRST_PRESETN_WDT0 105
+#define SRST_TRESETN_WDT0 106
+#define SRST_PRESETN_SYS_GRF 107
+#define SRST_PRESETN_PWM1 108
+#define SRST_RESETN_PWM1 109
+#define SRST_PRESETN_PWM2 110
+#define SRST_RESETN_PWM2 111
+
+/* CRU-->SOFTRST_CON18 */
+#define SRST_PRESETN_BUSTIMER0 112
+#define SRST_PRESETN_BUSTIMER1 113
+#define SRST_RESETN_TIMER0 114
+#define SRST_RESETN_TIMER1 115
+#define SRST_RESETN_TIMER2 116
+#define SRST_RESETN_TIMER3 117
+#define SRST_RESETN_TIMER4 118
+#define SRST_RESETN_TIMER5 119
+#define SRST_PRESETN_MAILBOX0 120
+
+/* CRU-->SOFTRST_CON19 */
+#define SRST_PRESETN_GPIO1 121
+#define SRST_DBRESETN_GPIO1 122
+#define SRST_PRESETN_GPIO2 123
+#define SRST_DBRESETN_GPIO2 124
+#define SRST_PRESETN_GPIO3 125
+#define SRST_DBRESETN_GPIO3 126
+#define SRST_PRESETN_GPIO4 127
+#define SRST_DBRESETN_GPIO4 128
+#define SRST_ARESETN_DECOM 129
+#define SRST_PRESETN_DECOM 130
+#define SRST_DRESETN_DECOM 131
+#define SRST_RESETN_TIMER6 132
+#define SRST_RESETN_TIMER7 133
+#define SRST_RESETN_TIMER8 134
+#define SRST_RESETN_TIMER9 135
+
+/* CRU-->SOFTRST_CON20 */
+#define SRST_RESETN_TIMER10 136
+#define SRST_RESETN_TIMER11 137
+#define SRST_ARESETN_RKDMA0 138
+#define SRST_PRESETN_RKDMA0 139
+#define SRST_ARESETN_RKDMA1 140
+#define SRST_PRESETN_RKDMA1 141
+#define SRST_ARESETN_RKDMA2 142
+#define SRST_PRESETN_RKDMA2 143
+#define SRST_ARESETN_RKDMA3 144
+#define SRST_PRESETN_RKDMA3 145
+#define SRST_PRESETN_SPINLOCK 146
+#define SRST_RESETN_REF_PVTPLL_BUS 147
+#define SRST_RESETN_I3C 148
+#define SRST_HRESETN_I3C 149
+
+/* CRU-->SOFTRST_CON21 */
+#define SRST_RESETN_BUSMCU_BIU 150
+#define SRST_CORERESETN_N320 151
+#define SRST_PORESETN_N320 152
+#define SRST_RESETN_MCU_AXI_INTEGRITY 153
+#define SRST_PRESETN_INTMUX2PMU 154
+#define SRST_PRESETN_INTMUX2DDR 155
+#define SRST_PRESETN_PVTPLL_BUS 156
+#define SRST_RESETN_HDMITXHPD 157
+
+/* CRU-->SOFTRST_CON22 */
+#define SRST_PRESETN_APB2ASB_HDMITX 158
+#define SRST_SRESETN_APB2ASB_HDMITX 159
+#define SRST_PRESETN_APB2ASB_MIPICSI 160
+#define SRST_SRESETN_APB2ASB_MIPICSI 161
+#define SRST_PRESETN_APB2ASB_VCCIO0_3 162
+#define SRST_SRESETN_APB2ASB_VCCIO0_3 163
+#define SRST_PRESETN_APB2ASB_VCCIO1_2_4 164
+#define SRST_SRESETN_APB2ASB_VCCIO1_2_4 165
+#define SRST_PRESETN_APB2ASB_VCCIO5_6 166
+#define SRST_SRESETN_APB2ASB_VCCIO5_6 167
+#define SRST_RESETN_TEST_JUDGE_24M_BUS 168
+#define SRST_RESETN_TEST_JUDGE_BUS 169
+
+/* CRU-->SOFTRST_CON23 */
+#define SRST_PRESETN_DDR_MON 170
+#define SRST_PRESETN_DDR_BIU 171
+#define SRST_PRESETN_DDR_UPCTL 172
+#define SRST_TMRESETN_DDR_MON 173
+#define SRST_ARESETN_DDR_BIU 174
+#define SRST_PRESETN_DDR_BIU_FW 175
+#define SRST_RESETN_DDR_MON 176
+#define SRST_PRESETN_DDR_HWLP 177
+
+/* CRU-->SOFTRST_CON24 */
+#define SRST_ARESETN_DDR_MSCH_BIU 178
+#define SRST_ARESETN_DDR_MSCH_FW 179
+#define SRST_RESETN_DDR_SCRAMBLE 180
+#define SRST_LRESETN_DDRSCH_BIU 181
+
+/* CRU-->SOFTRST_CON25 */
+#define SRST_RESETN_DDR_TIMER0 182
+#define SRST_RESETN_DDR_TIMER1 183
+#define SRST_TRESETN_DDR_WDT 184
+#define SRST_PRESETN_WDT 185
+#define SRST_PRESETN_TIMER 186
+#define SRST_PRESETN_DDR_GRF 187
+
+/* CRU-->SOFTRST_CON26 */
+#define SRST_RESETN_DDR_UPCTL 188
+#define SRST_ARESETN_DDR_UPCTL_0 189
+#define SRST_ARESETN_DDR_UPCTL_1 190
+#define SRST_ARESETN_DDR_UPCTL_2 191
+#define SRST_ARESETN_DDR_UPCTL_3 192
+#define SRST_ARESETN_DDR_UPCTL_4 193
+#define SRST_ARESETN_DDR_UPCTL_5 194
+
+/* CRU-->SOFTRST_CON27 */
+#define SRST_RESETN_DDRMCU_BIU 195
+#define SRST_CORERESETN_N320_DDR 196
+#define SRST_PORESETN_N320_DDR 197
+#define SRST_RESETN_TEST_JUDGE_24M_DDR 198
+#define SRST_RESETN_TEST_JUDGE_DDR 199
+
+/* CRU-->SOFTRST_CON31 */
+#define SRST_ARESETN_RKNN 200
+#define SRST_ARESETN_RKNN_RV 201
+#define SRST_ARESETN_RKNN_BIU 202
+#define SRST_ARESETN_RKNN_FW 203
+#define SRST_PRESETN_RKNN_BIU 204
+#define SRST_PRESETN_PVTPLL_NPU 205
+#define SRST_RESETN_NPU_PVTPLL 206
+#define SRST_RESETN_24M_RKNN 207
+#define SRST_RESETN_NPUTIMER0 208
+#define SRST_RESETN_NPUTIMER1 209
+#define SRST_PRESETN_NPU_TIMER 210
+
+/* CRU-->SOFTRST_CON32 */
+#define SRST_PRESETN_NPU_WDT 211
+#define SRST_TRESETN_NPU_WDT 212
+#define SRST_PRESETN_RKNN_GRF 213
+#define SRST_RESETN_TEST_JUDGE_24M_NPU 214
+#define SRST_RESETN_TEST_JUDGE_NPU 215
+
+/* CRU-->SOFTRST_CON33 */
+#define SRST_PRESETN_PHP0_GRF 216
+#define SRST_PRESETN_PHP0_BIU 217
+#define SRST_ARESETN_PHP0_BIU 218
+#define SRST_ARESETN_PHP0_FW 219
+#define SRST_PRESETN_PCIE1 220
+#define SRST_RESETN_PCIE1_POWER_UP 221
+#define SRST_RESETN_TEST_JUDGE_24M_PHP0 222
+#define SRST_RESETN_TEST_JUDGE_PHP0 223
+
+/* CRU-->SOFTRST_CON34 */
+#define SRST_PRESETN_PCIE0 224
+#define SRST_RESETN_PCIE0_POWER_UP 225
+#define SRST_ARESETN_USB3OTG1 226
+#define SRST_ARESETN_GMAC0 227
+#define SRST_ARESETN_USB3OTG0 228
+
+/* CRU-->SOFTRST_CON35 */
+#define SRST_ARESETN_UFS_BIU 229
+#define SRST_ARESETN_UFS_SYS 230
+#define SRST_ARESETN_UFS 231
+#define SRST_PRESETN_UFS_GRF 232
+
+/* CRU-->SOFTRST_CON37 */
+#define SRST_RESETN_RXOOB0 233
+#define SRST_RESETN_PMALIVE0 234
+#define SRST_ARESETN_SATA0 235
+#define SRST_RESETN_RXOOB1 236
+#define SRST_RESETN_PMALIVE1 237
+#define SRST_ARESETN_SATA1 238
+#define SRST_RESETN_XPCS_PWR_ON 239
+#define SRST_RESETN_ASIC0 240
+#define SRST_RESETN_ASIC1 241
+
+/* CRU-->SOFTRST_CON42 */
+#define SRST_PRESETN_NVM0_GRF 242
+#define SRST_PRESETN_NVM0_BIU 243
+#define SRST_ARESETN_NVM0_BIU 244
+#define SRST_HRESETN_NVM0_BIU 245
+#define SRST_CRESETN_EMMC 246
+#define SRST_HRESETN_EMMC 247
+#define SRST_ARESETN_EMMC 248
+#define SRST_BRESETN_EMMC 249
+#define SRST_TRESETN_EMMC 250
+#define SRST_ARESETN_GMAC1 251
+
+/* CRU-->SOFTRST_CON43 */
+#define SRST_SRESETN_FSPI0 252
+#define SRST_HRESETN_FSPI0 253
+#define SRST_HRESETN_SDMMC1 254
+#define SRST_RESETN_TEST_JUDGE_24M_NVM0 255
+#define SRST_RESETN_TEST_JUDGE_NVM0 256
+
+/* CRU-->SOFTRST_CON44 */
+#define SRST_ARESETN_DSMC_BIU 257
+#define SRST_ARESETN_DSMC 258
+#define SRST_HRESETN_DSMC_BIU 259
+#define SRST_HRESETN_DSMC 260
+#define SRST_PRESETN_DSMC_BIU 261
+#define SRST_PRESETN_DSMC 262
+#define SRST_RESETN_TEST_JUDGE_24M_DSMC 263
+#define SRST_RESETN_TEST_JUDGE_DSMC 264
+#define SRST_PRESETN_DSMC_GRF 265
+
+/* CRU-->SOFTRST_CON45 */
+#define SRST_PRESETN_NVM1_GRF 266
+#define SRST_PRESETN_NVM1_BIU 267
+#define SRST_HRESETN_NVM1_BIU 268
+#define SRST_HRESETN_SDMMC0 269
+#define SRST_SRESETN_FSPI1 270
+#define SRST_HRESETN_FSPI1 271
+
+/* CRU-->SOFTRST_CON46 */
+#define SRST_RESETN_TEST_JUDGE_24M_NVM1 272
+#define SRST_RESETN_TEST_JUDGE_NVM1 273
+
+/* CRU-->SOFTRST_CON50 */
+#define SRST_HRESETN_RKVDEC 274
+#define SRST_HRESETN_RKVDEC_BIU 275
+#define SRST_ARESETN_RKVDEC_BIU 276
+#define SRST_RESETN_RKVDEC_HEVC_CA 277
+#define SRST_RESETN_RKVDEC_CORE 278
+#define SRST_RESETN_TEST_JUDGE_24M_VDEC 279
+#define SRST_RESETN_TEST_JUDGE_VDEC 280
+#define SRST_PRESETN_VDEC_BIU 281
+#define SRST_PRESETN_VDEC_GRF 282
+
+/* CRU-->SOFTRST_CON52 */
+#define SRST_PRESETN_APB2ASB_MIPI_HDMI_SUBVO 283
+#define SRST_SRESETN_APB2ASB_MIPI_HDMI_SUBVO 284
+#define SRST_PRESETN_APB2ASB_VCCIO0_3_SUBVO 285
+#define SRST_SRESETN_APB2ASB_VCCIO0_3_SUBVO 286
+#define SRST_PRESETN_HDPTXPHY 287
+#define SRST_PRESETN_HDPTXPHY_GRF 288
+#define SRST_PRESETN_MIPI_DPHY0 289
+
+/* CRU-->SOFTRST_CON53 */
+#define SRST_RESETN_HDPTX_INIT 290
+#define SRST_RESETN_HDPTX_CMN 291
+#define SRST_RESETN_HDPTX_LANE 292
+#define SRST_PRESETN_IOC_SUBVO 293
+#define SRST_RESETN_GMAC1_SUBVO_ASYNC 294
+#define SRST_RESETN_TEST_JUDGE_24M_SUBSYSVO 295
+#define SRST_RESETN_TEST_JUDGE_SUBSYSVO 296
+
+/* CRU-->SOFTRST_CON54 */
+#define SRST_PRESETN_APB2ASB_VCCIO1_2_4_SUBVI 297
+#define SRST_SRESETN_APB2ASB_VCCIO1_2_4_SUBVI 298
+#define SRST_PRESETN_APB2ASB_CSIPHY_SUBVI 299
+#define SRST_SRESETN_APB2ASB_CSIPHY_SUBVI 300
+#define SRST_PRESETN_CSIPHY0 301
+#define SRST_PRESETN_CSIPHY0_GRF 302
+#define SRST_PRESETN_CSIPHY1 303
+#define SRST_PRESETN_CSIPHY1_GRF 304
+#define SRST_PRESETN_IOC_SUBVI 305
+#define SRST_RESETN_GMAC0_SUBVI_ASYNC 306
+#define SRST_SCAN_RESETN_CSIPHY0 307
+#define SRST_SCAN_RESETN_CSIPHY1 308
+#define SRST_RESETN_TEST_JUDGE_24M_SUBSYSVI 309
+#define SRST_RESETN_TEST_JUDGE_SUBSYSVI 310
+
+/* CRU-->SOFTRST_CON56 */
+#define SRST_PRESETN_APB2ASB_VCCIO5_6_SUBDSMC 311
+#define SRST_SRESETN_APB2ASB_VCCIO5_6_SUBDSMC 312
+#define SRST_PRESETN_VCCIO5_6 313
+#define SRST_RESETN_GMAC1_ASYNC 314
+
+/* CRU-->SOFTRST_CON57 */
+#define SRST_PRESETN_IMG_BIU 315
+#define SRST_PRESETN_IMG_GRF 316
+#define SRST_HRESETN_IMG_BIU 317
+#define SRST_ARESETN_JPEG_BIU 318
+#define SRST_RESETN_TEST_JUDGE_24M_IMG 319
+#define SRST_RESETN_TEST_JUDGE_IMG 320
+#define SRST_ARESETN_RGA_BIU 321
+#define SRST_ARESETN_VDPP_BIU 322
+#define SRST_ARESETN_EBC_BIU 323
+
+/* CRU-->SOFTRST_CON58 */
+#define SRST_HRESETN_RGA2E_0 324
+#define SRST_ARESETN_RGA2E_0 325
+#define SRST_RESETN_CORE_RGA2E_0 326
+#define SRST_ARESETN_JPEG 327
+#define SRST_HRESETN_JPEG 328
+#define SRST_HRESETN_VDPP 329
+#define SRST_ARESETN_VDPP 330
+#define SRST_RESETN_CORE_VDPP 331
+#define SRST_HRESETN_EBC 332
+#define SRST_ARESETN_EBC 333
+#define SRST_DRESETN_EBC 334
+
+/* CRU-->SOFTRST_CON60 */
+#define SRST_HRESETN_RKVENC_BIU 335
+#define SRST_ARESETN_RKVENC_BIU 336
+#define SRST_HRESETN_RKVENC 337
+#define SRST_ARESETN_RKVENC 338
+#define SRST_RESETN_RKVENC_CORE 339
+#define SRST_RESETN_TEST_JUDGE_24M_VENC 340
+#define SRST_RESETN_TEST_JUDGE_VENC 341
+
+/* CRU-->SOFTRST_CON63 */
+#define SRST_ARESETN_VI_BIU 342
+#define SRST_HRESETN_VI_BIU 343
+#define SRST_PRESETN_VI_BIU 344
+#define SRST_DRESETN_VICAP 345
+#define SRST_ARESETN_VICAP 346
+#define SRST_HRESETN_VICAP 347
+#define SRST_RESETN_ISP 348
+#define SRST_RESETN_ISP_VICAP 349
+
+/* CRU-->SOFTRST_CON64 */
+#define SRST_RESETN_CORE_VPSS 350
+#define SRST_PRESETN_VI_GRF 351
+#define SRST_PRESETN_CSI_HOST_0 352
+#define SRST_PRESETN_CSI_HOST_1 353
+#define SRST_PRESETN_CSI_HOST_2 354
+#define SRST_PRESETN_CSI_HOST_3 355
+#define SRST_RESETN_TEST_JUDGE_24M_VI 356
+#define SRST_RESETN_TEST_JUDGE_VI 357
+
+/* CRU-->SOFTRST_CON72 */
+#define SRST_RESETN_CIFIN 358
+
+/* CRU-->SOFTRST_CON74 */
+#define SRST_ARESETN_VOP_BIU 359
+#define SRST_ARESETN_VOP_FW 360
+#define SRST_HRESETN_VOP_BIU 361
+#define SRST_PRESETN_VOP_BIU 362
+#define SRST_HRESETN_VOP 363
+#define SRST_ARESETN_VOP 364
+#define SRST_DRESETN_VP0 365
+
+/* CRU-->SOFTRST_CON75 */
+#define SRST_DRESETN_VP1 366
+#define SRST_PRESETN_VOPGRF 367
+#define SRST_RESETN_TEST_JUDGE_24M_VOP 368
+#define SRST_RESETN_TEST_JUDGE_VOP 369
+
+/* CRU-->SOFTRST_CON78 */
+#define SRST_PRESETN_DSIHOST0 370
+#define SRST_HRESETN_VO_BIU 371
+#define SRST_PRESETN_VO_BIU 372
+#define SRST_ARESETN_HDCP0_BIU 373
+#define SRST_PRESETN_VO_GRF 374
+
+/* CRU-->SOFTRST_CON79 */
+#define SRST_PRESETN_HDCP0_TRNG_NS 375
+#define SRST_ARESETN_HDCP0 376
+#define SRST_HRESETN_HDCP0 377
+#define SRST_RESETN_HDCP0 378
+#define SRST_PRESETN_HDMITX0 379
+#define SRST_RESETN_HDMITX0_EARC 380
+
+/* CRU-->SOFTRST_CON80 */
+#define SRST_RESETN_HDMITX0_REF 381
+#define SRST_PRESETN_EDP0 382
+#define SRST_RESETN_EDP0_24M 383
+#define SRST_MRESETN_SAI4 384
+#define SRST_HRESETN_SAI4 385
+#define SRST_MRESETN_SAI5 386
+#define SRST_HRESETN_SAI5 387
+#define SRST_HRESETN_SPDIF_TX2 388
+#define SRST_MRESETN_SPDIF_TX2 389
+#define SRST_HRESETN_SPDIF_RX1 390
+#define SRST_MRESETN_SPDIF_RX1 391
+
+/* CRU-->SOFTRST_CON81 */
+#define SRST_RESETN_EBC_VOP_DCLK_VO 392
+
+/* CRU-->SOFTRST_CON82 */
+#define SRST_RESETN_TEST_JUDGE_24M_VO 393
+#define SRST_RESETN_TEST_JUDGE_VO 394
+
+/* CRU-->SOFTRST_CON84 */
+#define SRST_RESETN_GPU 395
+#define SRST_SYSRESETN_GPU 396
+#define SRST_PRESETN_GPU_BIU 397
+#define SRST_PORESETN_GPU_JTAG 398
+#define SRST_PRESETN_GPU_GRF 399
+#define SRST_RESETN_GPU_PVTPLL 400
+#define SRST_PRESETN_PVTPLL_GPU 401
+#define SRST_ARESETN_SLV_GPU_BIU 402
+
+/* CRU-->SOFTRST_CON85 */
+#define SRST_ARESETN_GPU_BIU 403
+#define SRST_RESETN_TEST_JUDGE_24M_GPU 404
+#define SRST_RESETN_TEST_JUDGE_GPU 405
+
+/* CRU-->SOFTRST_CON86 */
+#define SRST_ARESETN_CENTER_BIU 406
+#define SRST_ARESETN_CENTER_FW_DDR 407
+#define SRST_ARESETN_CENTER_FW_GPU 408
+#define SRST_ARESETN_DMA2DDR 409
+#define SRST_ARESETN_DDR_SHAREMEM 410
+#define SRST_ARESETN_DDR_SHAREMEM_BIU 411
+#define SRST_ARESETN_DDR_SHAREMEM_FW 412
+#define SRST_HRESETN_CENTER_BIU 413
+#define SRST_HRESETN_CENTER_FW 414
+#define SRST_PRESETN_CENTER_GRF 415
+#define SRST_PRESETN_DMA2DDR 416
+
+/* CRU-->SOFTRST_CON87 */
+#define SRST_PRESETN_CENTER_BIU 417
+#define SRST_RESETN_TEST_JUDGE_24M_CENTER 418
+#define SRST_RESETN_TEST_JUDGE_CENTER 419
+#define SRST_RESETN_LINKSYM_HDMITXPHY0 420
+
+/* PHPPHY_CRU-->SOFTRST_CON00 */
+#define SRST_PRESETN_PHPPHY_CRU 422
+#define SRST_PRESETN_PCIE2_COMBOPHY0 423
+#define SRST_PRESETN_PCIE2_COMBOPHY0_GRF 424
+#define SRST_PRESETN_PCIE2_COMBOPHY1 425
+#define SRST_PRESETN_PCIE2_COMBOPHY1_GRF 426
+#define SRST_PRESETN_USBPHY_GRF_0 427
+#define SRST_PRESETN_USBPHY_GRF_1 428
+#define SRST_RESETN_MPHY_INIT 429
+#define SRST_PRESETN_MPHY_GRF 430
+#define SRST_PRESETN_VCCIO7_IOC 431
+#define SRST_RESETN_USB2DEBUG 432
+#define SRST_PRESETN_PCIEPHY2 433
+#define SRST_PRESETN_PCIEPHY2_GRF 434
+
+/* PHPPHY_CRU-->SOFTRST_CON01 */
+#define SRST_SRESETN_APB2ASB_USBMPHY_PHPPHY 435
+#define SRST_PRESETN_APB2ASB_USBMPHY_PHPPHY 436
+#define SRST_RESETN_OTGPHY_0 437
+#define SRST_RESETN_OTGPHY_1 438
+#define SRST_RESETN_TEST_JUDGE_24M_PHPPHY 439
+#define SRST_RESETN_TEST_JUDGE_PHPPHY 440
+
+/* PHPPHY_CRU-->SOFTRST_CON02 */
+#define SRST_RESETN_PCIEPHY2 441
+#define SRST_RESETN_PCIE0_PIPE_PHY 442
+#define SRST_RESETN_PCIE1_PIPE_PHY 443
+
+/* SECURE_CRU-->SOFTRST_CON00 */
+#define SRST_HRESETN_CRYPTO_NS 444
+#define SRST_HRESETN_TRNG_NS 445
+#define SRST_PRESETN_SECURE_NS_BIU 446
+#define SRST_ARESETN_SECURE_HIGH_BIU 447
+#define SRST_HRESETN_SECURE_NS_BIU 448
+#define SRST_PRESETN_OTPC_NS 449
+#define SRST_RESETN_OTPC_NS 450
+
+/* PMU1_CRU-->SOFTRST_CON03 */
+#define SRST_PRESETN_APB2ASB_PMU1 451
+#define SRST_SRESETN_APB2ASB_PMU1 452
+#define SRST_HRESETN_PMU1_BIU 453
+#define SRST_HRESETN_PMU1_FW 454
+#define SRST_PRESETN_PMU1_BIU 455
+#define SRST_HRESETN_PMU_CM0_BIU 456
+#define SRST_CORERESETN_N100 457
+#define SRST_PORESETN_N100 458
+
+/* PMU1_CRU-->SOFTRST_CON04 */
+#define SRST_PRESETN_CRU_PMU1 459
+#define SRST_PRESETN_PMU1_GRF 460
+#define SRST_PRESETN_PMU1_IOC 461
+#define SRST_PRESETN_PMU1WDT 462
+#define SRST_TRESETN_PMU1WDT 463
+#define SRST_PRESETN_PMUTIMER 464
+#define SRST_RESETN_PMUTIMER0 465
+#define SRST_RESETN_PMUTIMER1 466
+#define SRST_PRESETN_PWM0 467
+#define SRST_RESETN_PWM0 468
+
+/* PMU1_CRU-->SOFTRST_CON05 */
+#define SRST_PRESETN_I2C0 469
+#define SRST_RESETN_I2C0 470
+#define SRST_SRESETN_UART1 471
+#define SRST_PRESETN_UART1 472
+#define SRST_RESETN_TEST_JUDGE_24M_PMU1 473
+#define SRST_RESETN_TEST_JUDGE_PMU1 474
+#define SRST_RESETN_PDM0 475
+
+/* PMU1_CRU-->SOFTRST_CON06 */
+#define SRST_HRESETN_PDM0 476
+#define SRST_MRESETN_PDM0 477
+#define SRST_HRESETN_VAD 478
+#define SRST_PRESETN_RCOSC 479
+#define SRST_RESETN_RCOSC 480
+
+/* PMU1_CRU-->SOFTRST_CON07 */
+#define SRST_PRESETN_PMU0GRF 481
+#define SRST_PRESETN_PMU0IOC 482
+#define SRST_PRESETN_GPIO0 483
+#define SRST_DBRESETN_GPIO0 484
+
+/* DDR0_CRU-->SOFTRST_CON00 */
+#define SRST_RESETN_DDRPHY1X 485
+
+/* DDR0_CRU-->SOFTRST_CON01 */
+#define SRST_PRESETN_DDRPHY_CRU 486
+#define SRST_PRESETN_DDRPHY 487
+
+/* BIGCORE_CRU-->SOFTRST_CON00 */
+#define SRST_RESETN_REF_PVTPLL_BIGCORE 488
+#define SRST_PRESETN_BIGCORE_BIU 489
+#define SRST_PRESETN_BIGCORE_GRF 490
+#define SRST_PRESETN_BIGCORE_CRU 491
+#define SRST_PRESETN_PVTPLL_BIGCORE 492
+#define SRST_NBIGCOREPORESET0 493
+#define SRST_NBIGCOREPORESET1 494
+#define SRST_NBIGCORESET0 495
+#define SRST_NBIGCORESET1 496
+
+/* BIGCORE_CRU-->SOFTRST_CON01 */
+#define SRST_NL2RESET_BIGCORE 497
+#define SRST_ARESETN_ADB400_A73_ACE 498
+#define SRST_RESETN_TEST_JUDGE_24M_BIGCORE 499
+#define SRST_RESETN_TEST_JUDGE_BIGCORE 500
+#define SRST_PRESETN_DBG_BIGCORE 501
+
+/* LITCORE0_CRU-->SOFTRST_CON00 */
+#define SRST_RESETN_REF_LITCORE0_PVTPLL 502
+#define SRST_NLITCOREPORESET0 503
+#define SRST_NLITCOREPORESET1 504
+#define SRST_NLITCOREPORESET2 505
+#define SRST_NLITCOREPORESET3 506
+#define SRST_NLITCORESET0 507
+#define SRST_NLITCORESET1 508
+#define SRST_NLITCORESET2 509
+#define SRST_NLITCORESET3 510
+#define SRST_NL2RESET_LITCORE0 511
+#define SRST_PRESETN_DBG_LITCORE0 512
+#define SRST_ARESETN_ADB400_A53_ACE_LITCORE0 513
+
+/* LITCORE0_CRU-->SOFTRST_CON01 */
+#define SRST_PRESETN_LITCORE0_GRF 514
+#define SRST_PRESETN_LITCORE0_BIU 515
+#define SRST_PRESETN_PVTPLL_LITCORE0 516
+#define SRST_PRESETN_LITCORE0_CRU 517
+#define SRST_RESETN_TEST_JUDGE_24M_LITCORE0 518
+#define SRST_RESETN_TEST_JUDGE_LITCORE0 519
+
+/* LITCORE1_CRU-->SOFTRST_CON00 */
+#define SRST_RESETN_REF_LITCORE1_PVTPLL 520
+#define SRST_NLITCOREPORESET4 521
+#define SRST_NLITCOREPORESET5 522
+#define SRST_NLITCORESET4 523
+#define SRST_NLITCORESET5 524
+#define SRST_NL2RESET_LITCORE1 525
+#define SRST_PRESETN_DBG_LITCORE1 526
+#define SRST_ARESETN_ADB400_A53_ACE_LITCORE1 527
+#define SRST_PRESETN_LITCORE1_GRF 528
+#define SRST_PRESETN_LITCORE1_BIU 529
+
+/* LITCORE1_CRU-->SOFTRST_CON01 */
+#define SRST_PRESETN_PVTPLL_LITCORE1 530
+#define SRST_PRESETN_LITCORE1_CRU 531
+#define SRST_RESETN_TEST_JUDGE_24M_LITCORE1 532
+#define SRST_RESETN_TEST_JUDGE_LITCORE1 533
+
+/* CCI_CRU-->SOFTRST_CON01 */
+#define SRST_RESETN_TEST_JUDGE_24M_CCI 534
+#define SRST_RESETN_TEST_JUDGE_CCI 535
+#define SRST_ARESETN_CPE 536
+#define SRST_PRESETN_CCI_BIU 537
+#define SRST_PRESETN_CCI_FW 538
+#define SRST_ARESETN_CCI_BIU 539
+#define SRST_ARESETN_CCI_FW 540
+
+/* CCI_CRU-->SOFTRST_CON02 */
+#define SRST_PRESETN_DBG_SYS 541
+#define SRST_PRESETN_CCI_GRF 542
+#define SRST_PRESETN_CCI_CRU 543
+#define SRST_ARESETN_CCI 544
+#define SRST_PORESETN_JTAG 545
+#define SRST_PRESETN_DBG_M 546
+#define SRST_ARESETN_ADB400_CCI_A73 547
+#define SRST_ARESETN_ADB400_CCI_A53_0 548
+#define SRST_ARESETN_ADB400_CCI_A53_1 549
+#define SRST_PRESETN_PVTPLL_CCI 550
+#define SRST_PRESETN_CCI_SPINLOCK 551
+#define SRST_PRESETN_DBG_M_BIU 552
+#define SRST_RESETN_REF_CCI_PVTPLL 553
+
+#endif
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 02/27] dt-bindings: power: rockchip: Add RK3572 power domains
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
2026-10-21 16:10 ` [PATCH 01/27] dt-bindings: clock: rockchip: Add RK3572 CRU Cunhao Lu via B4 Relay
@ 2026-10-21 16:10 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 03/27] dt-bindings: soc: rockchip: Add RK3572 PMU and GRF Cunhao Lu via B4 Relay
` (25 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:10 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Define the RK3572 power-domain IDs and require the system GRF used to
check firewall status.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
.../bindings/power/rockchip,power-controller.yaml | 17 ++++++++++++
.../power/rockchip,rk3572-power-controller.h | 30 ++++++++++++++++++++++
2 files changed, 47 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
index b41db576f95de..f8afb0fabe809 100644
--- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
@@ -43,6 +43,7 @@ properties:
- rockchip,rk3528-power-controller
- rockchip,rk3562-power-controller
- rockchip,rk3568-power-controller
+ - rockchip,rk3572-power-controller
- rockchip,rk3576-power-controller
- rockchip,rk3588-power-controller
- rockchip,rv1126-power-controller
@@ -57,6 +58,22 @@ properties:
"#size-cells":
const: 0
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: System GRF with firewall readiness status.
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ const: rockchip,rk3572-power-controller
+ then:
+ required:
+ - rockchip,grf
+ else:
+ properties:
+ rockchip,grf: false
+
required:
- compatible
- "#power-domain-cells"
diff --git a/include/dt-bindings/power/rockchip,rk3572-power-controller.h b/include/dt-bindings/power/rockchip,rk3572-power-controller.h
new file mode 100644
index 0000000000000..c2316fa859df9
--- /dev/null
+++ b/include/dt-bindings/power/rockchip,rk3572-power-controller.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2026 Rockchip Electronics Co., Ltd.
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#ifndef __DT_BINDINGS_POWER_RK3572_POWER_CONTROLLER_H__
+#define __DT_BINDINGS_POWER_RK3572_POWER_CONTROLLER_H__
+
+/* VD_NPU */
+#define RK3572_PD_NPU 0
+
+/* VD_GPU */
+#define RK3572_PD_GPU 1
+
+/* VD_LOGIC */
+#define RK3572_PD_NVM0 2
+#define RK3572_PD_NVM1 3
+#define RK3572_PD_DSMC 4
+#define RK3572_PD_PHP 5
+#define RK3572_PD_AUDIO 6
+#define RK3572_PD_IMG 7
+#define RK3572_PD_VDEC 8
+#define RK3572_PD_VI 9
+#define RK3572_PD_VENC 10
+#define RK3572_PD_VO 11
+#define RK3572_PD_VOP 12
+#define RK3572_PD_VOP_PRE 13
+
+#endif
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 03/27] dt-bindings: soc: rockchip: Add RK3572 PMU and GRF
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
2026-10-21 16:10 ` [PATCH 01/27] dt-bindings: clock: rockchip: Add RK3572 CRU Cunhao Lu via B4 Relay
2026-10-21 16:10 ` [PATCH 02/27] dt-bindings: power: rockchip: Add RK3572 power domains Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 04/27] dt-bindings: mfd: syscon: Add RK3572 QoS register compatible Cunhao Lu via B4 Relay
` (24 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
The RK3572 PMU and GRF blocks are system controllers shared with the
clock, power-domain, and USB PHY drivers.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
Documentation/devicetree/bindings/arm/rockchip/pmu.yaml | 2 ++
Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 12 ++++++++++++
2 files changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml
index 1cff2328cd01..43dcaa77ffdb 100644
--- a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml
@@ -28,6 +28,7 @@ select:
- rockchip,rk3528-pmu
- rockchip,rk3562-pmu
- rockchip,rk3568-pmu
+ - rockchip,rk3572-pmu
- rockchip,rk3576-pmu
- rockchip,rk3588-pmu
- rockchip,rv1126-pmu
@@ -48,6 +49,7 @@ properties:
- rockchip,rk3528-pmu
- rockchip,rk3562-pmu
- rockchip,rk3568-pmu
+ - rockchip,rk3572-pmu
- rockchip,rk3576-pmu
- rockchip,rk3588-pmu
- rockchip,rv1126-pmu
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index 7bcb4e2f47ec..3c4e7d1e9a07 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -30,6 +30,12 @@ properties:
- rockchip,rk3568-pipe-grf
- rockchip,rk3568-pipe-phy-grf
- rockchip,rk3568-usb2phy-grf
+ - rockchip,rk3572-ioc-grf
+ - rockchip,rk3572-nvm0-grf
+ - rockchip,rk3572-php-grf
+ - rockchip,rk3572-pipe-phy-grf
+ - rockchip,rk3572-pmu0-grf
+ - rockchip,rk3572-sys-grf
- rockchip,rk3576-bigcore-grf
- rockchip,rk3576-cci-grf
- rockchip,rk3576-dcphy-grf
@@ -95,6 +101,7 @@ properties:
- rockchip,rk3562-pmu-grf
- rockchip,rk3568-grf
- rockchip,rk3568-pmugrf
+ - rockchip,rk3572-usb2phy-grf
- rockchip,rk3576-ioc-grf
- rockchip,rk3576-pmu0-grf
- rockchip,rk3576-usb2phy-grf
@@ -258,6 +265,7 @@ allOf:
- rockchip,rk3308-usb2phy-grf
- rockchip,rk3328-usb2phy-grf
- rockchip,rk3399-grf
+ - rockchip,rk3572-usb2phy-grf
- rockchip,rk3576-usb2phy-grf
- rockchip,rk3588-usb2phy-grf
- rockchip,rv1108-grf
@@ -309,6 +317,10 @@ allOf:
compatible:
contains:
enum:
+ - rockchip,rk3572-nvm0-grf
+ - rockchip,rk3572-php-grf
+ - rockchip,rk3572-pipe-phy-grf
+ - rockchip,rk3572-usb2phy-grf
- rockchip,rk3576-dcphy-grf
- rockchip,rk3576-vo1-grf
- rockchip,rk3588-vo-grf
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 04/27] dt-bindings: mfd: syscon: Add RK3572 QoS register compatible
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (2 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 03/27] dt-bindings: soc: rockchip: Add RK3572 PMU and GRF Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 05/27] dt-bindings: pinctrl: rockchip: Add RK3572 Cunhao Lu via B4 Relay
` (23 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Add rockchip,rk3572-qos to the syscon compatible list.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index 945a168b613d..b3c96e1de74f 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -118,6 +118,7 @@ properties:
- rockchip,rk3528-qos
- rockchip,rk3562-qos
- rockchip,rk3568-qos
+ - rockchip,rk3572-qos
- rockchip,rk3576-qos
- rockchip,rk3588-qos
- rockchip,rv1126-qos
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 05/27] dt-bindings: pinctrl: rockchip: Add RK3572
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (3 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 04/27] dt-bindings: mfd: syscon: Add RK3572 QoS register compatible Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 06/27] dt-bindings: gpio: rockchip: Add RK3572 GPIO banks Cunhao Lu via B4 Relay
` (22 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Add the RK3572 pinctrl compatible.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
index 81747bb53056..cbecabd8e307 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
@@ -48,6 +48,7 @@ properties:
- rockchip,rk3528-pinctrl
- rockchip,rk3562-pinctrl
- rockchip,rk3568-pinctrl
+ - rockchip,rk3572-pinctrl
- rockchip,rk3576-pinctrl
- rockchip,rk3588-pinctrl
- rockchip,rv1103b-pinctrl
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 06/27] dt-bindings: gpio: rockchip: Add RK3572 GPIO banks
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (4 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 05/27] dt-bindings: pinctrl: rockchip: Add RK3572 Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 07/27] clk: rockchip: Add RK3572 clock and reset support Cunhao Lu via B4 Relay
` (21 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
RK3572 GPIO banks have four parent interrupts and a separate debounce
clock.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
.../bindings/gpio/rockchip,gpio-bank.yaml | 24 +++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml b/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
index 774e9c7de606..8655854ac0a3 100644
--- a/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
+++ b/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
@@ -14,12 +14,14 @@ properties:
enum:
- rockchip,gpio-bank
- rockchip,rk3188-gpio-bank0
+ - rockchip,rk3572-gpio-bank
reg:
maxItems: 1
interrupts:
- maxItems: 1
+ minItems: 1
+ maxItems: 4
clocks:
minItems: 1
@@ -51,6 +53,26 @@ properties:
of this bank, on SoCs such as the RV1106 where each GPIO bank has
its own IOC block.
+allOf:
+ - if:
+ properties:
+ compatible:
+ const: rockchip,rk3572-gpio-bank
+ then:
+ properties:
+ interrupts:
+ items:
+ - description: GPIO group 0
+ - description: GPIO group 1
+ - description: GPIO group 2
+ - description: GPIO group 3
+ clocks:
+ minItems: 2
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+
patternProperties:
"^.+-hog(-[0-9]+)?$":
type: object
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 07/27] clk: rockchip: Add RK3572 clock and reset support
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (5 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 06/27] dt-bindings: gpio: rockchip: Add RK3572 GPIO banks Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 22:26 ` Heiko Stübner
2026-10-21 16:11 ` [PATCH 08/27] pinctrl: rockchip: Add RK3572 support Cunhao Lu via B4 Relay
` (20 subsequent siblings)
27 siblings, 1 reply; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
CPU clocks are managed by SCMI. Keep BPLL and LPLL enabled for firmware
consumers.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
drivers/clk/rockchip/Kconfig | 7 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-rk3572.c | 1972 +++++++++++++++++++++++++++++++++++++
drivers/clk/rockchip/clk.h | 36 +
drivers/clk/rockchip/rst-rk3572.c | 739 ++++++++++++++
5 files changed, 2755 insertions(+)
diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
index 4b55f48d72c2..8efd54fd295d 100644
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@@ -142,6 +142,13 @@ config CLK_RK3568
help
Build the driver for RK3568 Clock Driver.
+config CLK_RK3572
+ bool "Rockchip RK3572 clock controller support"
+ depends on ARM64 || COMPILE_TEST
+ default y
+ help
+ Build the driver for RK3572 Clock Driver.
+
config CLK_RK3576
bool "Rockchip RK3576 clock controller support"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 554b7eb83dc9..d6a194f7ea2b 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -36,5 +36,6 @@ obj-$(CONFIG_CLK_RK3506) += clk-rk3506.o rst-rk3506.o
obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o rst-rk3528.o
obj-$(CONFIG_CLK_RK3562) += clk-rk3562.o rst-rk3562.o
obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
+obj-$(CONFIG_CLK_RK3572) += clk-rk3572.o rst-rk3572.o
obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o
obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o
diff --git a/drivers/clk/rockchip/clk-rk3572.c b/drivers/clk/rockchip/clk-rk3572.c
new file mode 100644
index 000000000000..78fd35f5f27d
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3572.c
@@ -0,0 +1,1972 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <dt-bindings/clock/rockchip,rk3572-cru.h>
+#include "clk.h"
+
+#define COMPOSITE_MUXTBL(_id, cname, pnames, num, f, mo, ms, mw, mf, \
+ mt, ds, dw, df, go, gs, gf) \
+ { \
+ .id = _id, \
+ .branch_type = branch_composite, \
+ .name = cname, \
+ .parent_names = pnames, \
+ .num_parents = num, \
+ .flags = f, \
+ .muxdiv_offset = mo, \
+ .mux_shift = ms, \
+ .mux_width = mw, \
+ .mux_flags = mf, \
+ .mux_table = mt, \
+ .div_shift = ds, \
+ .div_width = dw, \
+ .div_flags = df, \
+ .gate_offset = go, \
+ .gate_shift = gs, \
+ .gate_flags = gf, \
+ }
+
+#define RK3572_GRF_SOC_STATUS0 0x600
+#define RK3572_PMU0_GRF_OSC_CON6 0x18
+
+enum rk3572_plls {
+ bpll, lpll, vpll, aupll, cpll, gpll, ppll,
+};
+
+static struct rockchip_pll_rate_table rk3572_pll_rates[] = {
+ /* _mhz, _p, _m, _s, _k */
+ RK3588_PLL_RATE(2520000000, 2, 210, 0, 0),
+ RK3588_PLL_RATE(2496000000, 2, 208, 0, 0),
+ RK3588_PLL_RATE(2472000000, 2, 206, 0, 0),
+ RK3588_PLL_RATE(2448000000, 2, 204, 0, 0),
+ RK3588_PLL_RATE(2424000000, 2, 202, 0, 0),
+ RK3588_PLL_RATE(2400000000, 2, 200, 0, 0),
+ RK3588_PLL_RATE(2376000000, 2, 198, 0, 0),
+ RK3588_PLL_RATE(2352000000, 2, 196, 0, 0),
+ RK3588_PLL_RATE(2328000000, 2, 194, 0, 0),
+ RK3588_PLL_RATE(2304000000, 2, 192, 0, 0),
+ RK3588_PLL_RATE(2280000000, 2, 190, 0, 0),
+ RK3588_PLL_RATE(2256000000, 2, 376, 1, 0),
+ RK3588_PLL_RATE(2232000000, 2, 372, 1, 0),
+ RK3588_PLL_RATE(2208000000, 2, 368, 1, 0),
+ RK3588_PLL_RATE(2184000000, 2, 364, 1, 0),
+ RK3588_PLL_RATE(2160000000, 2, 360, 1, 0),
+ RK3588_PLL_RATE(2136000000, 2, 356, 1, 0),
+ RK3588_PLL_RATE(2112000000, 2, 352, 1, 0),
+ RK3588_PLL_RATE(2088000000, 2, 348, 1, 0),
+ RK3588_PLL_RATE(2064000000, 2, 344, 1, 0),
+ RK3588_PLL_RATE(2040000000, 2, 340, 1, 0),
+ RK3588_PLL_RATE(2016000000, 2, 336, 1, 0),
+ RK3588_PLL_RATE(1992000000, 2, 332, 1, 0),
+ RK3588_PLL_RATE(1968000000, 2, 328, 1, 0),
+ RK3588_PLL_RATE(1944000000, 2, 324, 1, 0),
+ RK3588_PLL_RATE(1920000000, 2, 320, 1, 0),
+ RK3588_PLL_RATE(1896000000, 2, 316, 1, 0),
+ RK3588_PLL_RATE(1872000000, 2, 312, 1, 0),
+ RK3588_PLL_RATE(1848000000, 2, 308, 1, 0),
+ RK3588_PLL_RATE(1824000000, 2, 304, 1, 0),
+ RK3588_PLL_RATE(1800000000, 2, 300, 1, 0),
+ RK3588_PLL_RATE(1776000000, 2, 296, 1, 0),
+ RK3588_PLL_RATE(1752000000, 2, 292, 1, 0),
+ RK3588_PLL_RATE(1728000000, 2, 288, 1, 0),
+ RK3588_PLL_RATE(1704000000, 2, 284, 1, 0),
+ RK3588_PLL_RATE(1680000000, 2, 280, 1, 0),
+ RK3588_PLL_RATE(1656000000, 2, 276, 1, 0),
+ RK3588_PLL_RATE(1632000000, 2, 272, 1, 0),
+ RK3588_PLL_RATE(1608000000, 2, 268, 1, 0),
+ RK3588_PLL_RATE(1584000000, 2, 264, 1, 0),
+ RK3588_PLL_RATE(1560000000, 2, 260, 1, 0),
+ RK3588_PLL_RATE(1536000000, 2, 256, 1, 0),
+ RK3588_PLL_RATE(1512000000, 2, 252, 1, 0),
+ RK3588_PLL_RATE(1488000000, 2, 248, 1, 0),
+ RK3588_PLL_RATE(1464000000, 2, 244, 1, 0),
+ RK3588_PLL_RATE(1440000000, 2, 240, 1, 0),
+ RK3588_PLL_RATE(1416000000, 2, 236, 1, 0),
+ RK3588_PLL_RATE(1392000000, 2, 232, 1, 0),
+ RK3588_PLL_RATE(1320000000, 2, 220, 1, 0),
+ RK3588_PLL_RATE(1200000000, 2, 200, 1, 0),
+ RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),
+ RK3588_PLL_RATE(1186814000, 2, 198, 1, 52581),
+ RK3588_PLL_RATE(1186812000, 2, 198, 1, 52559),
+ RK3588_PLL_RATE(1109000000, 3, 554, 2, 32767),
+ RK3588_PLL_RATE(1100000000, 3, 550, 2, 0),
+ RK3588_PLL_RATE(1051000000, 3, 525, 2, 32767),
+ RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
+ RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
+ RK3588_PLL_RATE(983040000, 4, 655, 2, 23592),
+ RK3588_PLL_RATE(955520000, 3, 478, 2, -15730),
+ RK3588_PLL_RATE(903168000, 6, 903, 2, 11009),
+ RK3588_PLL_RATE(900000000, 2, 300, 2, 0),
+ RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
+ RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
+ RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
+ RK3588_PLL_RATE(785560000, 3, 393, 2, -14419),
+ RK3588_PLL_RATE(773000000, 2, 258, 2, 43690),
+ RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
+ RK3588_PLL_RATE(697000000, 2, 232, 2, 21845),
+ RK3588_PLL_RATE(610400000, 3, 305, 2, 13107),
+ RK3588_PLL_RATE(604800000, 1, 101, 2, 52428),
+ RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
+ RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
+ RK3588_PLL_RATE(408000000, 2, 272, 3, 0),
+ RK3588_PLL_RATE(312000000, 2, 208, 3, 0),
+ RK3588_PLL_RATE(266580000, 1, 178, 4, 47185),
+ RK3588_PLL_RATE(216000000, 2, 288, 4, 0),
+ RK3588_PLL_RATE(96000000, 2, 256, 5, 0),
+ { /* sentinel */ },
+};
+
+static struct rockchip_pll_rate_table rk3572_ppll_rates[] = {
+ /* _mhz, _p, _m, _s, _k */
+ RK3588_PLL_RATE(1300000000, 3, 325, 2, 0),
+ { /* sentinel */ },
+};
+
+static struct rockchip_pll_rate_table rk3572_aupll_rates[] = {
+ RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
+ { /* sentinel */ },
+};
+
+#define RK3572_ACLK_M_BIGCORE_DIV_MASK 0x1f
+#define RK3572_ACLK_M_BIGCORE_DIV_SHIFT 9
+#define RK3572_PCLK_DBG_BIGCORE_DIV_MASK 0x1f
+#define RK3572_PCLK_DBG_BIGCORE_DIV_SHIFT 10
+#define RK3572_ACLK_M_LITCORE_DIV_MASK 0x1f
+#define RK3572_ACLK_M_LITCORE_DIV_SHIFT 2
+#define RK3572_PCLK_DBG_LITCORE_DIV_MASK 0x1f
+#define RK3572_PCLK_DBG_LITCORE_DIV_SHIFT 7
+#define RK3572_ACLK_CCI_DIV_MASK 0x1f
+#define RK3572_ACLK_CCI_DIV_SHIFT 7
+#define RK3572_ACLK_CCI_MUX_MASK 0x3
+#define RK3572_ACLK_CCI_MUX_SHIFT 12
+
+#define RK3572_BIGCORE_CLKSEL1(_amcore) \
+{ \
+ .reg = RK3572_BIGCORE_CLKSEL_CON(1), \
+ .val = HIWORD_UPDATE((_amcore) - 1, RK3572_ACLK_M_BIGCORE_DIV_MASK, \
+ RK3572_ACLK_M_BIGCORE_DIV_SHIFT), \
+}
+
+#define RK3572_BIGCORE_CLKSEL2(_pclkdbg) \
+{ \
+ .reg = RK3572_BIGCORE_CLKSEL_CON(2), \
+ .val = HIWORD_UPDATE((_pclkdbg) - 1, RK3572_PCLK_DBG_BIGCORE_DIV_MASK, \
+ RK3572_PCLK_DBG_BIGCORE_DIV_SHIFT), \
+}
+
+#define RK3572_LITCORE0_CLKSEL1(_amcore, _pclkdbg) \
+{ \
+ .reg = RK3572_LITCORE0_CLKSEL_CON(1), \
+ .val = HIWORD_UPDATE((_amcore) - 1, RK3572_ACLK_M_LITCORE_DIV_MASK, \
+ RK3572_ACLK_M_LITCORE_DIV_SHIFT) | \
+ HIWORD_UPDATE((_pclkdbg) - 1, RK3572_PCLK_DBG_LITCORE_DIV_MASK, \
+ RK3572_PCLK_DBG_LITCORE_DIV_SHIFT), \
+}
+
+#define RK3572_LITCORE1_CLKSEL1(_amcore, _pclkdbg) \
+{ \
+ .reg = RK3572_LITCORE1_CLKSEL_CON(1), \
+ .val = HIWORD_UPDATE((_amcore) - 1, RK3572_ACLK_M_LITCORE_DIV_MASK, \
+ RK3572_ACLK_M_LITCORE_DIV_SHIFT) | \
+ HIWORD_UPDATE((_pclkdbg) - 1, RK3572_PCLK_DBG_LITCORE_DIV_MASK, \
+ RK3572_PCLK_DBG_LITCORE_DIV_SHIFT), \
+}
+
+#define RK3572_CCI_CLKSEL3(_ccisel, _div) \
+{ \
+ .reg = RK3572_CCI_CLKSEL_CON(3), \
+ .val = HIWORD_UPDATE(_ccisel, RK3572_ACLK_CCI_MUX_MASK, \
+ RK3572_ACLK_CCI_MUX_SHIFT) | \
+ HIWORD_UPDATE((_div) - 1, RK3572_ACLK_CCI_DIV_MASK, \
+ RK3572_ACLK_CCI_DIV_SHIFT), \
+}
+
+#define RK3572_CPUBCLK_RATE(_prate, _amcore, _pclkdbg) \
+{ \
+ .prate = _prate##U, \
+ .divs = { \
+ RK3572_BIGCORE_CLKSEL1(_amcore), \
+ RK3572_BIGCORE_CLKSEL2(_pclkdbg), \
+ }, \
+}
+
+#define RK3572_CPUL0CLK_RATE(_prate, _amcore, _pclkdbg, _ccisel) \
+{ \
+ .prate = _prate##U, \
+ .divs = { \
+ RK3572_LITCORE0_CLKSEL1(_amcore, _pclkdbg), \
+ }, \
+ .pre_muxs = { \
+ RK3572_CCI_CLKSEL3(1, 2), \
+ }, \
+ .post_muxs = { \
+ RK3572_CCI_CLKSEL3(_ccisel, 2), \
+ }, \
+}
+
+#define RK3572_CPUL1CLK_RATE(_prate, _amcore, _pclkdbg) \
+{ \
+ .prate = _prate##U, \
+ .divs = { \
+ RK3572_LITCORE1_CLKSEL1(_amcore, _pclkdbg), \
+ }, \
+}
+
+static struct rockchip_cpuclk_rate_table rk3572_cpubclk_rates[] __initdata = {
+ RK3572_CPUBCLK_RATE(2496000000, 2, 6),
+ RK3572_CPUBCLK_RATE(2400000000, 2, 6),
+ RK3572_CPUBCLK_RATE(2304000000, 2, 6),
+ RK3572_CPUBCLK_RATE(2208000000, 2, 6),
+ RK3572_CPUBCLK_RATE(2184000000, 2, 6),
+ RK3572_CPUBCLK_RATE(2088000000, 2, 6),
+ RK3572_CPUBCLK_RATE(2040000000, 2, 6),
+ RK3572_CPUBCLK_RATE(2016000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1992000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1896000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1800000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1704000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1608000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1584000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1560000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1536000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1512000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1488000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1464000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1440000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1416000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1392000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1368000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1344000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1320000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1296000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1272000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1248000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1224000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1200000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1104000000, 2, 6),
+ RK3572_CPUBCLK_RATE(1008000000, 2, 6),
+ RK3572_CPUBCLK_RATE(912000000, 2, 6),
+ RK3572_CPUBCLK_RATE(816000000, 2, 6),
+ RK3572_CPUBCLK_RATE(696000000, 2, 6),
+ RK3572_CPUBCLK_RATE(600000000, 2, 6),
+ RK3572_CPUBCLK_RATE(408000000, 2, 6),
+ RK3572_CPUBCLK_RATE(312000000, 2, 6),
+ RK3572_CPUBCLK_RATE(216000000, 2, 6),
+ RK3572_CPUBCLK_RATE(96000000, 2, 6),
+};
+
+static const struct rockchip_cpuclk_reg_data rk3572_cpubclk_data = {
+ .core_reg[0] = RK3572_BIGCORE_CLKSEL_CON(1),
+ .div_core_shift[0] = 0,
+ .div_core_mask[0] = 0x1f,
+ .num_cores = 1,
+ .mux_core_alt = 1,
+ .mux_core_main = 0,
+ .mux_core_shift = 5,
+ .mux_core_mask = 0x3,
+};
+
+static struct rockchip_cpuclk_rate_table rk3572_cpul0clk_rates[] __initdata = {
+ RK3572_CPUL0CLK_RATE(2400000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(2304000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(2208000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(2184000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(2088000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(2040000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(2016000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1992000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1896000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1800000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1704000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1608000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1584000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1560000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1536000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1512000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1488000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1464000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1440000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1416000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1392000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1368000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1344000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1320000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1296000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1272000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1248000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1224000000, 2, 6, 0),
+ RK3572_CPUL0CLK_RATE(1200000000, 2, 6, 1),
+ RK3572_CPUL0CLK_RATE(1104000000, 2, 6, 1),
+ RK3572_CPUL0CLK_RATE(1008000000, 2, 6, 1),
+ RK3572_CPUL0CLK_RATE(912000000, 2, 6, 1),
+ RK3572_CPUL0CLK_RATE(816000000, 2, 6, 1),
+ RK3572_CPUL0CLK_RATE(696000000, 2, 6, 1),
+ RK3572_CPUL0CLK_RATE(600000000, 2, 6, 1),
+ RK3572_CPUL0CLK_RATE(408000000, 2, 6, 1),
+ RK3572_CPUL0CLK_RATE(312000000, 2, 6, 1),
+ RK3572_CPUL0CLK_RATE(216000000, 2, 6, 1),
+ RK3572_CPUL0CLK_RATE(96000000, 2, 6, 1),
+};
+
+static const struct rockchip_cpuclk_reg_data rk3572_cpul0clk_data = {
+ .core_reg[0] = RK3572_LITCORE0_CLKSEL_CON(0),
+ .div_core_shift[0] = 3,
+ .div_core_mask[0] = 0x1f,
+ .num_cores = 1,
+ .mux_core_alt = 1,
+ .mux_core_main = 0,
+ .mux_core_shift = 8,
+ .mux_core_mask = 0x3,
+};
+
+static struct rockchip_cpuclk_rate_table rk3572_cpul1clk_rates[] __initdata = {
+ RK3572_CPUL1CLK_RATE(2400000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(2304000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(2208000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(2184000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(2088000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(2040000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(2016000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1992000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1896000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1800000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1704000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1608000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1584000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1560000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1536000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1512000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1488000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1464000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1440000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1416000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1392000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1368000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1344000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1320000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1296000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1272000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1248000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1224000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1200000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1188000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1104000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(1008000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(912000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(816000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(696000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(600000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(594000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(408000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(396000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(312000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(216000000, 2, 6),
+ RK3572_CPUL1CLK_RATE(96000000, 2, 6),
+};
+
+#define MFLAGS CLK_MUX_HIWORD_MASK
+#define DFLAGS CLK_DIVIDER_HIWORD_MASK
+#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
+
+PNAME(mux_aupll_ref_p) = { "xin24m", "aupll_ref_io" };
+PNAME(mux_pll_p) = { "xin24m", "xin32k" };
+PNAME(mux_aupll_p) = { "aupll_ref", "xin32k" };
+PNAME(mux_24m_32k_p) = { "xin24m", "clk_32k" };
+PNAME(gpll_cpll_p) = { "gpll", "cpll" };
+PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m" };
+PNAME(gpll_cpll_aupll_p) = { "gpll", "cpll", "aupll" };
+PNAME(gpll_cpll_aupll_24m_p) = { "gpll", "cpll", "aupll", "xin24m" };
+PNAME(gpll_cpll_spll_aupll_p) = { "gpll", "cpll", "spll", "aupll" };
+PNAME(gpll_spll_aupll_bpll_p) = { "gpll", "spll", "aupll", "bpll_dummy" };
+PNAME(gpll_cpll_spll_aupll_bpll_p) = { "gpll", "cpll", "spll", "aupll", "bpll_dummy" };
+PNAME(gpll_cpll_spll_aupll_bpll_24m_p) = {
+ "gpll", "cpll", "spll", "aupll", "bpll_dummy", "xin24m",
+};
+
+PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" };
+PNAME(gpll_cpll_bpll_p) = { "gpll", "cpll", "bpll_dummy" };
+PNAME(gpll_cpll_spll_bpll_p) = { "gpll", "cpll", "spll", "bpll_dummy" };
+PNAME(gpll_cpll_aupll_spll_p) = { "gpll", "cpll", "aupll", "spll" };
+PNAME(gpll_cpll_aupll_spll_bpll_p) = { "gpll", "cpll", "aupll", "spll", "bpll_dummy" };
+PNAME(gpll_cpll_spll_aupll_24m_p) = { "gpll", "cpll", "spll", "aupll", "xin24m" };
+PNAME(gpll_spll_cpll_bpll_p) = { "gpll", "spll", "cpll", "bpll_dummy" };
+PNAME(gpll_cpll_vpll_aupll_bpll_24m_p) = {
+ "gpll", "cpll", "vpll", "aupll", "bpll_dummy", "xin24m",
+};
+
+PNAME(gpll_spll_isppvtpll_bpll_p) = { "gpll", "spll", "clk_isp_pvtpll_src", "bpll_dummy" };
+PNAME(gpll_cpll_vpll_bpll_p) = { "gpll", "cpll", "vpll", "bpll_dummy" };
+PNAME(gpll_24m_32k_p) = { "gpll", "xin24m", "clk_32k" };
+PNAME(mux_24m_spll_gpll_cpll_p) = {"xin24m", "spll", "gpll", "cpll" };
+PNAME(mux_100m_24m_p) = { "clk_cpll_div10", "xin24m" };
+PNAME(mux_100m_24m_32k_p) = { "clk_cpll_div10", "xin24m", "clk_32k" };
+PNAME(mux_100m_50m_24m_p) = { "clk_cpll_div10", "clk_cpll_div20", "xin24m" };
+PNAME(mux_100m_50m_24m_rc_p) = {
+ "clk_cpll_div10", "clk_cpll_div20", "xin24m", "clk_rcosc",
+};
+
+PNAME(mux_150m_100m_50m_24m_p) = {
+ "clk_gpll_div8", "clk_cpll_div10", "clk_cpll_div20", "xin24m",
+};
+
+PNAME(mux_200m_100m_50m_24m_p) = {
+ "clk_gpll_div6", "clk_cpll_div10", "clk_cpll_div20", "xin24m",
+};
+
+PNAME(mux_300m_200m_100m_24m_p) = {
+ "clk_gpll_div4", "clk_gpll_div6", "clk_cpll_div10", "xin24m",
+};
+
+PNAME(mux_300m_200m_100m_50m_24m_p) = {
+ "clk_gpll_div4", "clk_gpll_div6", "clk_cpll_div10", "clk_cpll_div20", "xin24m",
+};
+
+PNAME(mux_400m_200m_100m_24m_p) = {
+ "clk_gpll_div3", "clk_gpll_div6", "clk_cpll_div10", "xin24m",
+};
+
+PNAME(mux_600m_400m_300m_24m_p) = {
+ "clk_gpll_div2", "clk_gpll_div3", "clk_gpll_div4", "xin24m",
+};
+
+PNAME(mux_500m_250m_100m_24m_p) = {
+ "clk_cpll_div2", "clk_cpll_div4", "clk_cpll_div10", "xin24m",
+};
+
+PNAME(mux_175m_116m_58m_24m_p) = {
+ "clk_spll_div4", "clk_spll_div6", "clk_spll_div12", "xin24m",
+};
+
+PNAME(mux_116m_58m_24m_p) = { "clk_spll_div6", "clk_spll_div12", "xin24m" };
+PNAME(clk_uart_src_p) = {
+ "gpll", "cpll", "aupll", "xin24m", "clk_uart_frac_0", "clk_uart_frac_1",
+ "clk_uart_frac_2",
+};
+
+PNAME(ref_pulse_p) = {
+ "usb0_sof_clk", "usb1_sof_clk", "gmac0_ptp_pps", "gmac1_ptp_pps", "asrc_ref_pulse",
+};
+
+PNAME(lrck_asrc_src_p) = {
+ "asrc_sai0_fs_inter", "asrc_sai1_fs_inter", "asrc_sai2_fs_inter", "asrc_sai3_fs_inter",
+ "asrc_sai4_fs_inter", "asrc_sai5_fs_inter", "asrc_pdm0_clk", "asrc_spdifrx0_clk",
+ "asrc_spdifrx1_clk", "mclk_asrc0_src_0", "mclk_asrc1_src_1",
+};
+
+PNAME(lrck_asrc_dst_p) = {
+ "asrc_sai0_fs_inter", "asrc_sai1_fs_inter", "asrc_sai2_fs_inter", "asrc_sai3_fs_inter",
+ "asrc_sai4_fs_inter", "asrc_sai5_fs_inter", "asrc_pdm0_clk", "asrc_spdiftx0_clk",
+ "asrc_spdiftx1_clk", "asrc_spdiftx2_clk", "mclk_asrc0_src_0", "mclk_asrc1_src_1",
+};
+
+PNAME(asrc_ref_pulse_p) = {
+ "asrc_sai0_fs_inter", "asrc_sai1_fs_inter", "asrc_sai2_fs_inter", "asrc_sai3_fs_inter",
+ "asrc_sai4_fs_inter", "asrc_sai5_fs_inter", "asrc_spdifrx0_clk", "asrc_spdifrx1_clk",
+};
+
+PNAME(clk_freq_pwm1_p) = {
+ "sai0_mclk_in", "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in", "sai4_mclk_in",
+ "sai_sclkin_freq",
+};
+
+PNAME(clk_counter_pwm1_p) = {
+ "sai0_mclk_in", "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in", "sai4_mclk_in",
+ "sai_sclkin_counter",
+};
+
+PNAME(sai_sclkin_freq_p) = {
+ "sai0_sclk_in", "sai1_sclk_in", "sai2_sclk_in", "sai3_sclk_in", "sai4_sclk_in",
+};
+
+PNAME(clk_timer7_p) = {
+ "clk_cpll_div10", "xin24m", "mclk_asrc0_src_0", "mclk_asrc1_src_1",
+};
+
+PNAME(clk_timer8_p) = {
+ "clk_cpll_div10", "xin24m", "mclk_asrc0_src_0", "mclk_asrc1_src_1",
+};
+
+PNAME(clk_gmac0_ptp_ref_src_p) = { "clk_gmac0_ptp_ref_pre", "gmac0_ptp_refclk_in" };
+PNAME(clk_gmac1_ptp_ref_p) = { "clk_gmac1_ptp_ref_src", "gmac1_ptp_refclk_in" };
+PNAME(clk_ref_pciephy_p) = {
+ "clk_pcie_100m_src", "clk_pcie_100m_nduty_src", "xin24m",
+};
+
+PNAME(dclk_ebc_p) = { "dclk_ebc_int_src", "dclk_ebc_frac_src" };
+PNAME(hclk_vi_root_p) = {
+ "clk_gpll_div6", "clk_cpll_div10", "aclk_vi_root_inter", "xin24m",
+};
+
+PNAME(dclk_vp0_p) = { "dclk_vp0_src", "clk_hdmiphy_pixel0" };
+PNAME(dclk_vp1_p) = { "dclk_vp1_src", "clk_hdmiphy_pixel0" };
+PNAME(mux_24m_frac_int_mclk4_p) = {
+ "xin24m", "clk_audio_frac_0", "clk_audio_frac_1", "clk_audio_frac_2",
+ "clk_audio_frac_3", "clk_audio_int_0", "clk_audio_int_1", "clk_audio_int_2",
+ "sai0_mclk_in", "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in",
+};
+
+PNAME(mclk_sai4_p) = { "mclk_sai4_src", "sai4_mclk_in" };
+PNAME(mclk_sai5_p) = { "mclk_sai5_src", "sai4_mclk_in" };
+PNAME(mclk_spdif_tx2_p) = { "mclk_spdif_tx2_src", "sai4_mclk_in" };
+PNAME(clk_ref_osc_mphy_p) = { "xin24m", "clk_ref_mphy_26m" };
+PNAME(clk_pwm0_osc_p) = { "xin24m", "clk_rcosc" };
+PNAME(sclk_uart1_p) = { "clk_uart1_src_top", "xin24m", "clk_rcosc" };
+PNAME(clk_pdm0_p) = { "clk_pdm0_src_top", "xin24m", "clk_rcosc" };
+PNAME(mclk_pdm0_p) = { "mclk_pdm0_src_top", "xin24m", "clk_rcosc" };
+PNAME(pclk_phpsubsys_root_p) = { "clk_cpll_div10_phpphy", "xin24m" };
+PNAME(mux_armclkl0_p) = { "lpll", "gpll", "litcore0pvtpll" };
+PNAME(mux_armclkb_p) = { "bpll", "gpll", "bigcorepvtpll" };
+PNAME(mux_armclkl1_p) = { "lpll_dummy", "gpll", "litcore1pvtpll" };
+PNAME(sclk_apb2asb_src_p) = {
+ "spll", "clk_gpll_div2", "clk_cpll_div2", "clk_gpll_div3", "clk_gpll_div4",
+};
+
+PNAME(sclk_apb2asb_p) = {
+ "sclk_apb2asb_src", "clk_gpll_div6", "clk_cpll_div10", "xin24m",
+};
+
+PNAME(mux_24m_frac_int_mclki_p) = {
+ "xin24m", "clk_audio_int_0", "clk_audio_int_1", "clk_audio_int_2", "clk_audio_frac_0",
+ "clk_audio_frac_1", "clk_audio_frac_2", "clk_audio_frac_3", "sai0_mclk_in",
+ "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in", "sai4_mclk_in",
+};
+
+PNAME(mux_24m_frac_int_mclki_sclki_p) = {
+ "xin24m", "clk_audio_int_0", "clk_audio_int_1", "clk_audio_int_2", "clk_audio_frac_0",
+ "clk_audio_frac_1", "clk_audio_frac_2", "clk_audio_frac_3", "sai0_mclk_in",
+ "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in", "sai4_mclk_in", "sai0_sclk_in",
+ "sai1_sclk_in", "sai2_sclk_in", "sai3_sclk_in", "sai4_sclk_in",
+};
+
+static u32 mux_24m_frac_int_mclki_idx[] = {
+ 0, 5, 6, 7, 1, 2, 3, 4, 8, 9, 10, 11, 12,
+};
+
+static u32 mux_24m_frac_int_mclki_sclki_idx[] = {
+ 0, 5, 6, 7, 1, 2, 3, 4, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+};
+
+static struct rockchip_pll_clock rk3572_pll_clks[] __initdata = {
+ /* Keep BPLL and LPLL enabled for firmware consumers. */
+ [bpll] = PLL(pll_rk3588_core, PLL_BPLL, "bpll", mux_pll_p,
+ CLK_IGNORE_UNUSED, RK3572_PLL_CON(0),
+ RK3572_MODE_CON1, 0, 15, 0, rk3572_pll_rates),
+ [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p,
+ CLK_IGNORE_UNUSED, RK3572_LPLL_CON(16),
+ RK3572_LPLL_MODE_CON0, 0, 15, 0, rk3572_pll_rates),
+ [vpll] = PLL(pll_rk3588, PLL_VPLL, "vpll", mux_pll_p,
+ 0, RK3572_PLL_CON(88),
+ RK3572_MODE_CON0, 4, 15, 0, rk3572_pll_rates),
+ [aupll] = PLL(pll_rk3588, PLL_AUPLL, "aupll", mux_aupll_p,
+ 0, RK3572_PLL_CON(96),
+ RK3572_MODE_CON0, 6, 15, 0, rk3572_aupll_rates),
+ [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p,
+ 0, RK3572_PLL_CON(104),
+ RK3572_MODE_CON0, 8, 15, 0, rk3572_pll_rates),
+ [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p,
+ CLK_IGNORE_UNUSED, RK3572_PLL_CON(112),
+ RK3572_MODE_CON0, 2, 15, 0, rk3572_pll_rates),
+ [ppll] = PLL(pll_rk3588_ddr, PLL_PPLL, "ppll", mux_pll_p,
+ 0, RK3572_PPLL_CON(128),
+ RK3572_PPLL_CON(134), 15, 15, 0, rk3572_ppll_rates),
+};
+
+static struct rockchip_clk_branch rk3572_clk_branches[] __initdata = {
+ /* fixed */
+ FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
+
+ COMPOSITE_FRACMUX(CLK_32K, "clk_32k", "xin24m", CLK_IS_CRITICAL,
+ RK3572_PMU_CLKSEL_CON(21), 0,
+ RK3572_PMU_CLKGATE_CON(7), 14, GFLAGS, NULL),
+
+ FACTOR(0, "clk_spll_div12", "spll", 0, 1, 12),
+ FACTOR(0, "clk_spll_div6", "spll", 0, 1, 6),
+ FACTOR(0, "clk_spll_div4", "spll", 0, 1, 4),
+ FACTOR(0, "clk_spll_div2", "spll", 0, 1, 2),
+
+ COMPOSITE(CLK_CPLL_DIV20, "clk_cpll_div20", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(0), 1, GFLAGS),
+ COMPOSITE(CLK_CPLL_DIV10, "clk_cpll_div10", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS,
+ RK3572_CLKGATE_CON(0), 2, GFLAGS),
+ COMPOSITE(CLK_GPLL_DIV8, "clk_gpll_div8", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(0), 3, GFLAGS),
+ COMPOSITE(CLK_GPLL_DIV6, "clk_gpll_div6", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS,
+ RK3572_CLKGATE_CON(0), 4, GFLAGS),
+ COMPOSITE(CLK_CPLL_DIV4, "clk_cpll_div4", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(0), 5, GFLAGS),
+ COMPOSITE(CLK_GPLL_DIV4, "clk_gpll_div4", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS,
+ RK3572_CLKGATE_CON(0), 6, GFLAGS),
+ COMPOSITE(CLK_GPLL_DIV3, "clk_gpll_div3", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(3), 12, 1, MFLAGS, 7, 5, DFLAGS,
+ RK3572_CLKGATE_CON(0), 8, GFLAGS),
+ COMPOSITE(CLK_CPLL_DIV2, "clk_cpll_div2", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS,
+ RK3572_CLKGATE_CON(0), 10, GFLAGS),
+ COMPOSITE(CLK_GPLL_DIV2, "clk_gpll_div2", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(0), 11, GFLAGS),
+ COMPOSITE_NODIV(SCLK_APB2ASB_SRC, "sclk_apb2asb_src", sclk_apb2asb_src_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(6), 13, 3, MFLAGS,
+ RK3572_CLKGATE_CON(0), 15, GFLAGS),
+ COMPOSITE(CLK_DDRPHY_TOP_SRC, "clk_ddrphy_top_src", gpll_cpll_spll_aupll_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(8), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(1), 1, GFLAGS),
+ COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(8), 7, 2, MFLAGS,
+ RK3572_CLKGATE_CON(1), 2, GFLAGS),
+ COMPOSITE(ACLK_TOP, "aclk_top", gpll_cpll_spll_aupll_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(9), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(1), 4, GFLAGS),
+ COMPOSITE(ACLK_TOP_MID, "aclk_top_mid", gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(10), 5, 1, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(1), 7, GFLAGS),
+ COMPOSITE(ACLK_SECURE_HIGH, "aclk_secure_high", gpll_spll_aupll_bpll_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(10), 11, 2, MFLAGS, 6, 5, DFLAGS,
+ RK3572_CLKGATE_CON(1), 8, GFLAGS),
+ COMPOSITE_NOMUX(CLK_BPLL_DIV, "clk_bpll_div", "bpll", 0,
+ RK3572_CLKSEL_CON(11), 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(1), 9, GFLAGS),
+
+ MUX(CLK_AUDIO_FRAC_0_SRC, "clk_audio_frac_0_src", gpll_cpll_aupll_24m_p, 0,
+ RK3572_CLKSEL_CON(13), 0, 2, MFLAGS),
+ MUX(CLK_AUDIO_FRAC_1_SRC, "clk_audio_frac_1_src", gpll_cpll_aupll_24m_p, 0,
+ RK3572_CLKSEL_CON(15), 0, 2, MFLAGS),
+ MUX(CLK_AUDIO_FRAC_2_SRC, "clk_audio_frac_2_src", gpll_cpll_aupll_24m_p, 0,
+ RK3572_CLKSEL_CON(17), 0, 2, MFLAGS),
+ MUX(CLK_AUDIO_FRAC_3_SRC, "clk_audio_frac_3_src", gpll_cpll_aupll_24m_p, 0,
+ RK3572_CLKSEL_CON(19), 0, 2, MFLAGS),
+ COMPOSITE_FRAC(CLK_AUDIO_FRAC_3, "clk_audio_frac_3", "clk_audio_frac_3_src", 0,
+ RK3572_CLKSEL_CON(18), 0,
+ RK3572_CLKGATE_CON(1), 14, GFLAGS),
+ COMPOSITE_NODIV(HCLK_TOP, "hclk_top", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(19), 2, 2, MFLAGS,
+ RK3572_CLKGATE_CON(1), 15, GFLAGS),
+ MUX(CLK_UART_FRAC_0_SRC, "clk_uart_frac_0_src", gpll_cpll_aupll_24m_p, 0,
+ RK3572_CLKSEL_CON(23), 0, 2, MFLAGS),
+ COMPOSITE_FRAC(CLK_UART_FRAC_0, "clk_uart_frac_0", "clk_uart_frac_0_src", 0,
+ RK3572_CLKSEL_CON(22), 0,
+ RK3572_CLKGATE_CON(2), 6, GFLAGS),
+ MUX(CLK_UART_FRAC_1_SRC, "clk_uart_frac_1_src", gpll_cpll_aupll_24m_p, 0,
+ RK3572_CLKSEL_CON(25), 0, 2, MFLAGS),
+ COMPOSITE_FRAC(CLK_UART_FRAC_1, "clk_uart_frac_1", "clk_uart_frac_1_src", 0,
+ RK3572_CLKSEL_CON(24), 0,
+ RK3572_CLKGATE_CON(2), 7, GFLAGS),
+ MUX(CLK_UART_FRAC_2_SRC, "clk_uart_frac_2_src", gpll_cpll_aupll_24m_p, 0,
+ RK3572_CLKSEL_CON(27), 0, 2, MFLAGS),
+ COMPOSITE_FRAC(CLK_UART_FRAC_2, "clk_uart_frac_2", "clk_uart_frac_2_src", 0,
+ RK3572_CLKSEL_CON(26), 0,
+ RK3572_CLKGATE_CON(2), 8, GFLAGS),
+ COMPOSITE(CLK_UART1_SRC_TOP, "clk_uart1_src_top", clk_uart_src_p, 0,
+ RK3572_CLKSEL_CON(29), 8, 3, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(2), 14, GFLAGS),
+ COMPOSITE_NOMUX(CLK_AUDIO_INT_0, "clk_audio_int_0", "aupll", 0,
+ RK3572_CLKSEL_CON(29), 11, 5, DFLAGS,
+ RK3572_CLKGATE_CON(2), 15, GFLAGS),
+ COMPOSITE_NOMUX(CLK_AUDIO_INT_1, "clk_audio_int_1", "aupll", 0,
+ RK3572_CLKSEL_CON(30), 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(3), 0, GFLAGS),
+ COMPOSITE_NOMUX(CLK_AUDIO_INT_2, "clk_audio_int_2", "aupll", 0,
+ RK3572_CLKSEL_CON(30), 5, 5, DFLAGS,
+ RK3572_CLKGATE_CON(3), 1, GFLAGS),
+ COMPOSITE_MUXTBL(CLK_PDM0_SRC_TOP, "clk_pdm0_src_top", mux_24m_frac_int_mclki_p,
+ ARRAY_SIZE(mux_24m_frac_int_mclki_p), 0,
+ RK3572_CLKSEL_CON(31), 9, 4, MFLAGS, mux_24m_frac_int_mclki_idx, 0, 9,
+ DFLAGS,
+ RK3572_CLKGATE_CON(3), 3, GFLAGS),
+ COMPOSITE_NOMUX(CLK_GMAC0_125M_SRC, "clk_gmac0_125m_src", "cpll", 0,
+ RK3572_CLKSEL_CON(33), 10, 5, DFLAGS,
+ RK3572_CLKGATE_CON(3), 7, GFLAGS),
+ COMPOSITE_NOMUX(CLK_GMAC1_125M_SRC, "clk_gmac1_125m_src", "cpll", 0,
+ RK3572_CLKSEL_CON(34), 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(3), 8, GFLAGS),
+ COMPOSITE_MUXTBL(MCLK_ASRC0_SRC_0, "mclk_asrc0_src_0", mux_24m_frac_int_mclki_sclki_p,
+ ARRAY_SIZE(mux_24m_frac_int_mclki_sclki_p), 0,
+ RK3572_CLKSEL_CON(34), 10, 5, MFLAGS, mux_24m_frac_int_mclki_sclki_idx,
+ 5, 5, DFLAGS,
+ RK3572_CLKGATE_CON(3), 11, GFLAGS),
+ COMPOSITE_MUXTBL(MCLK_ASRC1_SRC_1, "mclk_asrc1_src_1", mux_24m_frac_int_mclki_sclki_p,
+ ARRAY_SIZE(mux_24m_frac_int_mclki_sclki_p), 0,
+ RK3572_CLKSEL_CON(35), 5, 5, MFLAGS, mux_24m_frac_int_mclki_sclki_idx,
+ 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(3), 12, GFLAGS),
+ COMPOSITE(REF_CLK0_OUT_PLL, "ref_clk0_out_pll", gpll_cpll_spll_aupll_bpll_24m_p, 0,
+ RK3572_CLKSEL_CON(38), 8, 3, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(4), 2, GFLAGS),
+ COMPOSITE(REF_CLK1_OUT_PLL, "ref_clk1_out_pll", gpll_cpll_spll_aupll_bpll_24m_p, 0,
+ RK3572_CLKSEL_CON(39), 8, 3, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(4), 3, GFLAGS),
+ COMPOSITE(REF_CLK2_OUT_PLL, "ref_clk2_out_pll", gpll_cpll_spll_aupll_bpll_24m_p, 0,
+ RK3572_CLKSEL_CON(40), 8, 3, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(4), 4, GFLAGS),
+ COMPOSITE(REFCLKO25M_GMAC0_OUT, "refclko25m_gmac0_out", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(42), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RK3572_CLKGATE_CON(5), 6, GFLAGS),
+ COMPOSITE(REFCLKO25M_GMAC1_OUT, "refclko25m_gmac1_out", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(42), 15, 1, MFLAGS, 8, 7, DFLAGS,
+ RK3572_CLKGATE_CON(5), 7, GFLAGS),
+ COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0,
+ RK3572_CLKSEL_CON(43), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(5), 8, GFLAGS),
+ GATE(CLK_GMAC0_RMII_CRU, "clk_gmac0_rmii_cru", "clk_cpll_div20", 0,
+ RK3572_CLKGATE_CON(5), 9, GFLAGS),
+ GATE(CLK_GMAC1_RMII_CRU, "clk_gmac1_rmii_cru", "clk_cpll_div20", 0,
+ RK3572_CLKGATE_CON(5), 10, GFLAGS),
+ GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0,
+ RK3572_CLKGATE_CON(5), 11, GFLAGS),
+ COMPOSITE(CAM_CLK0_OUT_IOUT, "cam_clk0_out_iout", mux_24m_spll_gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(44), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(5), 15, GFLAGS),
+ COMPOSITE(CAM_CLK1_OUT_IOUT, "cam_clk1_out_iout", mux_24m_spll_gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(45), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(6), 0, GFLAGS),
+ COMPOSITE(CAM_CLK2_OUT_IOUT, "cam_clk2_out_iout", mux_24m_spll_gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(46), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(6), 1, GFLAGS),
+ COMPOSITE_MUXTBL(MCLK_PDM0_SRC_TOP, "mclk_pdm0_src_top", mux_24m_frac_int_mclki_p,
+ ARRAY_SIZE(mux_24m_frac_int_mclki_p), 0,
+ RK3572_CLKSEL_CON(47), 9, 4, MFLAGS, mux_24m_frac_int_mclki_idx, 0, 9,
+ DFLAGS,
+ RK3572_CLKGATE_CON(6), 10, GFLAGS),
+ COMPOSITE_NODIV(HCLK_AUDIO_ROOT, "hclk_audio_root", mux_200m_100m_50m_24m_p,
+ CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(49), 0, 2, MFLAGS,
+ RK3572_CLKGATE_CON(7), 1, GFLAGS),
+ GATE(HCLK_ASRC_2CH_0, "hclk_asrc_2ch_0", "hclk_audio_root", 0,
+ RK3572_CLKGATE_CON(7), 3, GFLAGS),
+ GATE(HCLK_ASRC_2CH_1, "hclk_asrc_2ch_1", "hclk_audio_root", 0,
+ RK3572_CLKGATE_CON(7), 4, GFLAGS),
+ COMPOSITE(CLK_ASRC_2CH_0, "clk_asrc_2ch_0", gpll_cpll_aupll_p, 0,
+ RK3572_CLKSEL_CON(49), 7, 2, MFLAGS, 2, 5, DFLAGS,
+ RK3572_CLKGATE_CON(7), 7, GFLAGS),
+ COMPOSITE(CLK_ASRC_2CH_1, "clk_asrc_2ch_1", gpll_cpll_aupll_p, 0,
+ RK3572_CLKSEL_CON(49), 14, 2, MFLAGS, 9, 5, DFLAGS,
+ RK3572_CLKGATE_CON(7), 8, GFLAGS),
+ COMPOSITE_MUXTBL(MCLK_SAI0, "mclk_sai0", mux_24m_frac_int_mclki_p,
+ ARRAY_SIZE(mux_24m_frac_int_mclki_p), 0,
+ RK3572_CLKSEL_CON(51), 11, 4, MFLAGS, mux_24m_frac_int_mclki_idx, 3, 8,
+ DFLAGS,
+ RK3572_CLKGATE_CON(7), 12, GFLAGS),
+ GATE(HCLK_SAI0, "hclk_sai0", "hclk_audio_root", 0,
+ RK3572_CLKGATE_CON(7), 13, GFLAGS),
+ GATE(HCLK_SPDIF_RX0, "hclk_spdif_rx0", "hclk_audio_root", 0,
+ RK3572_CLKGATE_CON(7), 14, GFLAGS),
+ COMPOSITE(MCLK_SPDIF_RX0, "mclk_spdif_rx0", gpll_cpll_aupll_p, 0,
+ RK3572_CLKSEL_CON(52), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(7), 15, GFLAGS),
+ COMPOSITE_MUXTBL(MCLK_SAI1, "mclk_sai1", mux_24m_frac_int_mclki_p,
+ ARRAY_SIZE(mux_24m_frac_int_mclki_p), 0,
+ RK3572_CLKSEL_CON(54), 8, 4, MFLAGS, mux_24m_frac_int_mclki_idx, 0, 8,
+ DFLAGS,
+ RK3572_CLKGATE_CON(8), 5, GFLAGS),
+ GATE(HCLK_SAI1, "hclk_sai1", "hclk_audio_root", 0,
+ RK3572_CLKGATE_CON(8), 6, GFLAGS),
+ COMPOSITE_MUXTBL(MCLK_SAI2, "mclk_sai2", mux_24m_frac_int_mclki_p,
+ ARRAY_SIZE(mux_24m_frac_int_mclki_p), 0,
+ RK3572_CLKSEL_CON(56), 8, 4, MFLAGS, mux_24m_frac_int_mclki_idx, 0, 8,
+ DFLAGS,
+ RK3572_CLKGATE_CON(8), 8, GFLAGS),
+ GATE(HCLK_SAI2, "hclk_sai2", "hclk_audio_root", 0,
+ RK3572_CLKGATE_CON(8), 10, GFLAGS),
+ COMPOSITE_MUXTBL(MCLK_SAI3, "mclk_sai3", mux_24m_frac_int_mclki_p,
+ ARRAY_SIZE(mux_24m_frac_int_mclki_p), 0,
+ RK3572_CLKSEL_CON(58), 8, 4, MFLAGS, mux_24m_frac_int_mclki_idx, 0, 8,
+ DFLAGS,
+ RK3572_CLKGATE_CON(8), 12, GFLAGS),
+ GATE(HCLK_SAI3, "hclk_sai3", "hclk_audio_root", 0,
+ RK3572_CLKGATE_CON(8), 14, GFLAGS),
+ GATE(CLK_SAI1_MCLKOUT, "clk_sai1_mclkout", "mclk_sai1", 0,
+ RK3572_CLKGATE_CON(4), 10, GFLAGS),
+ GATE(CLK_SAI2_MCLKOUT, "clk_sai2_mclkout", "mclk_sai2", 0,
+ RK3572_CLKGATE_CON(4), 11, GFLAGS),
+ GATE(CLK_SAI3_MCLKOUT, "clk_sai3_mclkout", "mclk_sai3", 0,
+ RK3572_CLKGATE_CON(4), 12, GFLAGS),
+ GATE(CLK_SAI0_MCLKOUT, "clk_sai0_mclkout", "mclk_sai0", 0,
+ RK3572_CLKGATE_CON(4), 14, GFLAGS),
+ GATE(HCLK_ACDCDIG_DSM, "hclk_acdcdig_dsm", "hclk_audio_root", 0,
+ RK3572_CLKGATE_CON(8), 15, GFLAGS),
+ GATE(MCLK_ACDCDIG_DSM, "mclk_acdcdig_dsm", "mclk_sai3", 0,
+ RK3572_CLKGATE_CON(9), 0, GFLAGS),
+ COMPOSITE_NODIV(PCLK_AUDIO_ROOT, "pclk_audio_root", mux_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(60), 12, 2, MFLAGS,
+ RK3572_CLKGATE_CON(9), 3, GFLAGS),
+ GATE(HCLK_SPDIF_TX0, "hclk_spdif_tx0", "hclk_audio_root", 0,
+ RK3572_CLKGATE_CON(9), 6, GFLAGS),
+ COMPOSITE_MUXTBL(MCLK_SPDIF_TX0, "mclk_spdif_tx0", mux_24m_frac_int_mclki_p,
+ ARRAY_SIZE(mux_24m_frac_int_mclki_p), 0,
+ RK3572_CLKSEL_CON(61), 8, 4, MFLAGS, mux_24m_frac_int_mclki_idx, 0, 8,
+ DFLAGS,
+ RK3572_CLKGATE_CON(9), 7, GFLAGS),
+ GATE(HCLK_SPDIF_TX1, "hclk_spdif_tx1", "hclk_audio_root", 0,
+ RK3572_CLKGATE_CON(9), 8, GFLAGS),
+ COMPOSITE_MUXTBL(MCLK_SPDIF_TX1, "mclk_spdif_tx1", mux_24m_frac_int_mclki_p,
+ ARRAY_SIZE(mux_24m_frac_int_mclki_p), 0,
+ RK3572_CLKSEL_CON(62), 8, 4, MFLAGS, mux_24m_frac_int_mclki_idx, 0, 8,
+ DFLAGS,
+ RK3572_CLKGATE_CON(9), 9, GFLAGS),
+ COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(64), 0, 2, MFLAGS,
+ RK3572_CLKGATE_CON(11), 0, GFLAGS),
+ COMPOSITE_NODIV(PCLK_BUS_ROOT, "pclk_bus_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(64), 2, 2, MFLAGS,
+ RK3572_CLKGATE_CON(11), 1, GFLAGS),
+ COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(64), 9, 1, MFLAGS, 4, 5, DFLAGS,
+ RK3572_CLKGATE_CON(11), 2, GFLAGS),
+ GATE(HCLK_CAN0, "hclk_can0", "hclk_bus_root", 0,
+ RK3572_CLKGATE_CON(11), 7, GFLAGS),
+ COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_24m_p, 0,
+ RK3572_CLKSEL_CON(65), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(11), 8, GFLAGS),
+ GATE(HCLK_CAN1, "hclk_can1", "hclk_bus_root", 0,
+ RK3572_CLKGATE_CON(11), 9, GFLAGS),
+ COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_24m_p, 0,
+ RK3572_CLKSEL_CON(65), 12, 2, MFLAGS, 7, 5, DFLAGS,
+ RK3572_CLKGATE_CON(11), 10, GFLAGS),
+ GATE(HCLK_CAN2, "hclk_can2", "hclk_bus_root", 0,
+ RK3572_CLKGATE_CON(11), 11, GFLAGS),
+ COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_24m_p, 0,
+ RK3572_CLKSEL_CON(66), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(11), 12, GFLAGS),
+ GATE(HCLK_CAN3, "hclk_can3", "hclk_bus_root", 0,
+ RK3572_CLKGATE_CON(11), 13, GFLAGS),
+ COMPOSITE(CLK_CAN3, "clk_can3", gpll_cpll_24m_p, 0,
+ RK3572_CLKSEL_CON(66), 12, 2, MFLAGS, 7, 5, DFLAGS,
+ RK3572_CLKGATE_CON(11), 14, GFLAGS),
+ COMPOSITE(ACLK_DECOM_ROOT, "aclk_decom_root", gpll_cpll_spll_bpll_p, 0,
+ RK3572_CLKSEL_CON(67), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(11), 15, GFLAGS),
+ GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(12), 5, GFLAGS),
+ GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(12), 6, GFLAGS),
+ GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(12), 7, GFLAGS),
+ GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(12), 8, GFLAGS),
+ GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(12), 9, GFLAGS),
+ GATE(PCLK_I2C6, "pclk_i2c6", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(12), 10, GFLAGS),
+ GATE(PCLK_I2C7, "pclk_i2c7", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(12), 11, GFLAGS),
+ GATE(PCLK_I2C8, "pclk_i2c8", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(12), 12, GFLAGS),
+ GATE(PCLK_I2C9, "pclk_i2c9", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(12), 13, GFLAGS),
+ GATE(PCLK_WDT_BUSMCU, "pclk_wdt_busmcu", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(12), 14, GFLAGS),
+ GATE(TCLK_WDT_BUSMCU, "tclk_wdt_busmcu", "xin24m", 0,
+ RK3572_CLKGATE_CON(12), 15, GFLAGS),
+ GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL,
+ RK3572_CLKGATE_CON(13), 0, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(67), 7, 2, MFLAGS,
+ RK3572_CLKGATE_CON(13), 5, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(67), 9, 2, MFLAGS,
+ RK3572_CLKGATE_CON(13), 6, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(67), 11, 2, MFLAGS,
+ RK3572_CLKGATE_CON(13), 7, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(67), 13, 2, MFLAGS,
+ RK3572_CLKGATE_CON(13), 8, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(68), 0, 2, MFLAGS,
+ RK3572_CLKGATE_CON(13), 9, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(68), 2, 2, MFLAGS,
+ RK3572_CLKGATE_CON(13), 10, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(68), 4, 2, MFLAGS,
+ RK3572_CLKGATE_CON(13), 11, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C8, "clk_i2c8", mux_200m_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(68), 6, 2, MFLAGS,
+ RK3572_CLKGATE_CON(13), 12, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C9, "clk_i2c9", mux_200m_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(68), 8, 2, MFLAGS,
+ RK3572_CLKGATE_CON(13), 13, GFLAGS),
+ GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(13), 15, GFLAGS),
+ COMPOSITE(CLK_SARADC, "clk_saradc", gpll_24m_32k_p, 0,
+ RK3572_CLKSEL_CON(69), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(14), 0, GFLAGS),
+ GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(14), 2, GFLAGS),
+ COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
+ RK3572_CLKSEL_CON(70), 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(14), 3, GFLAGS),
+ GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(14), 4, GFLAGS),
+ GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(14), 5, GFLAGS),
+ GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(14), 6, GFLAGS),
+ GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(14), 7, GFLAGS),
+ GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(14), 8, GFLAGS),
+ GATE(PCLK_UART6, "pclk_uart6", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(14), 9, GFLAGS),
+ GATE(PCLK_UART7, "pclk_uart7", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(14), 10, GFLAGS),
+ GATE(PCLK_UART8, "pclk_uart8", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(14), 11, GFLAGS),
+ GATE(PCLK_UART9, "pclk_uart9", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(14), 12, GFLAGS),
+ GATE(PCLK_UART10, "pclk_uart10", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(14), 13, GFLAGS),
+ GATE(PCLK_UART11, "pclk_uart11", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(14), 14, GFLAGS),
+ COMPOSITE(SCLK_UART0, "sclk_uart0", clk_uart_src_p, 0,
+ RK3572_CLKSEL_CON(71), 8, 3, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(14), 15, GFLAGS),
+ COMPOSITE(SCLK_UART2, "sclk_uart2", clk_uart_src_p, 0,
+ RK3572_CLKSEL_CON(72), 8, 3, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(15), 0, GFLAGS),
+ COMPOSITE(SCLK_UART3, "sclk_uart3", clk_uart_src_p, 0,
+ RK3572_CLKSEL_CON(73), 8, 3, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(15), 3, GFLAGS),
+ COMPOSITE(SCLK_UART4, "sclk_uart4", clk_uart_src_p, 0,
+ RK3572_CLKSEL_CON(74), 8, 3, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(15), 6, GFLAGS),
+ COMPOSITE(SCLK_UART5, "sclk_uart5", clk_uart_src_p, 0,
+ RK3572_CLKSEL_CON(75), 8, 3, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(15), 9, GFLAGS),
+ COMPOSITE(SCLK_UART6, "sclk_uart6", clk_uart_src_p, 0,
+ RK3572_CLKSEL_CON(76), 8, 3, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(15), 12, GFLAGS),
+ COMPOSITE(SCLK_UART7, "sclk_uart7", clk_uart_src_p, 0,
+ RK3572_CLKSEL_CON(77), 8, 3, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(15), 15, GFLAGS),
+ COMPOSITE(SCLK_UART8, "sclk_uart8", clk_uart_src_p, 0,
+ RK3572_CLKSEL_CON(78), 8, 3, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(16), 2, GFLAGS),
+ COMPOSITE(SCLK_UART9, "sclk_uart9", clk_uart_src_p, 0,
+ RK3572_CLKSEL_CON(79), 8, 3, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(16), 3, GFLAGS),
+ COMPOSITE(SCLK_UART10, "sclk_uart10", clk_uart_src_p, 0,
+ RK3572_CLKSEL_CON(80), 8, 3, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(16), 4, GFLAGS),
+ COMPOSITE(SCLK_UART11, "sclk_uart11", clk_uart_src_p, 0,
+ RK3572_CLKSEL_CON(81), 8, 3, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(16), 5, GFLAGS),
+ GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(16), 7, GFLAGS),
+ GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(16), 8, GFLAGS),
+ GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(16), 9, GFLAGS),
+ GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(16), 10, GFLAGS),
+ GATE(PCLK_SPI4, "pclk_spi4", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(16), 11, GFLAGS),
+ COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_300m_200m_100m_24m_p, 0,
+ RK3572_CLKSEL_CON(81), 13, 2, MFLAGS,
+ RK3572_CLKGATE_CON(16), 12, GFLAGS),
+ COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_300m_200m_100m_24m_p, 0,
+ RK3572_CLKSEL_CON(82), 0, 2, MFLAGS,
+ RK3572_CLKGATE_CON(16), 13, GFLAGS),
+ COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_300m_200m_100m_24m_p, 0,
+ RK3572_CLKSEL_CON(82), 2, 2, MFLAGS,
+ RK3572_CLKGATE_CON(16), 14, GFLAGS),
+ COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_300m_200m_100m_24m_p, 0,
+ RK3572_CLKSEL_CON(82), 4, 2, MFLAGS,
+ RK3572_CLKGATE_CON(16), 15, GFLAGS),
+ COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_300m_200m_100m_24m_p, 0,
+ RK3572_CLKSEL_CON(82), 6, 2, MFLAGS,
+ RK3572_CLKGATE_CON(17), 0, GFLAGS),
+ GATE(PCLK_WDT0, "pclk_wdt0", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(17), 1, GFLAGS),
+ GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0,
+ RK3572_CLKGATE_CON(17), 2, GFLAGS),
+ GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(17), 4, GFLAGS),
+ COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(82), 8, 2, MFLAGS,
+ RK3572_CLKGATE_CON(17), 5, GFLAGS),
+ GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0,
+ RK3572_CLKGATE_CON(17), 6, GFLAGS),
+ GATE(CLK_RC_PWM1, "clk_rc_pwm1", "clk_rcosc", 0,
+ RK3572_CLKGATE_CON(17), 7, GFLAGS),
+ GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(17), 10, GFLAGS),
+ COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(83), 0, 2, MFLAGS,
+ RK3572_CLKGATE_CON(17), 11, GFLAGS),
+ GATE(CLK_RC_PWM2, "clk_rc_pwm2", "clk_rcosc", 0,
+ RK3572_CLKGATE_CON(17), 12, GFLAGS),
+ GATE(CLK_OSC_PWM2, "clk_osc_pwm2", "xin24m", 0,
+ RK3572_CLKGATE_CON(17), 13, GFLAGS),
+ GATE(PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(18), 4, GFLAGS),
+ GATE(PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(18), 5, GFLAGS),
+ COMPOSITE_NODIV(CLK_TIMER0_ROOT, "clk_timer0_root", mux_100m_24m_p, 0,
+ RK3572_CLKSEL_CON(83), 10, 1, MFLAGS,
+ RK3572_CLKGATE_CON(18), 6, GFLAGS),
+ GATE(CLK_TIMER0, "clk_timer0", "clk_timer0_root", 0,
+ RK3572_CLKGATE_CON(18), 7, GFLAGS),
+ GATE(CLK_TIMER1, "clk_timer1", "clk_timer0_root", 0,
+ RK3572_CLKGATE_CON(18), 8, GFLAGS),
+ GATE(CLK_TIMER2, "clk_timer2", "clk_timer0_root", 0,
+ RK3572_CLKGATE_CON(18), 9, GFLAGS),
+ GATE(CLK_TIMER3, "clk_timer3", "clk_timer0_root", 0,
+ RK3572_CLKGATE_CON(18), 10, GFLAGS),
+ GATE(CLK_TIMER4, "clk_timer4", "clk_timer0_root", 0,
+ RK3572_CLKGATE_CON(18), 11, GFLAGS),
+ GATE(CLK_TIMER5, "clk_timer5", "clk_timer0_root", 0,
+ RK3572_CLKGATE_CON(18), 12, GFLAGS),
+ GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(18), 14, GFLAGS),
+ GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(19), 0, GFLAGS),
+ GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
+ RK3572_CLKGATE_CON(19), 1, GFLAGS),
+ GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(19), 2, GFLAGS),
+ GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
+ RK3572_CLKGATE_CON(19), 3, GFLAGS),
+ GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(19), 4, GFLAGS),
+ GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
+ RK3572_CLKGATE_CON(19), 5, GFLAGS),
+ GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(19), 6, GFLAGS),
+ GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
+ RK3572_CLKGATE_CON(19), 7, GFLAGS),
+ GATE(ACLK_DECOM, "aclk_decom", "aclk_decom_root", 0,
+ RK3572_CLKGATE_CON(19), 8, GFLAGS),
+ GATE(PCLK_DECOM, "pclk_decom", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(19), 9, GFLAGS),
+ COMPOSITE(DCLK_DECOM, "dclk_decom", gpll_cpll_spll_bpll_p, 0,
+ RK3572_CLKSEL_CON(84), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(19), 10, GFLAGS),
+ COMPOSITE_NODIV(CLK_TIMER1_ROOT, "clk_timer1_root", mux_100m_24m_p, 0,
+ RK3572_CLKSEL_CON(84), 7, 1, MFLAGS,
+ RK3572_CLKGATE_CON(19), 11, GFLAGS),
+ GATE(CLK_TIMER6, "clk_timer6", "clk_timer1_root", 0,
+ RK3572_CLKGATE_CON(19), 12, GFLAGS),
+ COMPOSITE(CLK_TIMER7, "clk_timer7", clk_timer7_p, 0,
+ RK3572_CLKSEL_CON(84), 13, 2, MFLAGS, 8, 5, DFLAGS,
+ RK3572_CLKGATE_CON(19), 13, GFLAGS),
+ COMPOSITE(CLK_TIMER8, "clk_timer8", clk_timer8_p, 0,
+ RK3572_CLKSEL_CON(85), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(19), 14, GFLAGS),
+ GATE(CLK_TIMER9, "clk_timer9", "clk_timer1_root", 0,
+ RK3572_CLKGATE_CON(19), 15, GFLAGS),
+ GATE(CLK_TIMER10, "clk_timer10", "clk_timer1_root", 0,
+ RK3572_CLKGATE_CON(20), 0, GFLAGS),
+ GATE(CLK_TIMER11, "clk_timer11", "clk_timer1_root", 0,
+ RK3572_CLKGATE_CON(20), 1, GFLAGS),
+ GATE(ACLK_RKDMA0, "aclk_rkdma0", "aclk_bus_root", 0,
+ RK3572_CLKGATE_CON(20), 2, GFLAGS),
+ GATE(PCLK_RKDMA0, "pclk_rkdma0", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(20), 3, GFLAGS),
+ GATE(ACLK_RKDMA1, "aclk_rkdma1", "aclk_bus_root", 0,
+ RK3572_CLKGATE_CON(20), 4, GFLAGS),
+ GATE(PCLK_RKDMA1, "pclk_rkdma1", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(20), 5, GFLAGS),
+ GATE(ACLK_RKDMA2, "aclk_rkdma2", "aclk_bus_root", 0,
+ RK3572_CLKGATE_CON(20), 6, GFLAGS),
+ GATE(PCLK_RKDMA2, "pclk_rkdma2", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(20), 7, GFLAGS),
+ GATE(ACLK_RKDMA3, "aclk_rkdma3", "aclk_bus_root", 0,
+ RK3572_CLKGATE_CON(20), 8, GFLAGS),
+ GATE(PCLK_RKDMA3, "pclk_rkdma3", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(20), 9, GFLAGS),
+ GATE(PCLK_SPINLOCK, "pclk_spinlock", "pclk_bus_root", 0,
+ RK3572_CLKGATE_CON(20), 10, GFLAGS),
+ COMPOSITE_NODIV(CLK_I3C, "clk_i3c", mux_300m_200m_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(85), 7, 3, MFLAGS,
+ RK3572_CLKGATE_CON(20), 12, GFLAGS),
+ GATE(HCLK_I3C, "hclk_i3c", "hclk_bus_root", 0,
+ RK3572_CLKGATE_CON(20), 13, GFLAGS),
+ COMPOSITE_NODIV(CLK_BUSMCU_ROOT, "clk_busmcu_root", mux_400m_200m_100m_24m_p, 0,
+ RK3572_CLKSEL_CON(85), 13, 2, MFLAGS,
+ RK3572_CLKGATE_CON(21), 0, GFLAGS),
+ GATE(CLK_BUSMCU_CORE_AON, "clk_busmcu_core_aon", "clk_busmcu_root", 0,
+ RK3572_CLKGATE_CON(21), 2, GFLAGS),
+ COMPOSITE_NOMUX(CLK_MTIME_TOGGLE_A, "clk_mtime_toggle_a", "xin24m", 0,
+ RK3572_CLKSEL_CON(86), 0, 6, DFLAGS,
+ RK3572_CLKGATE_CON(21), 4, GFLAGS),
+ GATE(CLK_DBG_TOGGLE_A, "clk_dbg_toggle_a", "clk_32k", 0,
+ RK3572_CLKGATE_CON(21), 5, GFLAGS),
+ GATE(CLK_MCU_AXI_INTEGRITY, "clk_mcu_axi_integrity", "clk_busmcu_root", 0,
+ RK3572_CLKGATE_CON(21), 6, GFLAGS),
+ GATE(PCLK_PMU2, "pclk_pmu2", "pclk_bus_root", CLK_IS_CRITICAL,
+ RK3572_CLKGATE_CON(21), 7, GFLAGS),
+ GATE(CLK_HDMITXHPD, "clk_hdmitxhpd", "xin24m", 0,
+ RK3572_CLKGATE_CON(21), 14, GFLAGS),
+ GATE(PCLK_APB2ASB_HDMITX, "pclk_apb2asb_hdmitx", "pclk_bus_root", CLK_IS_CRITICAL,
+ RK3572_CLKGATE_CON(22), 2, GFLAGS),
+ COMPOSITE_NODIV(SCLK_APB2ASB_HDMITX, "sclk_apb2asb_hdmitx", sclk_apb2asb_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(88), 7, 2, MFLAGS,
+ RK3572_CLKGATE_CON(22), 3, GFLAGS),
+ GATE(PCLK_APB2ASB_MIPICSI, "pclk_apb2asb_mipicsi", "pclk_bus_root", CLK_IS_CRITICAL,
+ RK3572_CLKGATE_CON(22), 6, GFLAGS),
+ COMPOSITE_NODIV(SCLK_APB2ASB_MIPICSI, "sclk_apb2asb_mipicsi", sclk_apb2asb_p,
+ CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(88), 11, 2, MFLAGS,
+ RK3572_CLKGATE_CON(22), 7, GFLAGS),
+ GATE(PCLK_APB2ASB_VCCIO0_3, "pclk_apb2asb_vccio0_3", "pclk_bus_root", CLK_IS_CRITICAL,
+ RK3572_CLKGATE_CON(22), 8, GFLAGS),
+ COMPOSITE_NODIV(SCLK_APB2ASB_VCCIO0_3, "sclk_apb2asb_vccio0_3", sclk_apb2asb_p,
+ CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(88), 13, 2, MFLAGS,
+ RK3572_CLKGATE_CON(22), 9, GFLAGS),
+ GATE(PCLK_APB2ASB_VCCIO1_2_4, "pclk_apb2asb_vccio1_2_4", "pclk_bus_root", CLK_IS_CRITICAL,
+ RK3572_CLKGATE_CON(22), 10, GFLAGS),
+ COMPOSITE_NODIV(SCLK_APB2ASB_VCCIO1_2_4, "sclk_apb2asb_vccio1_2_4", sclk_apb2asb_p,
+ CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(89), 0, 2, MFLAGS,
+ RK3572_CLKGATE_CON(22), 11, GFLAGS),
+ GATE(PCLK_APB2ASB_VCCIO5_6, "pclk_apb2asb_vccio5_6", "pclk_bus_root", CLK_IS_CRITICAL,
+ RK3572_CLKGATE_CON(22), 12, GFLAGS),
+ COMPOSITE_NODIV(SCLK_APB2ASB_VCCIO5_6, "sclk_apb2asb_vccio5_6", sclk_apb2asb_p,
+ CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(89), 2, 2, MFLAGS,
+ RK3572_CLKGATE_CON(22), 13, GFLAGS),
+
+ /* pd_ddr */
+ COMPOSITE(PCLK_DDR_ROOT, "pclk_ddr_root", gpll_cpll_24m_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(90), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(23), 0, GFLAGS),
+ COMPOSITE(ACLK_DDR_ROOT, "aclk_ddr_root", gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(90), 12, 1, MFLAGS, 7, 5, DFLAGS,
+ RK3572_CLKGATE_CON(23), 9, GFLAGS),
+ COMPOSITE_NODIV(LCLK_DDRSCH_BIU, "lclk_ddrsch_biu", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(90), 13, 2, MFLAGS,
+ RK3572_CLKGATE_CON(24), 11, GFLAGS),
+ COMPOSITE_NODIV(CLK_DDR_TIMER_ROOT, "clk_ddr_timer_root", mux_100m_24m_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(90), 15, 1, MFLAGS,
+ RK3572_CLKGATE_CON(25), 3, GFLAGS),
+ GATE(CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", CLK_IS_CRITICAL,
+ RK3572_CLKGATE_CON(25), 4, GFLAGS),
+ GATE(CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", CLK_IS_CRITICAL,
+ RK3572_CLKGATE_CON(25), 5, GFLAGS),
+ GATE(TCLK_DDR_WDT, "tclk_ddr_wdt", "xin24m", 0,
+ RK3572_CLKGATE_CON(25), 6, GFLAGS),
+ GATE(PCLK_WDT, "pclk_wdt", "pclk_ddr_root", 0,
+ RK3572_CLKGATE_CON(25), 7, GFLAGS),
+ GATE(PCLK_TIMER, "pclk_timer", "pclk_ddr_root", CLK_IS_CRITICAL,
+ RK3572_CLKGATE_CON(25), 8, GFLAGS),
+ COMPOSITE_NODIV(CLK_DDRMCU_ROOT, "clk_ddrmcu_root", mux_400m_200m_100m_24m_p,
+ CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(91), 6, 2, MFLAGS,
+ RK3572_CLKGATE_CON(26), 15, GFLAGS),
+ GATE(CLK_DDRMCU_CORE_AON, "clk_ddrmcu_core_aon", "clk_ddrmcu_root", CLK_IS_CRITICAL,
+ RK3572_CLKGATE_CON(27), 1, GFLAGS),
+ COMPOSITE_NOMUX(CLK_MTIME_TOGGLE_A_DDR, "clk_mtime_toggle_a_ddr", "xin24m", 0,
+ RK3572_CLKSEL_CON(91), 8, 6, DFLAGS,
+ RK3572_CLKGATE_CON(27), 3, GFLAGS),
+ GATE(CLK_DBG_TOGGLE_A_DDR, "clk_dbg_toggle_a_ddr", "clk_32k", 0,
+ RK3572_CLKGATE_CON(27), 4, GFLAGS),
+ GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr_root", 0,
+ RK3572_CLKGATE_CON(23), 1, GFLAGS),
+
+ /* pd_npu */
+ COMPOSITE(ACLK_RKNN_ROOT, "aclk_rknn_root", gpll_cpll_aupll_spll_p, 0,
+ RK3572_CLKSEL_CON(95), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(31), 0, GFLAGS),
+ GATE(ACLK_RKNN, "aclk_rknn", "aclk_rknn_root", 0,
+ RK3572_CLKGATE_CON(31), 2, GFLAGS),
+ COMPOSITE_NODIV(PCLK_RKNN_ROOT, "pclk_rknn_root", mux_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(95), 8, 2, MFLAGS,
+ RK3572_CLKGATE_CON(31), 6, GFLAGS),
+ GATE(CLK_24M_RKNN, "clk_24m_rknn", "xin24m", 0,
+ RK3572_CLKGATE_CON(31), 11, GFLAGS),
+ COMPOSITE_NODIV(CLK_NPUTIMER_ROOT, "clk_nputimer_root", mux_100m_24m_p, 0,
+ RK3572_CLKSEL_CON(95), 11, 1, MFLAGS,
+ RK3572_CLKGATE_CON(31), 12, GFLAGS),
+ GATE(CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 0,
+ RK3572_CLKGATE_CON(31), 13, GFLAGS),
+ GATE(CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 0,
+ RK3572_CLKGATE_CON(31), 14, GFLAGS),
+ GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_rknn_root", 0,
+ RK3572_CLKGATE_CON(31), 15, GFLAGS),
+ GATE(PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_rknn_root", 0,
+ RK3572_CLKGATE_CON(32), 0, GFLAGS),
+ GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0,
+ RK3572_CLKGATE_CON(32), 1, GFLAGS),
+
+ /* pd_php */
+ COMPOSITE_NODIV(PCLK_PHP0_ROOT, "pclk_php0_root", mux_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(97), 0, 2, MFLAGS,
+ RK3572_CLKGATE_CON(33), 0, GFLAGS),
+ COMPOSITE(ACLK_PHP0_ROOT, "aclk_php0_root", gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(97), 7, 1, MFLAGS, 2, 5, DFLAGS,
+ RK3572_CLKGATE_CON(33), 3, GFLAGS),
+ GATE(PCLK_PCIE1, "pclk_pcie1", "pclk_php0_root", 0,
+ RK3572_CLKGATE_CON(33), 7, GFLAGS),
+ GATE(CLK_PCIE1_AUX, "clk_pcie1_aux", "xin24m", 0,
+ RK3572_CLKGATE_CON(33), 8, GFLAGS),
+ GATE(ACLK_PCIE1_MSTR, "aclk_pcie1_mstr", "aclk_php0_root", 0,
+ RK3572_CLKGATE_CON(33), 9, GFLAGS),
+ GATE(ACLK_PCIE1_SLV, "aclk_pcie1_slv", "aclk_php0_root", 0,
+ RK3572_CLKGATE_CON(33), 10, GFLAGS),
+ GATE(ACLK_PCIE1_DBI, "aclk_pcie1_dbi", "aclk_php0_root", 0,
+ RK3572_CLKGATE_CON(33), 11, GFLAGS),
+ GATE(PCLK_PCIE0, "pclk_pcie0", "pclk_php0_root", 0,
+ RK3572_CLKGATE_CON(34), 3, GFLAGS),
+ GATE(CLK_PCIE0_AUX, "clk_pcie0_aux", "xin24m", 0,
+ RK3572_CLKGATE_CON(34), 4, GFLAGS),
+ GATE(ACLK_PCIE0_MSTR, "aclk_pcie0_mstr", "aclk_php0_root", 0,
+ RK3572_CLKGATE_CON(34), 5, GFLAGS),
+ GATE(ACLK_PCIE0_SLV, "aclk_pcie0_slv", "aclk_php0_root", 0,
+ RK3572_CLKGATE_CON(34), 6, GFLAGS),
+ GATE(ACLK_PCIE0_DBI, "aclk_pcie0_dbi", "aclk_php0_root", 0,
+ RK3572_CLKGATE_CON(34), 7, GFLAGS),
+ GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_php0_root", 0,
+ RK3572_CLKGATE_CON(34), 9, GFLAGS),
+ GATE(CLK_REF_USB3OTG1, "clk_ref_usb3otg1", "xin24m", 0,
+ RK3572_CLKGATE_CON(34), 10, GFLAGS),
+ GATE(CLK_SUSPEND_USB3OTG1, "clk_suspend_usb3otg1", "xin24m", 0,
+ RK3572_CLKGATE_CON(34), 11, GFLAGS),
+ GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php0_root", 0,
+ RK3572_CLKGATE_CON(34), 12, GFLAGS),
+ GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php0_root", 0,
+ RK3572_CLKGATE_CON(34), 13, GFLAGS),
+ COMPOSITE(ACLK_UFS_ROOT, "aclk_ufs_root", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(97), 15, 1, MFLAGS, 10, 5, DFLAGS,
+ RK3572_CLKGATE_CON(34), 14, GFLAGS),
+ GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_php0_root", 0,
+ RK3572_CLKGATE_CON(34), 15, GFLAGS),
+ GATE(CLK_REF_USB3OTG0, "clk_ref_usb3otg0", "xin24m", 0,
+ RK3572_CLKGATE_CON(35), 0, GFLAGS),
+ GATE(CLK_SUSPEND_USB3OTG0, "clk_suspend_usb3otg0", "xin24m", 0,
+ RK3572_CLKGATE_CON(35), 1, GFLAGS),
+ GATE(ACLK_UFS_SYS, "aclk_ufs_sys", "aclk_ufs_root", 0,
+ RK3572_CLKGATE_CON(35), 3, GFLAGS),
+ COMPOSITE(CLK_GMAC0_PTP_REF_PRE, "clk_gmac0_ptp_ref_pre", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(98), 5, 1, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(35), 5, GFLAGS),
+ COMPOSITE_NODIV(CLK_GMAC0_PTP_REF_SRC, "clk_gmac0_ptp_ref_src", clk_gmac0_ptp_ref_src_p, 0,
+ RK3572_CLKSEL_CON(98), 6, 1, MFLAGS,
+ RK3572_CLKGATE_CON(35), 7, GFLAGS),
+ COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(100), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RK3572_CLKGATE_CON(37), 0, GFLAGS),
+ GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", 0,
+ RK3572_CLKGATE_CON(37), 1, GFLAGS),
+ GATE(ACLK_SATA0, "aclk_sata0", "aclk_php0_root", 0,
+ RK3572_CLKGATE_CON(37), 2, GFLAGS),
+ COMPOSITE(CLK_RXOOB1, "clk_rxoob1", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(100), 15, 1, MFLAGS, 8, 7, DFLAGS,
+ RK3572_CLKGATE_CON(37), 3, GFLAGS),
+ GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", 0,
+ RK3572_CLKGATE_CON(37), 4, GFLAGS),
+ GATE(ACLK_SATA1, "aclk_sata1", "aclk_php0_root", 0,
+ RK3572_CLKGATE_CON(37), 5, GFLAGS),
+ COMPOSITE(CLK_EEE_XPCS, "clk_eee_xpcs", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(101), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RK3572_CLKGATE_CON(37), 6, GFLAGS),
+ GATE(PCLK_XPCS, "pclk_xpcs", "pclk_php0_root", 0,
+ RK3572_CLKGATE_CON(37), 7, GFLAGS),
+
+ /* pd_nvm */
+ COMPOSITE_NODIV(HCLK_NVM0_ROOT, "hclk_nvm0_root", mux_200m_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(113), 0, 2, MFLAGS,
+ RK3572_CLKGATE_CON(42), 0, GFLAGS),
+ COMPOSITE(ACLK_NVM0_ROOT, "aclk_nvm0_root", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(113), 7, 1, MFLAGS, 2, 5, DFLAGS,
+ RK3572_CLKGATE_CON(42), 1, GFLAGS),
+ COMPOSITE_NODIV(PCLK_NVM0_ROOT, "pclk_nvm0_root", mux_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(113), 8, 2, MFLAGS,
+ RK3572_CLKGATE_CON(42), 2, GFLAGS),
+ COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", gpll_cpll_24m_p, 0,
+ RK3572_CLKSEL_CON(114), 6, 2, MFLAGS, 0, 6, DFLAGS,
+ RK3572_CLKGATE_CON(42), 7, GFLAGS),
+ GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm0_root", 0,
+ RK3572_CLKGATE_CON(42), 8, GFLAGS),
+ GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm0_root", 0,
+ RK3572_CLKGATE_CON(42), 9, GFLAGS),
+ COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", mux_200m_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(114), 8, 2, MFLAGS,
+ RK3572_CLKGATE_CON(42), 10, GFLAGS),
+ GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
+ RK3572_CLKGATE_CON(42), 11, GFLAGS),
+ COMPOSITE(CLK_GMAC1_PTP_REF_SRC, "clk_gmac1_ptp_ref_src", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(114), 15, 1, MFLAGS, 10, 5, DFLAGS,
+ RK3572_CLKGATE_CON(42), 12, GFLAGS),
+ COMPOSITE_NODIV(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac1_ptp_ref_p, 0,
+ RK3572_CLKSEL_CON(115), 0, 1, MFLAGS,
+ RK3572_CLKGATE_CON(42), 13, GFLAGS),
+ GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_nvm0_root", 0,
+ RK3572_CLKGATE_CON(42), 14, GFLAGS),
+ GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_nvm0_root", 0,
+ RK3572_CLKGATE_CON(42), 15, GFLAGS),
+ COMPOSITE(SCLK_FSPI0_X2, "sclk_fspi0_x2", gpll_cpll_spll_aupll_24m_p, 0,
+ RK3572_CLKSEL_CON(115), 7, 3, MFLAGS, 1, 6, DFLAGS,
+ RK3572_CLKGATE_CON(43), 0, GFLAGS),
+ GATE(HCLK_FSPI0, "hclk_fspi0", "hclk_nvm0_root", 0,
+ RK3572_CLKGATE_CON(43), 1, GFLAGS),
+ COMPOSITE(CCLK_SRC_SDMMC1, "cclk_src_sdmmc1", gpll_cpll_24m_p, 0,
+ RK3572_CLKSEL_CON(116), 6, 2, MFLAGS, 0, 6, DFLAGS,
+ RK3572_CLKGATE_CON(43), 2, GFLAGS),
+ GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_nvm0_root", 0,
+ RK3572_CLKGATE_CON(43), 3, GFLAGS),
+ COMPOSITE(ACLK_DSMC_ROOT, "aclk_dsmc_root", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(44), 0, GFLAGS),
+ GATE(ACLK_DSMC, "aclk_dsmc", "aclk_dsmc_root", 0,
+ RK3572_CLKGATE_CON(44), 2, GFLAGS),
+ COMPOSITE_NODIV(HCLK_DSMC_ROOT, "hclk_dsmc_root", mux_200m_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(118), 6, 2, MFLAGS,
+ RK3572_CLKGATE_CON(44), 3, GFLAGS),
+ GATE(HCLK_DSMC, "hclk_dsmc", "hclk_dsmc_root", 0,
+ RK3572_CLKGATE_CON(44), 5, GFLAGS),
+ COMPOSITE_NODIV(PCLK_DSMC_ROOT, "pclk_dsmc_root", mux_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(118), 8, 2, MFLAGS,
+ RK3572_CLKGATE_CON(44), 6, GFLAGS),
+ GATE(PCLK_DSMC, "pclk_dsmc", "pclk_dsmc_root", 0,
+ RK3572_CLKGATE_CON(44), 8, GFLAGS),
+ COMPOSITE(CLK_DSMC_SYS, "clk_dsmc_sys", gpll_cpll_24m_p, 0,
+ RK3572_CLKSEL_CON(119), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(44), 9, GFLAGS),
+ COMPOSITE_NODIV(HCLK_NVM1_ROOT, "hclk_nvm1_root", mux_200m_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(120), 0, 2, MFLAGS,
+ RK3572_CLKGATE_CON(45), 0, GFLAGS),
+ COMPOSITE_NODIV(PCLK_NVM1_ROOT, "pclk_nvm1_root", mux_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(120), 8, 2, MFLAGS,
+ RK3572_CLKGATE_CON(45), 2, GFLAGS),
+ COMPOSITE(CCLK_SRC_SDMMC0, "cclk_src_sdmmc0", gpll_cpll_24m_p, 0,
+ RK3572_CLKSEL_CON(121), 6, 2, MFLAGS, 0, 6, DFLAGS,
+ RK3572_CLKGATE_CON(45), 7, GFLAGS),
+ GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_nvm1_root", 0,
+ RK3572_CLKGATE_CON(45), 8, GFLAGS),
+ COMPOSITE(SCLK_FSPI1_X2, "sclk_fspi1_x2", gpll_cpll_spll_aupll_24m_p, 0,
+ RK3572_CLKSEL_CON(122), 6, 3, MFLAGS, 0, 6, DFLAGS,
+ RK3572_CLKGATE_CON(45), 11, GFLAGS),
+ GATE(HCLK_FSPI1, "hclk_fspi1", "hclk_nvm1_root", 0,
+ RK3572_CLKGATE_CON(45), 12, GFLAGS),
+
+ /* pd_phpphy */
+ COMPOSITE_NODIV(PCLK_PHPSUBSYS_ROOT, "pclk_phpsubsys_root", pclk_phpsubsys_root_p,
+ CLK_IS_CRITICAL,
+ RK3572_PHP_CLKSEL_CON(0), 0, 1, MFLAGS,
+ RK3572_PHP_CLKGATE_CON(0), 2, GFLAGS),
+ GATE(PCLK_PCIE2_COMBOPHY0, "pclk_pcie2_combophy0", "pclk_phpsubsys_root", 0,
+ RK3572_PHP_CLKGATE_CON(0), 4, GFLAGS),
+ GATE(PCLK_PCIE2_COMBOPHY1, "pclk_pcie2_combophy1", "pclk_phpsubsys_root", 0,
+ RK3572_PHP_CLKGATE_CON(0), 6, GFLAGS),
+ GATE(PCLK_MPHY, "pclk_mphy", "pclk_phpsubsys_root", 0,
+ RK3572_PHP_CLKGATE_CON(0), 10, GFLAGS),
+ GATE(PCLK_PCIEPHY2, "pclk_pciephy2", "pclk_phpsubsys_root", 0,
+ RK3572_PHP_CLKGATE_CON(0), 14, GFLAGS),
+ COMPOSITE(SCLK_APB2ASB_USBMPHY_PHPPHY, "sclk_apb2asb_usbmphy_phpphy", sclk_apb2asb_p,
+ CLK_IS_CRITICAL,
+ RK3572_PHP_CLKSEL_CON(0), 6, 2, MFLAGS, 1, 5, DFLAGS,
+ RK3572_PHP_CLKGATE_CON(1), 0, GFLAGS),
+ GATE(PCLK_APB2ASB_USBMPHY_PHPPHY, "pclk_apb2asb_usbmphy_phpphy", "pclk_phpsubsys_root",
+ CLK_IS_CRITICAL,
+ RK3572_PHP_CLKGATE_CON(1), 1, GFLAGS),
+ FACTOR_GATE(CLK_CPLL_DIV10_PHPPHY, "clk_cpll_div10_phpphy", "clk_gpll_div6",
+ CLK_IS_CRITICAL, 1, 2,
+ RK3572_PHP_CLKGATE_CON(1), 2, GFLAGS),
+ GATE(CLK_PHPPHY_REF, "clk_phpphy_ref", "xin24m", 0,
+ RK3572_PHP_CLKGATE_CON(1), 3, GFLAGS),
+ COMPOSITE_NOMUX(CLK_PCIE_100M_SRC, "clk_pcie_100m_src", "ppll", 0,
+ RK3572_PHP_CLKSEL_CON(2), 0, 5, DFLAGS,
+ RK3572_PHP_CLKGATE_CON(2), 1, GFLAGS),
+ COMPOSITE_NOMUX(CLK_PCIE_100M_NDUTY_SRC, "clk_pcie_100m_nduty_src", "ppll", 0,
+ RK3572_PHP_CLKSEL_CON(2), 5, 5, DFLAGS,
+ RK3572_PHP_CLKGATE_CON(2), 2, GFLAGS),
+ COMPOSITE_NODIV(CLK_REF_PCIEPHY2, "clk_ref_pciephy2", clk_ref_pciephy_p, 0,
+ RK3572_PHP_CLKSEL_CON(2), 10, 2, MFLAGS,
+ RK3572_PHP_CLKGATE_CON(2), 4, GFLAGS),
+ COMPOSITE_NODIV(CLK_REF_PCIE0_INNER_PHY, "clk_ref_pcie0_inner_phy", clk_ref_pciephy_p, 0,
+ RK3572_PHP_CLKSEL_CON(2), 12, 2, MFLAGS,
+ RK3572_PHP_CLKGATE_CON(2), 5, GFLAGS),
+ COMPOSITE_NODIV(CLK_REF_PCIE1_INNER_PHY, "clk_ref_pcie1_inner_phy", clk_ref_pciephy_p, 0,
+ RK3572_PHP_CLKSEL_CON(2), 14, 2, MFLAGS,
+ RK3572_PHP_CLKGATE_CON(2), 8, GFLAGS),
+ COMPOSITE_NOMUX(CLK_REF_MPHY_26M, "clk_ref_mphy_26m", "ppll", 0,
+ RK3572_PHP_CLKSEL_CON(3), 0, 8, DFLAGS,
+ RK3572_PHP_CLKGATE_CON(2), 9, GFLAGS),
+ COMPOSITE_NOMUX(REF_CLK_FROM_PPLL, "ref_clk_from_ppll", "ppll", 0,
+ RK3572_PHP_CLKSEL_CON(3), 8, 8, DFLAGS,
+ RK3572_PHP_CLKGATE_CON(2), 10, GFLAGS),
+
+ /* pd_rkvdec */
+ COMPOSITE_NODIV(HCLK_RKVDEC_ROOT, "hclk_rkvdec_root", mux_200m_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(130), 0, 2, MFLAGS,
+ RK3572_CLKGATE_CON(50), 0, GFLAGS),
+ GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_root", 0,
+ RK3572_CLKGATE_CON(50), 3, GFLAGS),
+ COMPOSITE(ACLK_RKVDEC_ROOT, "aclk_rkvdec_root", gpll_cpll_spll_bpll_p, 0,
+ RK3572_CLKSEL_CON(131), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(50), 7, GFLAGS),
+ COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_bpll_p, 0,
+ RK3572_CLKSEL_CON(131), 12, 2, MFLAGS, 7, 5, DFLAGS,
+ RK3572_CLKGATE_CON(50), 8, GFLAGS),
+ GATE(CLK_RKVDEC_CORE, "clk_rkvdec_core", "aclk_rkvdec_root", 0,
+ RK3572_CLKGATE_CON(50), 9, GFLAGS),
+ COMPOSITE_NODIV(PCLK_VDEC_ROOT, "pclk_vdec_root", mux_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(131), 14, 2, MFLAGS,
+ RK3572_CLKGATE_CON(50), 13, GFLAGS),
+
+ /* pd_vo */
+ COMPOSITE_NODIV(PCLK_VOSUBSYS_ROOT, "pclk_vosubsys_root", mux_100m_50m_24m_p,
+ CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(135), 0, 2, MFLAGS,
+ RK3572_CLKGATE_CON(52), 0, GFLAGS),
+ GATE(PCLK_APB2ASB_MIPI_HDMI_SUBVO, "pclk_apb2asb_mipi_hdmi_subvo", "pclk_vosubsys_root",
+ CLK_IS_CRITICAL,
+ RK3572_CLKGATE_CON(52), 1, GFLAGS),
+ COMPOSITE_NODIV(SCLK_APB2ASB_MIPI_HDMI_SUBVO, "sclk_apb2asb_mipi_hdmi_subvo",
+ sclk_apb2asb_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(135), 2, 2, MFLAGS,
+ RK3572_CLKGATE_CON(52), 2, GFLAGS),
+ GATE(PCLK_APB2ASB_VCCIO0_3_SUBVO, "pclk_apb2asb_vccio0_3_subvo", "pclk_vosubsys_root",
+ CLK_IS_CRITICAL,
+ RK3572_CLKGATE_CON(52), 7, GFLAGS),
+ COMPOSITE_NODIV(SCLK_APB2ASB_VCCIO0_3_SUBVO, "sclk_apb2asb_vccio0_3_subvo",
+ sclk_apb2asb_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(135), 8, 2, MFLAGS,
+ RK3572_CLKGATE_CON(52), 8, GFLAGS),
+ GATE(PCLK_HDPTXPHY, "pclk_hdptxphy", "pclk_vosubsys_root", 0,
+ RK3572_CLKGATE_CON(52), 9, GFLAGS),
+ GATE(PCLK_MIPI_DPHY0, "pclk_mipi_dphy0", "pclk_vosubsys_root", 0,
+ RK3572_CLKGATE_CON(52), 11, GFLAGS),
+ GATE(CLK_VOSUBSYS_REF, "clk_vosubsys_ref", "xin24m", 0,
+ RK3572_CLKGATE_CON(53), 0, GFLAGS),
+ GATE(PCLK_IOC_SUBVO, "pclk_ioc_subvo", "pclk_vosubsys_root", CLK_IS_CRITICAL,
+ RK3572_CLKGATE_CON(53), 3, GFLAGS),
+
+ /* pd_vi */
+ COMPOSITE_NODIV(PCLK_VISUBSYS_ROOT, "pclk_visubsys_root", mux_100m_50m_24m_p,
+ CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(137), 0, 2, MFLAGS,
+ RK3572_CLKGATE_CON(54), 0, GFLAGS),
+ GATE(PCLK_APB2ASB_VCCIO1_2_4_SUBVI, "pclk_apb2asb_vccio1_2_4_subvi",
+ "pclk_visubsys_root", CLK_IS_CRITICAL,
+ RK3572_CLKGATE_CON(54), 1, GFLAGS),
+ COMPOSITE_NODIV(SCLK_APB2ASB_VCCIO1_2_4_SUBVI, "sclk_apb2asb_vccio1_2_4_subvi",
+ sclk_apb2asb_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(137), 2, 2, MFLAGS,
+ RK3572_CLKGATE_CON(54), 2, GFLAGS),
+ GATE(PCLK_APB2ASB_CSIPHY_SUBVI, "pclk_apb2asb_csiphy_subvi", "pclk_visubsys_root",
+ CLK_IS_CRITICAL,
+ RK3572_CLKGATE_CON(54), 3, GFLAGS),
+ COMPOSITE_NODIV(SCLK_APB2ASB_CSIPHY_SUBVI, "sclk_apb2asb_csiphy_subvi", sclk_apb2asb_p,
+ CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(137), 4, 2, MFLAGS,
+ RK3572_CLKGATE_CON(54), 4, GFLAGS),
+ GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_visubsys_root", 0,
+ RK3572_CLKGATE_CON(54), 5, GFLAGS),
+ GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_visubsys_root", 0,
+ RK3572_CLKGATE_CON(54), 7, GFLAGS),
+ GATE(PCLK_IOC_SUBVI, "pclk_ioc_subvi", "pclk_visubsys_root", CLK_IS_CRITICAL,
+ RK3572_CLKGATE_CON(54), 9, GFLAGS),
+ GATE(CLK_SDMMC_SWITCH_24M, "clk_sdmmc_switch_24m", "xin24m", 0,
+ RK3572_CLKGATE_CON(54), 13, GFLAGS),
+
+ COMPOSITE_NODIV(PCLK_DSMCSUBSYS_ROOT, "pclk_dsmcsubsys_root", mux_100m_50m_24m_p,
+ CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(139), 0, 2, MFLAGS,
+ RK3572_CLKGATE_CON(56), 0, GFLAGS),
+ GATE(PCLK_APB2ASB_VCCIO5_6_SUBDSMC, "pclk_apb2asb_vccio5_6_subdsmc",
+ "pclk_dsmcsubsys_root", CLK_IS_CRITICAL,
+ RK3572_CLKGATE_CON(56), 3, GFLAGS),
+ COMPOSITE_NODIV(SCLK_APB2ASB_VCCIO5_6_SUBDSMC, "sclk_apb2asb_vccio5_6_subdsmc",
+ sclk_apb2asb_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(139), 9, 2, MFLAGS,
+ RK3572_CLKGATE_CON(56), 4, GFLAGS),
+
+ /* pd_vpu */
+ COMPOSITE(ACLK_IMG_ROOT, "aclk_img_root", gpll_spll_cpll_bpll_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(141), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(57), 0, GFLAGS),
+ COMPOSITE_NODIV(ACLK_IMG_MID_ROOT, "aclk_img_mid_root", mux_600m_400m_300m_24m_p,
+ CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(141), 7, 2, MFLAGS,
+ RK3572_CLKGATE_CON(57), 1, GFLAGS),
+ COMPOSITE_NODIV(HCLK_IMG_ROOT, "hclk_img_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(141), 9, 2, MFLAGS,
+ RK3572_CLKGATE_CON(57), 2, GFLAGS),
+ COMPOSITE(ACLK_JPEG_ROOT, "aclk_jpeg_root", gpll_cpll_aupll_spll_p, 0,
+ RK3572_CLKSEL_CON(142), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(57), 3, GFLAGS),
+ COMPOSITE_NODIV(ACLK_IMG_LOW_ROOT, "aclk_img_low_root", mux_400m_200m_100m_24m_p,
+ CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(142), 7, 2, MFLAGS,
+ RK3572_CLKGATE_CON(57), 4, GFLAGS),
+ COMPOSITE_NODIV(PCLK_IMG_ROOT, "pclk_img_root", mux_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(142), 9, 2, MFLAGS,
+ RK3572_CLKGATE_CON(57), 6, GFLAGS),
+ GATE(HCLK_RGA2E_0, "hclk_rga2e_0", "hclk_img_root", 0,
+ RK3572_CLKGATE_CON(58), 0, GFLAGS),
+ GATE(ACLK_RGA2E_0, "aclk_rga2e_0", "aclk_img_root", 0,
+ RK3572_CLKGATE_CON(58), 1, GFLAGS),
+ COMPOSITE(CLK_CORE_RGA2E_0, "clk_core_rga2e_0", gpll_spll_cpll_bpll_p, 0,
+ RK3572_CLKSEL_CON(143), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(58), 2, GFLAGS),
+ GATE(ACLK_JPEG, "aclk_jpeg", "aclk_jpeg_root", 0,
+ RK3572_CLKGATE_CON(58), 3, GFLAGS),
+ GATE(HCLK_JPEG, "hclk_jpeg", "hclk_img_root", 0,
+ RK3572_CLKGATE_CON(58), 4, GFLAGS),
+ GATE(HCLK_VDPP, "hclk_vdpp", "hclk_img_root", 0,
+ RK3572_CLKGATE_CON(58), 5, GFLAGS),
+ GATE(ACLK_VDPP, "aclk_vdpp", "aclk_img_mid_root", 0,
+ RK3572_CLKGATE_CON(58), 6, GFLAGS),
+ COMPOSITE(CLK_CORE_VDPP, "clk_core_vdpp", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(143), 12, 1, MFLAGS, 7, 5, DFLAGS,
+ RK3572_CLKGATE_CON(58), 7, GFLAGS),
+ COMPOSITE_NODIV(DCLK_EBC_SRC_TOP, "dclk_ebc_src_top", gpll_cpll_vpll_aupll_bpll_24m_p,
+ CLK_SET_RATE_NO_REPARENT,
+ RK3572_CLKSEL_CON(143), 13, 3, MFLAGS,
+ RK3572_CLKGATE_CON(58), 10, GFLAGS),
+ COMPOSITE_NOMUX(DCLK_EBC_INT_SRC, "dclk_ebc_int_src", "dclk_ebc_src_top",
+ CLK_SET_RATE_PARENT,
+ RK3572_CLKSEL_CON(144), 0, 9, DFLAGS,
+ RK3572_CLKGATE_CON(58), 11, GFLAGS),
+ COMPOSITE_FRACMUX(DCLK_EBC_FRAC_SRC, "dclk_ebc_frac_src", "dclk_ebc_src_top", 0,
+ RK3572_CLKSEL_CON(145), 0,
+ RK3572_CLKGATE_CON(58), 12, GFLAGS, NULL),
+ GATE(HCLK_EBC, "hclk_ebc", "hclk_img_root", 0,
+ RK3572_CLKGATE_CON(58), 13, GFLAGS),
+ GATE(ACLK_EBC, "aclk_ebc", "aclk_img_low_root", 0,
+ RK3572_CLKGATE_CON(58), 14, GFLAGS),
+ COMPOSITE_NODIV(DCLK_EBC, "dclk_ebc", dclk_ebc_p,
+ CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ RK3572_CLKSEL_CON(146), 0, 1, MFLAGS,
+ RK3572_CLKGATE_CON(58), 15, GFLAGS),
+
+ /* pd_venc */
+ COMPOSITE_NODIV(HCLK_RKVENC_ROOT, "hclk_rkvenc_root", mux_200m_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(148), 0, 2, MFLAGS,
+ RK3572_CLKGATE_CON(60), 0, GFLAGS),
+ COMPOSITE(ACLK_RKVENC_ROOT, "aclk_rkvenc_root", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(148), 7, 1, MFLAGS, 2, 5, DFLAGS,
+ RK3572_CLKGATE_CON(60), 1, GFLAGS),
+ GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_root", 0,
+ RK3572_CLKGATE_CON(60), 4, GFLAGS),
+ GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_root", 0,
+ RK3572_CLKGATE_CON(60), 5, GFLAGS),
+ COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_spll_bpll_p, 0,
+ RK3572_CLKSEL_CON(148), 13, 2, MFLAGS, 8, 5, DFLAGS,
+ RK3572_CLKGATE_CON(60), 6, GFLAGS),
+
+ /* pd_vi */
+ COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_spll_isppvtpll_bpll_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(154), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(63), 0, GFLAGS),
+ COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", hclk_vi_root_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(154), 7, 2, MFLAGS,
+ RK3572_CLKGATE_CON(63), 1, GFLAGS),
+ COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(154), 9, 2, MFLAGS,
+ RK3572_CLKGATE_CON(63), 2, GFLAGS),
+ COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(155), 5, 1, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(63), 6, GFLAGS),
+ GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0,
+ RK3572_CLKGATE_CON(63), 7, GFLAGS),
+ GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0,
+ RK3572_CLKGATE_CON(63), 8, GFLAGS),
+ COMPOSITE(CLK_ISP_CORE, "clk_isp_core", gpll_spll_isppvtpll_bpll_p, 0,
+ RK3572_CLKSEL_CON(155), 11, 2, MFLAGS, 6, 5, DFLAGS,
+ RK3572_CLKGATE_CON(63), 9, GFLAGS),
+ GATE(CLK_ISP_CORE_MARVIN, "clk_isp_core_marvin", "clk_isp_core", 0,
+ RK3572_CLKGATE_CON(63), 10, GFLAGS),
+ GATE(CLK_ISP_CORE_VICAP, "clk_isp_core_vicap", "clk_isp_core", 0,
+ RK3572_CLKGATE_CON(63), 11, GFLAGS),
+ GATE(ACLK_ISP, "aclk_isp", "aclk_vi_root", 0,
+ RK3572_CLKGATE_CON(63), 12, GFLAGS),
+ GATE(HCLK_ISP, "hclk_isp", "hclk_vi_root", 0,
+ RK3572_CLKGATE_CON(63), 13, GFLAGS),
+ GATE(ACLK_VPSS, "aclk_vpss", "aclk_vi_root", 0,
+ RK3572_CLKGATE_CON(63), 15, GFLAGS),
+ GATE(HCLK_VPSS, "hclk_vpss", "hclk_vi_root", 0,
+ RK3572_CLKGATE_CON(64), 0, GFLAGS),
+ GATE(CLK_CORE_VPSS, "clk_core_vpss", "clk_isp_core", 0,
+ RK3572_CLKGATE_CON(64), 1, GFLAGS),
+ GATE(PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 0,
+ RK3572_CLKGATE_CON(64), 4, GFLAGS),
+ GATE(PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 0,
+ RK3572_CLKGATE_CON(64), 5, GFLAGS),
+ GATE(PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 0,
+ RK3572_CLKGATE_CON(64), 6, GFLAGS),
+ GATE(PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 0,
+ RK3572_CLKGATE_CON(64), 7, GFLAGS),
+ GATE(DCLK_VICAP_CSIHOST0, "dclk_vicap_csihost0", "dclk_vicap", 0,
+ RK3572_CLKGATE_CON(64), 10, GFLAGS),
+ GATE(DCLK_VICAP_CSIHOST1, "dclk_vicap_csihost1", "dclk_vicap", 0,
+ RK3572_CLKGATE_CON(64), 11, GFLAGS),
+ GATE(DCLK_VICAP_CSIHOST2, "dclk_vicap_csihost2", "dclk_vicap", 0,
+ RK3572_CLKGATE_CON(64), 12, GFLAGS),
+ GATE(DCLK_VICAP_CSIHOST3, "dclk_vicap_csihost3", "dclk_vicap", 0,
+ RK3572_CLKGATE_CON(64), 13, GFLAGS),
+ COMPOSITE_NOMUX(ACLK_VI_ROOT_INTER, "aclk_vi_root_inter", "aclk_vi_root", 0,
+ RK3572_CLKSEL_CON(156), 8, 3, DFLAGS,
+ RK3572_CLKGATE_CON(65), 4, GFLAGS),
+
+ /* pd_vop */
+ COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_aupll_spll_bpll_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(174), 5, 3, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(74), 0, GFLAGS),
+ COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(174), 10, 2, MFLAGS,
+ RK3572_CLKGATE_CON(74), 2, GFLAGS),
+ COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(174), 12, 2, MFLAGS,
+ RK3572_CLKGATE_CON(74), 3, GFLAGS),
+ GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0,
+ RK3572_CLKGATE_CON(74), 8, GFLAGS),
+ GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0,
+ RK3572_CLKGATE_CON(74), 9, GFLAGS),
+ COMPOSITE(DCLK_VP0_SRC, "dclk_vp0_src", gpll_cpll_vpll_bpll_p, CLK_SET_RATE_NO_REPARENT,
+ RK3572_CLKSEL_CON(175), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(74), 10, GFLAGS),
+ COMPOSITE(DCLK_VP1_SRC, "dclk_vp1_src", gpll_cpll_vpll_bpll_p, CLK_SET_RATE_NO_REPARENT,
+ RK3572_CLKSEL_CON(176), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(74), 11, GFLAGS),
+ COMPOSITE_NODIV(DCLK_VP0, "dclk_vp0", dclk_vp0_p,
+ CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ RK3572_CLKSEL_CON(177), 11, 1, MFLAGS,
+ RK3572_CLKGATE_CON(74), 13, GFLAGS),
+ COMPOSITE_NODIV(DCLK_VP1, "dclk_vp1", dclk_vp1_p,
+ CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ RK3572_CLKSEL_CON(177), 12, 1, MFLAGS,
+ RK3572_CLKGATE_CON(75), 0, GFLAGS),
+ GATE(PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vo_root", 0,
+ RK3572_CLKGATE_CON(78), 1, GFLAGS),
+
+ /* pd_vo */
+ COMPOSITE(ACLK_VO_ROOT, "aclk_vo_root", gpll_cpll_bpll_p, 0,
+ RK3572_CLKSEL_CON(185), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(78), 5, GFLAGS),
+ COMPOSITE_NODIV(HCLK_VO_ROOT, "hclk_vo_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(185), 7, 2, MFLAGS,
+ RK3572_CLKGATE_CON(78), 6, GFLAGS),
+ COMPOSITE_NODIV(PCLK_VO_ROOT, "pclk_vo_root", mux_150m_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(185), 11, 2, MFLAGS,
+ RK3572_CLKGATE_CON(78), 8, GFLAGS),
+ GATE(PCLK_HDCP0_TRNG_NS, "pclk_hdcp0_trng_ns", "pclk_vo_root", 0,
+ RK3572_CLKGATE_CON(79), 0, GFLAGS),
+ GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_vo_root", 0,
+ RK3572_CLKGATE_CON(79), 1, GFLAGS),
+ GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo_root", 0,
+ RK3572_CLKGATE_CON(79), 2, GFLAGS),
+ GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo_root", 0,
+ RK3572_CLKGATE_CON(79), 3, GFLAGS),
+ GATE(CLK_TRNG0_SKP, "clk_trng0_skp", "aclk_hdcp0", 0,
+ RK3572_CLKGATE_CON(79), 9, GFLAGS),
+ GATE(PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo_root", 0,
+ RK3572_CLKGATE_CON(79), 14, GFLAGS),
+ COMPOSITE(CLK_HDMITX0_EARC, "clk_hdmitx0_earc", gpll_cpll_p, 0,
+ RK3572_CLKSEL_CON(188), 15, 1, MFLAGS, 10, 5, DFLAGS,
+ RK3572_CLKGATE_CON(79), 15, GFLAGS),
+ GATE(CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_vo_root", 0,
+ RK3572_CLKGATE_CON(80), 0, GFLAGS),
+ GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo_root", 0,
+ RK3572_CLKGATE_CON(80), 2, GFLAGS),
+ GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0,
+ RK3572_CLKGATE_CON(80), 3, GFLAGS),
+ COMPOSITE_NODIV(CLK_EDP0_200M, "clk_edp0_200m", mux_200m_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(189), 0, 2, MFLAGS,
+ RK3572_CLKGATE_CON(80), 4, GFLAGS),
+ COMPOSITE(MCLK_SAI4_SRC, "mclk_sai4_src", mux_24m_frac_int_mclk4_p, 0,
+ RK3572_CLKSEL_CON(189), 10, 4, MFLAGS, 2, 8, DFLAGS,
+ RK3572_CLKGATE_CON(80), 5, GFLAGS),
+ COMPOSITE_NODIV(MCLK_SAI4, "mclk_sai4", mclk_sai4_p, CLK_SET_RATE_PARENT,
+ RK3572_CLKSEL_CON(189), 14, 1, MFLAGS,
+ RK3572_CLKGATE_CON(80), 6, GFLAGS),
+ GATE(HCLK_SAI4, "hclk_sai4", "hclk_vo_root", 0,
+ RK3572_CLKGATE_CON(80), 7, GFLAGS),
+ COMPOSITE(MCLK_SAI5_SRC, "mclk_sai5_src", mux_24m_frac_int_mclk4_p, 0,
+ RK3572_CLKSEL_CON(190), 8, 4, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(80), 8, GFLAGS),
+ COMPOSITE_NODIV(MCLK_SAI5, "mclk_sai5", mclk_sai5_p, CLK_SET_RATE_PARENT,
+ RK3572_CLKSEL_CON(190), 12, 1, MFLAGS,
+ RK3572_CLKGATE_CON(80), 9, GFLAGS),
+ GATE(HCLK_SAI5, "hclk_sai5", "hclk_vo_root", 0,
+ RK3572_CLKGATE_CON(80), 10, GFLAGS),
+ GATE(HCLK_SPDIF_TX2, "hclk_spdif_tx2", "hclk_vo_root", 0,
+ RK3572_CLKGATE_CON(80), 11, GFLAGS),
+ COMPOSITE(MCLK_SPDIF_TX2_SRC, "mclk_spdif_tx2_src", mux_24m_frac_int_mclk4_p, 0,
+ RK3572_CLKSEL_CON(191), 8, 4, MFLAGS, 0, 8, DFLAGS,
+ RK3572_CLKGATE_CON(80), 12, GFLAGS),
+ COMPOSITE_NODIV(MCLK_SPDIF_TX2, "mclk_spdif_tx2", mclk_spdif_tx2_p, CLK_SET_RATE_PARENT,
+ RK3572_CLKSEL_CON(191), 12, 1, MFLAGS,
+ RK3572_CLKGATE_CON(80), 13, GFLAGS),
+ GATE(HCLK_SPDIF_RX1, "hclk_spdif_rx1", "hclk_vo_root", 0,
+ RK3572_CLKGATE_CON(80), 14, GFLAGS),
+ COMPOSITE(MCLK_SPDIF_RX1, "mclk_spdif_rx1", gpll_cpll_aupll_p, 0,
+ RK3572_CLKSEL_CON(192), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(80), 15, GFLAGS),
+ GATE(CLK_SAI4_MCLKOUT, "clk_sai4_mclkout", "mclk_sai4", 0,
+ RK3572_CLKGATE_CON(81), 12, GFLAGS),
+
+ /* pd_gpu */
+ COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", gpll_cpll_aupll_spll_bpll_p, 0,
+ RK3572_CLKSEL_CON(202), 5, 3, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(84), 1, GFLAGS),
+ GATE(CLK_GPU, "clk_gpu", "clk_gpu_src", 0,
+ RK3572_CLKGATE_CON(84), 3, GFLAGS),
+ COMPOSITE_NOMUX(CLK_GPU_COREGROUP, "clk_gpu_coregroup", "clk_gpu_src", 0,
+ RK3572_CLKSEL_CON(202), 9, 5, DFLAGS,
+ RK3572_CLKGATE_CON(84), 5, GFLAGS),
+ COMPOSITE_NOMUX(CLK_GPU_STACKS, "clk_gpu_stacks", "clk_gpu_src", 0,
+ RK3572_CLKSEL_CON(203), 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(84), 6, GFLAGS),
+ COMPOSITE_NODIV(PCLK_GPU_ROOT, "pclk_gpu_root", mux_100m_50m_24m_p, 0,
+ RK3572_CLKSEL_CON(203), 5, 2, MFLAGS,
+ RK3572_CLKGATE_CON(84), 7, GFLAGS),
+
+ /* pd_center */
+ COMPOSITE(ACLK_CENTER_ROOT, "aclk_center_root", gpll_cpll_spll_aupll_bpll_p,
+ CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(206), 5, 3, MFLAGS, 0, 5, DFLAGS,
+ RK3572_CLKGATE_CON(86), 0, GFLAGS),
+ COMPOSITE_NODIV(ACLK_CENTER_LOW_ROOT, "aclk_center_low_root", mux_500m_250m_100m_24m_p,
+ CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(206), 8, 2, MFLAGS,
+ RK3572_CLKGATE_CON(86), 1, GFLAGS),
+ COMPOSITE_NODIV(HCLK_CENTER_ROOT, "hclk_center_root", mux_200m_100m_50m_24m_p,
+ CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(206), 10, 2, MFLAGS,
+ RK3572_CLKGATE_CON(86), 2, GFLAGS),
+ COMPOSITE_NODIV(PCLK_CENTER_ROOT, "pclk_center_root", mux_200m_100m_50m_24m_p,
+ CLK_IS_CRITICAL,
+ RK3572_CLKSEL_CON(206), 12, 2, MFLAGS,
+ RK3572_CLKGATE_CON(86), 3, GFLAGS),
+ GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", 0,
+ RK3572_CLKGATE_CON(86), 8, GFLAGS),
+ GATE(ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", "aclk_center_low_root", CLK_IS_CRITICAL,
+ RK3572_CLKGATE_CON(86), 9, GFLAGS),
+ GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", 0,
+ RK3572_CLKGATE_CON(86), 15, GFLAGS),
+
+ /* pd_secure */
+ COMPOSITE_NODIV(HCLK_SECURE_NS_ROOT, "hclk_secure_ns_root", mux_175m_116m_58m_24m_p,
+ CLK_IS_CRITICAL,
+ RK3572_SECURE_NS_CLKSEL_CON(0), 2, 2, MFLAGS,
+ RK3572_SECURE_NS_CLKGATE_CON(0), 1, GFLAGS),
+ COMPOSITE_NODIV(PCLK_SECURE_NS_ROOT, "pclk_secure_ns_root", mux_116m_58m_24m_p, 0,
+ RK3572_SECURE_NS_CLKSEL_CON(0), 4, 2, MFLAGS,
+ RK3572_SECURE_NS_CLKGATE_CON(0), 2, GFLAGS),
+ GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_ns_root", 0,
+ RK3572_SECURE_NS_CLKGATE_CON(0), 3, GFLAGS),
+ GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_ns_root", 0,
+ RK3572_SECURE_NS_CLKGATE_CON(0), 4, GFLAGS),
+ GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_secure_ns_root", 0,
+ RK3572_SECURE_NS_CLKGATE_CON(0), 8, GFLAGS),
+ GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0,
+ RK3572_SECURE_NS_CLKGATE_CON(0), 9, GFLAGS),
+ GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "clk_spll_div2", 0,
+ RK3572_NON_SECURE_GATING_CON00, 2, GFLAGS),
+ GATE(CLK_PKA_CRYPTO_NS, "clk_pka_crypto_ns", "clk_spll_div2", 0,
+ RK3572_NON_SECURE_GATING_CON00, 1, GFLAGS),
+
+ /* pd_pmu */
+ MUX(CLK_REF_OSC_MPHY, "clk_ref_osc_mphy", clk_ref_osc_mphy_p, 0,
+ RK3572_PMU_CLKSEL_CON(3), 0, 1, MFLAGS),
+ GATE(CLK_REF_UFS_CLKOUT, "clk_ref_ufs_clkout", "clk_ref_osc_mphy", 0,
+ RK3572_PMU_CLKGATE_CON(2), 5, GFLAGS),
+ COMPOSITE_NODIV(HCLK_PMU1_ROOT, "hclk_pmu1_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3572_PMU_CLKSEL_CON(4), 0, 2, MFLAGS,
+ RK3572_PMU_CLKGATE_CON(3), 0, GFLAGS),
+ COMPOSITE_NODIV(HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", mux_200m_100m_50m_24m_p, 0,
+ RK3572_PMU_CLKSEL_CON(4), 2, 2, MFLAGS,
+ RK3572_PMU_CLKGATE_CON(3), 1, GFLAGS),
+ COMPOSITE_NODIV(PCLK_PMU0_ROOT, "pclk_pmu0_root", mux_100m_50m_24m_p, 0,
+ RK3572_PMU_CLKSEL_CON(20), 0, 2, MFLAGS,
+ RK3572_PMU_CLKGATE_CON(7), 0, GFLAGS),
+ GATE(PCLK_PMU1_ROOT, "pclk_pmu1_root", "pclk_pmu0_root", 0,
+ RK3572_PMU_CLKGATE_CON(7), 10, GFLAGS),
+ GATE(PCLK_APB2ASB_PMU1, "pclk_apb2asb_pmu1", "pclk_pmu1_root", CLK_IS_CRITICAL,
+ RK3572_PMU_CLKGATE_CON(3), 6, GFLAGS),
+ COMPOSITE_NODIV(SCLK_APB2ASB_PMU1, "sclk_apb2asb_pmu1", sclk_apb2asb_p, CLK_IS_CRITICAL,
+ RK3572_PMU_CLKSEL_CON(4), 4, 2, MFLAGS,
+ RK3572_PMU_CLKGATE_CON(3), 7, GFLAGS),
+ GATE(CLK_PMUMCU_CORE_AON, "clk_pmumcu_core_aon", "hclk_pmu_cm0_root", 0,
+ RK3572_PMU_CLKGATE_CON(3), 13, GFLAGS),
+ COMPOSITE(CLK_MTIME_TOGGLE_A_PMU, "clk_mtime_toggle_a_pmu", mux_24m_32k_p, 0,
+ RK3572_PMU_CLKSEL_CON(4), 12, 1, MFLAGS, 6, 6, DFLAGS,
+ RK3572_PMU_CLKGATE_CON(3), 15, GFLAGS),
+ GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu1_root", CLK_IS_CRITICAL,
+ RK3572_PMU_CLKGATE_CON(4), 0, GFLAGS),
+ GATE(CLK_PMU1, "clk_pmu1", "xin24m", CLK_IS_CRITICAL,
+ RK3572_PMU_CLKGATE_CON(4), 3, GFLAGS),
+ GATE(PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu1_root", 0,
+ RK3572_PMU_CLKGATE_CON(4), 6, GFLAGS),
+ COMPOSITE_NODIV(TCLK_PMU1WDT, "tclk_pmu1wdt", mux_24m_32k_p, 0,
+ RK3572_PMU_CLKSEL_CON(4), 13, 1, MFLAGS,
+ RK3572_PMU_CLKGATE_CON(4), 7, GFLAGS),
+ GATE(PCLK_PMUTIMER, "pclk_pmutimer", "pclk_pmu1_root", 0,
+ RK3572_PMU_CLKGATE_CON(4), 8, GFLAGS),
+ COMPOSITE_NODIV(CLK_PMUTIMER_ROOT, "clk_pmutimer_root", mux_100m_24m_32k_p, 0,
+ RK3572_PMU_CLKSEL_CON(4), 14, 2, MFLAGS,
+ RK3572_PMU_CLKGATE_CON(4), 9, GFLAGS),
+ GATE(CLK_PMUTIMER0, "clk_pmutimer0", "clk_pmutimer_root", 0,
+ RK3572_PMU_CLKGATE_CON(4), 10, GFLAGS),
+ GATE(CLK_PMUTIMER1, "clk_pmutimer1", "clk_pmutimer_root", 0,
+ RK3572_PMU_CLKGATE_CON(4), 11, GFLAGS),
+ GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pmu1_root", 0,
+ RK3572_PMU_CLKGATE_CON(4), 12, GFLAGS),
+ COMPOSITE_NODIV(CLK_PWM0, "clk_pwm0", mux_100m_50m_24m_rc_p, 0,
+ RK3572_PMU_CLKSEL_CON(5), 0, 2, MFLAGS,
+ RK3572_PMU_CLKGATE_CON(4), 13, GFLAGS),
+ COMPOSITE_NODIV(CLK_PWM0_OSC, "clk_pwm0_osc", clk_pwm0_osc_p, 0,
+ RK3572_PMU_CLKSEL_CON(5), 2, 1, MFLAGS,
+ RK3572_PMU_CLKGATE_CON(4), 14, GFLAGS),
+ GATE(PCLK_PMUPHY_ROOT, "pclk_pmuphy_root", "pclk_pmu1_root", CLK_IS_CRITICAL,
+ RK3572_PMU_CLKGATE_CON(5), 1, GFLAGS),
+ GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pmu1_root", 0,
+ RK3572_PMU_CLKGATE_CON(5), 2, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_200m_100m_50m_24m_p, 0,
+ RK3572_PMU_CLKSEL_CON(6), 7, 2, MFLAGS,
+ RK3572_PMU_CLKGATE_CON(5), 3, GFLAGS),
+ COMPOSITE_NODIV(SCLK_UART1, "sclk_uart1", sclk_uart1_p, 0,
+ RK3572_PMU_CLKSEL_CON(8), 0, 2, MFLAGS,
+ RK3572_PMU_CLKGATE_CON(5), 6, GFLAGS),
+ GATE(PCLK_UART1, "pclk_uart1", "pclk_pmu1_root", 0,
+ RK3572_PMU_CLKGATE_CON(5), 7, GFLAGS),
+ GATE(CLK_PWM0_RC, "clk_pwm0_rc", "clk_rcosc", 0,
+ RK3572_PMU_CLKGATE_CON(5), 8, GFLAGS),
+ COMPOSITE(CLK_PDM0, "clk_pdm0", clk_pdm0_p, CLK_SET_RATE_PARENT,
+ RK3572_PMU_CLKSEL_CON(8), 14, 2, MFLAGS, 8, 6, DFLAGS,
+ RK3572_PMU_CLKGATE_CON(5), 14, GFLAGS),
+ GATE(HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 0,
+ RK3572_PMU_CLKGATE_CON(6), 0, GFLAGS),
+ COMPOSITE_NODIV(MCLK_PDM0, "mclk_pdm0", mclk_pdm0_p, CLK_SET_RATE_PARENT,
+ RK3572_PMU_CLKSEL_CON(9), 0, 2, MFLAGS,
+ RK3572_PMU_CLKGATE_CON(6), 1, GFLAGS),
+ GATE(HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 0,
+ RK3572_PMU_CLKGATE_CON(6), 2, GFLAGS),
+ GATE(CLK_PDM0_OUT, "clk_pdm0_out", "clk_pdm0", 0,
+ RK3572_PMU_CLKGATE_CON(6), 9, GFLAGS),
+ GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL,
+ RK3572_PMU_CLKGATE_CON(7), 3, GFLAGS),
+ GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0,
+ RK3572_PMU_CLKGATE_CON(7), 6, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0,
+ RK3572_PMU_CLKSEL_CON(20), 2, 1, MFLAGS,
+ RK3572_PMU_CLKGATE_CON(7), 7, GFLAGS),
+
+ COMPOSITE_NODIV(SAI_SCLKIN_FREQ, "sai_sclkin_freq", sai_sclkin_freq_p, 0,
+ RK3572_CLKSEL_CON(83), 4, 3, MFLAGS,
+ RK3572_CLKGATE_CON(18), 2, GFLAGS),
+ COMPOSITE_NODIV(SAI_SCLKIN_COUNTER, "sai_sclkin_counter", sai_sclkin_freq_p, 0,
+ RK3572_CLKSEL_CON(83), 7, 3, MFLAGS,
+ RK3572_CLKGATE_CON(18), 3, GFLAGS),
+ COMPOSITE_NODIV(CLK_FREQ_PWM1, "clk_freq_pwm1", clk_freq_pwm1_p, 0,
+ RK3572_CLKSEL_CON(82), 10, 3, MFLAGS,
+ RK3572_CLKGATE_CON(17), 8, GFLAGS),
+ COMPOSITE_NODIV(CLK_COUNTER_PWM1, "clk_counter_pwm1", clk_counter_pwm1_p, 0,
+ RK3572_CLKSEL_CON(82), 13, 3, MFLAGS,
+ RK3572_CLKGATE_CON(17), 9, GFLAGS),
+ MUX(ASRC_REF_PULSE, "asrc_ref_pulse", asrc_ref_pulse_p, 0,
+ RK3572_CLKSEL_CON(62), 12, 3, MFLAGS),
+ MUX(LRCK_ASRC_2CH0_SRC, "lrck_asrc_2ch0_src", lrck_asrc_src_p, 0,
+ RK3572_CLKSEL_CON(59), 0, 4, MFLAGS),
+ MUX(LRCK_ASRC_2CH0_DST, "lrck_asrc_2ch0_dst", lrck_asrc_dst_p, 0,
+ RK3572_CLKSEL_CON(59), 4, 4, MFLAGS),
+ MUX(LRCK_ASRC_2CH1_SRC, "lrck_asrc_2ch1_src", lrck_asrc_src_p, 0,
+ RK3572_CLKSEL_CON(59), 8, 4, MFLAGS),
+ MUX(LRCK_ASRC_2CH1_DST, "lrck_asrc_2ch1_dst", lrck_asrc_dst_p, 0,
+ RK3572_CLKSEL_CON(59), 12, 4, MFLAGS),
+ MUX(REF_PULSE_CLK_AUDIO_FRAC_0, "ref_pulse_clk_audio_frac_0", ref_pulse_p, 0,
+ RK3572_CLKSEL_CON(40), 13, 3, MFLAGS),
+ MUX(REF_PULSE_CLK_AUDIO_FRAC_1, "ref_pulse_clk_audio_frac_1", ref_pulse_p, 0,
+ RK3572_CLKSEL_CON(41), 0, 3, MFLAGS),
+ MUX(REF_PULSE_CLK_AUDIO_FRAC_2, "ref_pulse_clk_audio_frac_2", ref_pulse_p, 0,
+ RK3572_CLKSEL_CON(41), 3, 3, MFLAGS),
+ MUX(REF_PULSE_FRACDIV_3, "ref_pulse_fracdiv_3", ref_pulse_p, 0,
+ RK3572_CLKSEL_CON(41), 6, 3, MFLAGS),
+ MUX(REF_PULSE_AUPLL, "ref_pulse_aupll", ref_pulse_p, 0,
+ RK3572_CLKSEL_CON(41), 9, 3, MFLAGS),
+};
+
+static struct rockchip_clk_branch rk3572_armclkl1 __initdata =
+ COMPOSITE_NOGATE(ARMCLK_L1, "armclk_l1", mux_armclkl1_p, CLK_IS_CRITICAL,
+ RK3572_LITCORE1_CLKSEL_CON(0), 8, 2, MFLAGS, 3, 5, DFLAGS);
+
+static struct rockchip_clk_branch rk3572_aupll_ref_branches[] __initdata = {
+ MUXGRF(AUPLL_REF, "aupll_ref", mux_aupll_ref_p, CLK_IS_CRITICAL,
+ RK3572_PMU0_GRF_OSC_CON6, 0, 1, MFLAGS, grf_type_pmu0),
+};
+
+static void __init rk3572_clk_init(struct device_node *np)
+{
+ struct rockchip_clk_provider *ctx;
+ void __iomem *reg_base;
+ struct regmap *pmu0_grf;
+ int ret;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("%s: could not map cru region\n", __func__);
+ return;
+ }
+
+ ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
+ if (IS_ERR(ctx)) {
+ pr_err("%s: rockchip clk init failed\n", __func__);
+ iounmap(reg_base);
+ return;
+ }
+ pmu0_grf = ctx->grf;
+ if (IS_ERR(pmu0_grf)) {
+ pr_err("%s: could not get PMU0 GRF\n", __func__);
+ goto err_free;
+ }
+
+ ret = rockchip_clk_add_grf(ctx, pmu0_grf, grf_type_pmu0);
+ if (ret)
+ goto err_free;
+
+ rockchip_clk_register_branches(ctx, rk3572_aupll_ref_branches,
+ ARRAY_SIZE(rk3572_aupll_ref_branches));
+
+ rockchip_clk_register_plls(ctx, rk3572_pll_clks,
+ ARRAY_SIZE(rk3572_pll_clks),
+ RK3572_GRF_SOC_STATUS0);
+
+ rockchip_clk_register_armclk(ctx, ARMCLK_L0, "armclk_l0",
+ mux_armclkl0_p, ARRAY_SIZE(mux_armclkl0_p),
+ &rk3572_cpul0clk_data, rk3572_cpul0clk_rates,
+ ARRAY_SIZE(rk3572_cpul0clk_rates));
+
+ rockchip_clk_register_armclk(ctx, ARMCLK_B, "armclk_b",
+ mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
+ &rk3572_cpubclk_data, rk3572_cpubclk_rates,
+ ARRAY_SIZE(rk3572_cpubclk_rates));
+
+ rockchip_clk_register_branches(ctx, rk3572_clk_branches,
+ ARRAY_SIZE(rk3572_clk_branches));
+
+ rockchip_clk_register_armclk_multi_pll(ctx, &rk3572_armclkl1,
+ rk3572_cpul1clk_rates,
+ ARRAY_SIZE(rk3572_cpul1clk_rates));
+
+ rk3572_rst_init(np, reg_base);
+
+ rockchip_register_restart_notifier(ctx, RK3572_GLB_SRST_FST, NULL);
+
+ rockchip_clk_of_add_provider(np, ctx);
+ return;
+
+err_free:
+ kfree(ctx->clk_data.clks);
+ kfree(ctx);
+ iounmap(reg_base);
+}
+
+CLK_OF_DECLARE(rk3572_cru, "rockchip,rk3572-cru", rk3572_clk_init);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 72b36bba3152..b77f440e9104 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -426,6 +426,41 @@ struct clk;
#define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
#define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
+#define RK3572_PHP_CRU_BASE 0x8000
+#define RK3572_SECURE_NS_CRU_BASE 0x10000
+#define RK3572_PMU_CRU_BASE 0x20000
+#define RK3572_BIGCORE_CRU_BASE 0x40000
+#define RK3572_LITCORE0_CRU_BASE 0x48000
+#define RK3572_LITCORE1_CRU_BASE 0x50000
+#define RK3572_CCI_CRU_BASE 0x58000
+
+#define RK3572_PLL_CON(x) (RK2928_PLL_CON(x) + 0x4000)
+#define RK3572_MODE_CON0 0x4280
+#define RK3572_MODE_CON1 0x4284
+#define RK3572_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
+#define RK3572_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
+#define RK3572_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
+#define RK3572_GLB_SRST_FST 0xc08
+#define RK3572_NON_SECURE_GATING_CON00 0xc48
+
+#define RK3572_PPLL_CON(x) ((x) * 0x4 + RK3572_PHP_CRU_BASE)
+#define RK3572_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3572_PHP_CRU_BASE + 0x300)
+#define RK3572_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3572_PHP_CRU_BASE + 0x800)
+
+#define RK3572_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3572_PMU_CRU_BASE + 0x300)
+#define RK3572_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3572_PMU_CRU_BASE + 0x800)
+
+#define RK3572_SECURE_NS_CLKSEL_CON(x) ((x) * 0x4 + RK3572_SECURE_NS_CRU_BASE + 0x300)
+#define RK3572_SECURE_NS_CLKGATE_CON(x) ((x) * 0x4 + RK3572_SECURE_NS_CRU_BASE + 0x800)
+
+#define RK3572_LPLL_CON(x) ((x) * 0x4 + RK3572_CCI_CRU_BASE)
+#define RK3572_LPLL_MODE_CON0 (0x280 + RK3572_CCI_CRU_BASE)
+#define RK3572_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3572_CCI_CRU_BASE + 0x300)
+
+#define RK3572_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3572_BIGCORE_CRU_BASE + 0x300)
+#define RK3572_LITCORE0_CLKSEL_CON(x) ((x) * 0x4 + RK3572_LITCORE0_CRU_BASE + 0x300)
+#define RK3572_LITCORE1_CLKSEL_CON(x) ((x) * 0x4 + RK3572_LITCORE1_CRU_BASE + 0x300)
+
#define RK3576_PHP_CRU_BASE 0x8000
#define RK3576_SECURE_NS_CRU_BASE 0x10000
#define RK3576_PMU_CRU_BASE 0x20000
@@ -1396,6 +1431,7 @@ void rv1126b_rst_init(struct device_node *np, void __iomem *reg_base);
void rk3506_rst_init(struct device_node *np, void __iomem *reg_base);
void rk3528_rst_init(struct device_node *np, void __iomem *reg_base);
void rk3562_rst_init(struct device_node *np, void __iomem *reg_base);
+void rk3572_rst_init(struct device_node *np, void __iomem *reg_base);
void rk3576_rst_init(struct device_node *np, void __iomem *reg_base);
void rk3588_rst_init(struct device_node *np, void __iomem *reg_base);
diff --git a/drivers/clk/rockchip/rst-rk3572.c b/drivers/clk/rockchip/rst-rk3572.c
new file mode 100644
index 000000000000..a07f88dadc00
--- /dev/null
+++ b/drivers/clk/rockchip/rst-rk3572.c
@@ -0,0 +1,739 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <dt-bindings/reset/rockchip,rk3572-cru.h>
+#include "clk.h"
+
+#define CRU_RESET_OFFSET(id, reg, bit)[id] = (0x00000 * 4 + (reg) * 16 + (bit))
+#define PHPPHY_CRU_RESET_OFFSET(id, reg, bit)[id] = (0x08000 * 4 + (reg) * 16 + (bit))
+#define SECURE_CRU_RESET_OFFSET(id, reg, bit)[id] = (0x10000 * 4 + (reg) * 16 + (bit))
+#define PMU1_CRU_RESET_OFFSET(id, reg, bit)[id] = (0x20000 * 4 + (reg) * 16 + (bit))
+#define DDR0_CRU_RESET_OFFSET(id, reg, bit)[id] = (0x30000 * 4 + (reg) * 16 + (bit))
+#define BIGCORE_CRU_RESET_OFFSET(id, reg, bit)[id] = (0x40000 * 4 + (reg) * 16 + (bit))
+#define LITCORE0_CRU_RESET_OFFSET(id, reg, bit)[id] = (0x48000 * 4 + (reg) * 16 + (bit))
+#define LITCORE1_CRU_RESET_OFFSET(id, reg, bit)[id] = (0x50000 * 4 + (reg) * 16 + (bit))
+#define CCI_CRU_RESET_OFFSET(id, reg, bit)[id] = (0x58000 * 4 + (reg) * 16 + (bit))
+
+static const int rk3572_register_offset[] = {
+ /* CRU-->SOFTRST_CON01 */
+ CRU_RESET_OFFSET(SRST_ARESETN_TOP_BIU, 1, 4),
+ CRU_RESET_OFFSET(SRST_PRESETN_TOP_BIU, 1, 6),
+ CRU_RESET_OFFSET(SRST_ARESETN_TOP_MID_BIU, 1, 7),
+ CRU_RESET_OFFSET(SRST_HRESETN_TOP_BIU, 1, 15),
+
+ /* CRU-->SOFTRST_CON02 */
+ CRU_RESET_OFFSET(SRST_HRESETN_TOP_FW, 2, 0),
+
+ /* CRU-->SOFTRST_CON06 */
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_TOP, 6, 2),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_TOP, 6, 3),
+
+ /* CRU-->SOFTRST_CON07 */
+ CRU_RESET_OFFSET(SRST_HRESETN_AUDIO_BIU, 7, 2),
+ CRU_RESET_OFFSET(SRST_HRESETN_ASRC_2CH_0, 7, 3),
+ CRU_RESET_OFFSET(SRST_HRESETN_ASRC_2CH_1, 7, 4),
+ CRU_RESET_OFFSET(SRST_RESETN_ASRC_2CH_0, 7, 7),
+ CRU_RESET_OFFSET(SRST_RESETN_ASRC_2CH_1, 7, 8),
+ CRU_RESET_OFFSET(SRST_MRESETN_SAI0, 7, 12),
+ CRU_RESET_OFFSET(SRST_HRESETN_SAI0, 7, 13),
+ CRU_RESET_OFFSET(SRST_HRESETN_SPDIF_RX0, 7, 14),
+ CRU_RESET_OFFSET(SRST_MRESETN_SPDIF_RX0, 7, 15),
+
+ /* CRU-->SOFTRST_CON08 */
+ CRU_RESET_OFFSET(SRST_MRESETN_SAI1, 8, 5),
+ CRU_RESET_OFFSET(SRST_HRESETN_SAI1, 8, 6),
+ CRU_RESET_OFFSET(SRST_MRESETN_SAI2, 8, 8),
+ CRU_RESET_OFFSET(SRST_HRESETN_SAI2, 8, 10),
+ CRU_RESET_OFFSET(SRST_MRESETN_SAI3, 8, 12),
+ CRU_RESET_OFFSET(SRST_HRESETN_SAI3, 8, 14),
+ CRU_RESET_OFFSET(SRST_HRESETN_ACDCDIG_DSM, 8, 15),
+
+ /* CRU-->SOFTRST_CON09 */
+ CRU_RESET_OFFSET(SRST_MRESETN_ACDCDIG_DSM, 9, 0),
+ CRU_RESET_OFFSET(SRST_PRESETN_AUDIO_BIU, 9, 4),
+ CRU_RESET_OFFSET(SRST_PRESETN_AUDIO_GRF, 9, 5),
+ CRU_RESET_OFFSET(SRST_HRESETN_SPDIF_TX0, 9, 6),
+ CRU_RESET_OFFSET(SRST_MRESETN_SPDIF_TX0, 9, 7),
+ CRU_RESET_OFFSET(SRST_HRESETN_SPDIF_TX1, 9, 8),
+ CRU_RESET_OFFSET(SRST_MRESETN_SPDIF_TX1, 9, 9),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_AUDIO, 9, 10),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_AUDIO, 9, 11),
+
+ /* CRU-->SOFTRST_CON11 */
+ CRU_RESET_OFFSET(SRST_ARESETN_BUS_BIU, 11, 3),
+ CRU_RESET_OFFSET(SRST_ARESETN_BUS_FW, 11, 4),
+ CRU_RESET_OFFSET(SRST_PRESETN_BUS_BIU, 11, 5),
+ CRU_RESET_OFFSET(SRST_PRESETN_CRU, 11, 6),
+ CRU_RESET_OFFSET(SRST_HRESETN_CAN0, 11, 7),
+ CRU_RESET_OFFSET(SRST_RESETN_CAN0, 11, 8),
+ CRU_RESET_OFFSET(SRST_HRESETN_CAN1, 11, 9),
+ CRU_RESET_OFFSET(SRST_RESETN_CAN1, 11, 10),
+ CRU_RESET_OFFSET(SRST_HRESETN_CAN2, 11, 11),
+ CRU_RESET_OFFSET(SRST_RESETN_CAN2, 11, 12),
+ CRU_RESET_OFFSET(SRST_HRESETN_CAN3, 11, 13),
+ CRU_RESET_OFFSET(SRST_RESETN_CAN3, 11, 14),
+
+ /* CRU-->SOFTRST_CON12 */
+ CRU_RESET_OFFSET(SRST_ARESETN_DECOM_BIU, 12, 0),
+ CRU_RESET_OFFSET(SRST_HRESETN_BUS_BIU, 12, 3),
+ CRU_RESET_OFFSET(SRST_RESETN_KEY_SHIFT, 12, 4),
+ CRU_RESET_OFFSET(SRST_PRESETN_I2C1, 12, 5),
+ CRU_RESET_OFFSET(SRST_PRESETN_I2C2, 12, 6),
+ CRU_RESET_OFFSET(SRST_PRESETN_I2C3, 12, 7),
+ CRU_RESET_OFFSET(SRST_PRESETN_I2C4, 12, 8),
+ CRU_RESET_OFFSET(SRST_PRESETN_I2C5, 12, 9),
+ CRU_RESET_OFFSET(SRST_PRESETN_I2C6, 12, 10),
+ CRU_RESET_OFFSET(SRST_PRESETN_I2C7, 12, 11),
+ CRU_RESET_OFFSET(SRST_PRESETN_I2C8, 12, 12),
+ CRU_RESET_OFFSET(SRST_PRESETN_I2C9, 12, 13),
+ CRU_RESET_OFFSET(SRST_PRESETN_WDT_BUSMCU, 12, 14),
+ CRU_RESET_OFFSET(SRST_TRESETN_WDT_BUSMCU, 12, 15),
+
+ /* CRU-->SOFTRST_CON13 */
+ CRU_RESET_OFFSET(SRST_ARESETN_GIC, 13, 0),
+ CRU_RESET_OFFSET(SRST_RESETN_I2C1, 13, 5),
+ CRU_RESET_OFFSET(SRST_RESETN_I2C2, 13, 6),
+ CRU_RESET_OFFSET(SRST_RESETN_I2C3, 13, 7),
+ CRU_RESET_OFFSET(SRST_RESETN_I2C4, 13, 8),
+ CRU_RESET_OFFSET(SRST_RESETN_I2C5, 13, 9),
+ CRU_RESET_OFFSET(SRST_RESETN_I2C6, 13, 10),
+ CRU_RESET_OFFSET(SRST_RESETN_I2C7, 13, 11),
+ CRU_RESET_OFFSET(SRST_RESETN_I2C8, 13, 12),
+ CRU_RESET_OFFSET(SRST_RESETN_I2C9, 13, 13),
+ CRU_RESET_OFFSET(SRST_PRESETN_SARADC, 13, 15),
+
+ /* CRU-->SOFTRST_CON14 */
+ CRU_RESET_OFFSET(SRST_RESETN_SARADC, 14, 0),
+ CRU_RESET_OFFSET(SRST_RESETN_SARADC_32K, 14, 1),
+ CRU_RESET_OFFSET(SRST_PRESETN_TSADC, 14, 2),
+ CRU_RESET_OFFSET(SRST_RESETN_TSADC, 14, 3),
+ CRU_RESET_OFFSET(SRST_PRESETN_UART0, 14, 4),
+ CRU_RESET_OFFSET(SRST_PRESETN_UART2, 14, 5),
+ CRU_RESET_OFFSET(SRST_PRESETN_UART3, 14, 6),
+ CRU_RESET_OFFSET(SRST_PRESETN_UART4, 14, 7),
+ CRU_RESET_OFFSET(SRST_PRESETN_UART5, 14, 8),
+ CRU_RESET_OFFSET(SRST_PRESETN_UART6, 14, 9),
+ CRU_RESET_OFFSET(SRST_PRESETN_UART7, 14, 10),
+ CRU_RESET_OFFSET(SRST_PRESETN_UART8, 14, 11),
+ CRU_RESET_OFFSET(SRST_PRESETN_UART9, 14, 12),
+ CRU_RESET_OFFSET(SRST_PRESETN_UART10, 14, 13),
+ CRU_RESET_OFFSET(SRST_PRESETN_UART11, 14, 14),
+ CRU_RESET_OFFSET(SRST_SRESETN_UART0, 14, 15),
+
+ /* CRU-->SOFTRST_CON15 */
+ CRU_RESET_OFFSET(SRST_SRESETN_UART2, 15, 0),
+ CRU_RESET_OFFSET(SRST_SRESETN_UART3, 15, 3),
+ CRU_RESET_OFFSET(SRST_SRESETN_UART4, 15, 6),
+ CRU_RESET_OFFSET(SRST_SRESETN_UART5, 15, 9),
+ CRU_RESET_OFFSET(SRST_SRESETN_UART6, 15, 12),
+ CRU_RESET_OFFSET(SRST_SRESETN_UART7, 15, 15),
+
+ /* CRU-->SOFTRST_CON16 */
+ CRU_RESET_OFFSET(SRST_SRESETN_UART8, 16, 2),
+ CRU_RESET_OFFSET(SRST_SRESETN_UART9, 16, 3),
+ CRU_RESET_OFFSET(SRST_SRESETN_UART10, 16, 4),
+ CRU_RESET_OFFSET(SRST_SRESETN_UART11, 16, 5),
+ CRU_RESET_OFFSET(SRST_PRESETN_SPI0, 16, 7),
+ CRU_RESET_OFFSET(SRST_PRESETN_SPI1, 16, 8),
+ CRU_RESET_OFFSET(SRST_PRESETN_SPI2, 16, 9),
+ CRU_RESET_OFFSET(SRST_PRESETN_SPI3, 16, 10),
+ CRU_RESET_OFFSET(SRST_PRESETN_SPI4, 16, 11),
+ CRU_RESET_OFFSET(SRST_RESETN_SPI0, 16, 12),
+ CRU_RESET_OFFSET(SRST_RESETN_SPI1, 16, 13),
+ CRU_RESET_OFFSET(SRST_RESETN_SPI2, 16, 14),
+ CRU_RESET_OFFSET(SRST_RESETN_SPI3, 16, 15),
+
+ /* CRU-->SOFTRST_CON17 */
+ CRU_RESET_OFFSET(SRST_RESETN_SPI4, 17, 0),
+ CRU_RESET_OFFSET(SRST_PRESETN_WDT0, 17, 1),
+ CRU_RESET_OFFSET(SRST_TRESETN_WDT0, 17, 2),
+ CRU_RESET_OFFSET(SRST_PRESETN_SYS_GRF, 17, 3),
+ CRU_RESET_OFFSET(SRST_PRESETN_PWM1, 17, 4),
+ CRU_RESET_OFFSET(SRST_RESETN_PWM1, 17, 5),
+ CRU_RESET_OFFSET(SRST_PRESETN_PWM2, 17, 10),
+ CRU_RESET_OFFSET(SRST_RESETN_PWM2, 17, 11),
+
+ /* CRU-->SOFTRST_CON18 */
+ CRU_RESET_OFFSET(SRST_PRESETN_BUSTIMER0, 18, 4),
+ CRU_RESET_OFFSET(SRST_PRESETN_BUSTIMER1, 18, 5),
+ CRU_RESET_OFFSET(SRST_RESETN_TIMER0, 18, 7),
+ CRU_RESET_OFFSET(SRST_RESETN_TIMER1, 18, 8),
+ CRU_RESET_OFFSET(SRST_RESETN_TIMER2, 18, 9),
+ CRU_RESET_OFFSET(SRST_RESETN_TIMER3, 18, 10),
+ CRU_RESET_OFFSET(SRST_RESETN_TIMER4, 18, 11),
+ CRU_RESET_OFFSET(SRST_RESETN_TIMER5, 18, 12),
+ CRU_RESET_OFFSET(SRST_PRESETN_MAILBOX0, 18, 14),
+
+ /* CRU-->SOFTRST_CON19 */
+ CRU_RESET_OFFSET(SRST_PRESETN_GPIO1, 19, 0),
+ CRU_RESET_OFFSET(SRST_DBRESETN_GPIO1, 19, 1),
+ CRU_RESET_OFFSET(SRST_PRESETN_GPIO2, 19, 2),
+ CRU_RESET_OFFSET(SRST_DBRESETN_GPIO2, 19, 3),
+ CRU_RESET_OFFSET(SRST_PRESETN_GPIO3, 19, 4),
+ CRU_RESET_OFFSET(SRST_DBRESETN_GPIO3, 19, 5),
+ CRU_RESET_OFFSET(SRST_PRESETN_GPIO4, 19, 6),
+ CRU_RESET_OFFSET(SRST_DBRESETN_GPIO4, 19, 7),
+ CRU_RESET_OFFSET(SRST_ARESETN_DECOM, 19, 8),
+ CRU_RESET_OFFSET(SRST_PRESETN_DECOM, 19, 9),
+ CRU_RESET_OFFSET(SRST_DRESETN_DECOM, 19, 10),
+ CRU_RESET_OFFSET(SRST_RESETN_TIMER6, 19, 12),
+ CRU_RESET_OFFSET(SRST_RESETN_TIMER7, 19, 13),
+ CRU_RESET_OFFSET(SRST_RESETN_TIMER8, 19, 14),
+ CRU_RESET_OFFSET(SRST_RESETN_TIMER9, 19, 15),
+
+ /* CRU-->SOFTRST_CON20 */
+ CRU_RESET_OFFSET(SRST_RESETN_TIMER10, 20, 0),
+ CRU_RESET_OFFSET(SRST_RESETN_TIMER11, 20, 1),
+ CRU_RESET_OFFSET(SRST_ARESETN_RKDMA0, 20, 2),
+ CRU_RESET_OFFSET(SRST_PRESETN_RKDMA0, 20, 3),
+ CRU_RESET_OFFSET(SRST_ARESETN_RKDMA1, 20, 4),
+ CRU_RESET_OFFSET(SRST_PRESETN_RKDMA1, 20, 5),
+ CRU_RESET_OFFSET(SRST_ARESETN_RKDMA2, 20, 6),
+ CRU_RESET_OFFSET(SRST_PRESETN_RKDMA2, 20, 7),
+ CRU_RESET_OFFSET(SRST_ARESETN_RKDMA3, 20, 8),
+ CRU_RESET_OFFSET(SRST_PRESETN_RKDMA3, 20, 9),
+ CRU_RESET_OFFSET(SRST_PRESETN_SPINLOCK, 20, 10),
+ CRU_RESET_OFFSET(SRST_RESETN_REF_PVTPLL_BUS, 20, 11),
+ CRU_RESET_OFFSET(SRST_RESETN_I3C, 20, 12),
+ CRU_RESET_OFFSET(SRST_HRESETN_I3C, 20, 13),
+
+ /* CRU-->SOFTRST_CON21 */
+ CRU_RESET_OFFSET(SRST_RESETN_BUSMCU_BIU, 21, 1),
+ CRU_RESET_OFFSET(SRST_CORERESETN_N320, 21, 2),
+ CRU_RESET_OFFSET(SRST_PORESETN_N320, 21, 3),
+ CRU_RESET_OFFSET(SRST_RESETN_MCU_AXI_INTEGRITY, 21, 6),
+ CRU_RESET_OFFSET(SRST_PRESETN_INTMUX2PMU, 21, 8),
+ CRU_RESET_OFFSET(SRST_PRESETN_INTMUX2DDR, 21, 9),
+ CRU_RESET_OFFSET(SRST_PRESETN_PVTPLL_BUS, 21, 11),
+ CRU_RESET_OFFSET(SRST_RESETN_HDMITXHPD, 21, 14),
+
+ /* CRU-->SOFTRST_CON22 */
+ CRU_RESET_OFFSET(SRST_PRESETN_APB2ASB_HDMITX, 22, 2),
+ CRU_RESET_OFFSET(SRST_SRESETN_APB2ASB_HDMITX, 22, 3),
+ CRU_RESET_OFFSET(SRST_PRESETN_APB2ASB_MIPICSI, 22, 6),
+ CRU_RESET_OFFSET(SRST_SRESETN_APB2ASB_MIPICSI, 22, 7),
+ CRU_RESET_OFFSET(SRST_PRESETN_APB2ASB_VCCIO0_3, 22, 8),
+ CRU_RESET_OFFSET(SRST_SRESETN_APB2ASB_VCCIO0_3, 22, 9),
+ CRU_RESET_OFFSET(SRST_PRESETN_APB2ASB_VCCIO1_2_4, 22, 10),
+ CRU_RESET_OFFSET(SRST_SRESETN_APB2ASB_VCCIO1_2_4, 22, 11),
+ CRU_RESET_OFFSET(SRST_PRESETN_APB2ASB_VCCIO5_6, 22, 12),
+ CRU_RESET_OFFSET(SRST_SRESETN_APB2ASB_VCCIO5_6, 22, 13),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_BUS, 22, 14),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_BUS, 22, 15),
+
+ /* CRU-->SOFTRST_CON23 */
+ CRU_RESET_OFFSET(SRST_PRESETN_DDR_MON, 23, 1),
+ CRU_RESET_OFFSET(SRST_PRESETN_DDR_BIU, 23, 2),
+ CRU_RESET_OFFSET(SRST_PRESETN_DDR_UPCTL, 23, 3),
+ CRU_RESET_OFFSET(SRST_TMRESETN_DDR_MON, 23, 4),
+ CRU_RESET_OFFSET(SRST_ARESETN_DDR_BIU, 23, 5),
+ CRU_RESET_OFFSET(SRST_PRESETN_DDR_BIU_FW, 23, 6),
+ CRU_RESET_OFFSET(SRST_RESETN_DDR_MON, 23, 10),
+ CRU_RESET_OFFSET(SRST_PRESETN_DDR_HWLP, 23, 13),
+
+ /* CRU-->SOFTRST_CON24 */
+ CRU_RESET_OFFSET(SRST_ARESETN_DDR_MSCH_BIU, 24, 3),
+ CRU_RESET_OFFSET(SRST_ARESETN_DDR_MSCH_FW, 24, 4),
+ CRU_RESET_OFFSET(SRST_RESETN_DDR_SCRAMBLE, 24, 9),
+ CRU_RESET_OFFSET(SRST_LRESETN_DDRSCH_BIU, 24, 11),
+
+ /* CRU-->SOFTRST_CON25 */
+ CRU_RESET_OFFSET(SRST_RESETN_DDR_TIMER0, 25, 4),
+ CRU_RESET_OFFSET(SRST_RESETN_DDR_TIMER1, 25, 5),
+ CRU_RESET_OFFSET(SRST_TRESETN_DDR_WDT, 25, 6),
+ CRU_RESET_OFFSET(SRST_PRESETN_WDT, 25, 7),
+ CRU_RESET_OFFSET(SRST_PRESETN_TIMER, 25, 8),
+ CRU_RESET_OFFSET(SRST_PRESETN_DDR_GRF, 25, 11),
+
+ /* CRU-->SOFTRST_CON26 */
+ CRU_RESET_OFFSET(SRST_RESETN_DDR_UPCTL, 26, 1),
+ CRU_RESET_OFFSET(SRST_ARESETN_DDR_UPCTL_0, 26, 2),
+ CRU_RESET_OFFSET(SRST_ARESETN_DDR_UPCTL_1, 26, 3),
+ CRU_RESET_OFFSET(SRST_ARESETN_DDR_UPCTL_2, 26, 4),
+ CRU_RESET_OFFSET(SRST_ARESETN_DDR_UPCTL_3, 26, 5),
+ CRU_RESET_OFFSET(SRST_ARESETN_DDR_UPCTL_4, 26, 6),
+ CRU_RESET_OFFSET(SRST_ARESETN_DDR_UPCTL_5, 26, 7),
+
+ /* CRU-->SOFTRST_CON27 */
+ CRU_RESET_OFFSET(SRST_RESETN_DDRMCU_BIU, 27, 0),
+ CRU_RESET_OFFSET(SRST_CORERESETN_N320_DDR, 27, 1),
+ CRU_RESET_OFFSET(SRST_PORESETN_N320_DDR, 27, 2),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_DDR, 27, 6),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_DDR, 27, 7),
+
+ /* CRU-->SOFTRST_CON31 */
+ CRU_RESET_OFFSET(SRST_ARESETN_RKNN, 31, 2),
+ CRU_RESET_OFFSET(SRST_ARESETN_RKNN_RV, 31, 3),
+ CRU_RESET_OFFSET(SRST_ARESETN_RKNN_BIU, 31, 4),
+ CRU_RESET_OFFSET(SRST_ARESETN_RKNN_FW, 31, 5),
+ CRU_RESET_OFFSET(SRST_PRESETN_RKNN_BIU, 31, 7),
+ CRU_RESET_OFFSET(SRST_PRESETN_PVTPLL_NPU, 31, 8),
+ CRU_RESET_OFFSET(SRST_RESETN_NPU_PVTPLL, 31, 9),
+ CRU_RESET_OFFSET(SRST_RESETN_24M_RKNN, 31, 11),
+ CRU_RESET_OFFSET(SRST_RESETN_NPUTIMER0, 31, 13),
+ CRU_RESET_OFFSET(SRST_RESETN_NPUTIMER1, 31, 14),
+ CRU_RESET_OFFSET(SRST_PRESETN_NPU_TIMER, 31, 15),
+
+ /* CRU-->SOFTRST_CON32 */
+ CRU_RESET_OFFSET(SRST_PRESETN_NPU_WDT, 32, 0),
+ CRU_RESET_OFFSET(SRST_TRESETN_NPU_WDT, 32, 1),
+ CRU_RESET_OFFSET(SRST_PRESETN_RKNN_GRF, 32, 2),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_NPU, 32, 3),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_NPU, 32, 4),
+
+ /* CRU-->SOFTRST_CON33 */
+ CRU_RESET_OFFSET(SRST_PRESETN_PHP0_GRF, 33, 1),
+ CRU_RESET_OFFSET(SRST_PRESETN_PHP0_BIU, 33, 2),
+ CRU_RESET_OFFSET(SRST_ARESETN_PHP0_BIU, 33, 5),
+ CRU_RESET_OFFSET(SRST_ARESETN_PHP0_FW, 33, 6),
+ CRU_RESET_OFFSET(SRST_PRESETN_PCIE1, 33, 7),
+ CRU_RESET_OFFSET(SRST_RESETN_PCIE1_POWER_UP, 33, 9),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_PHP0, 33, 14),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_PHP0, 33, 15),
+
+ /* CRU-->SOFTRST_CON34 */
+ CRU_RESET_OFFSET(SRST_PRESETN_PCIE0, 34, 3),
+ CRU_RESET_OFFSET(SRST_RESETN_PCIE0_POWER_UP, 34, 5),
+ CRU_RESET_OFFSET(SRST_ARESETN_USB3OTG1, 34, 9),
+ CRU_RESET_OFFSET(SRST_ARESETN_GMAC0, 34, 12),
+ CRU_RESET_OFFSET(SRST_ARESETN_USB3OTG0, 34, 15),
+
+ /* CRU-->SOFTRST_CON35 */
+ CRU_RESET_OFFSET(SRST_ARESETN_UFS_BIU, 35, 2),
+ CRU_RESET_OFFSET(SRST_ARESETN_UFS_SYS, 35, 3),
+ CRU_RESET_OFFSET(SRST_ARESETN_UFS, 35, 4),
+ CRU_RESET_OFFSET(SRST_PRESETN_UFS_GRF, 35, 6),
+
+ /* CRU-->SOFTRST_CON37 */
+ CRU_RESET_OFFSET(SRST_RESETN_RXOOB0, 37, 0),
+ CRU_RESET_OFFSET(SRST_RESETN_PMALIVE0, 37, 1),
+ CRU_RESET_OFFSET(SRST_ARESETN_SATA0, 37, 2),
+ CRU_RESET_OFFSET(SRST_RESETN_RXOOB1, 37, 3),
+ CRU_RESET_OFFSET(SRST_RESETN_PMALIVE1, 37, 4),
+ CRU_RESET_OFFSET(SRST_ARESETN_SATA1, 37, 5),
+ CRU_RESET_OFFSET(SRST_RESETN_XPCS_PWR_ON, 37, 6),
+ CRU_RESET_OFFSET(SRST_RESETN_ASIC0, 37, 8),
+ CRU_RESET_OFFSET(SRST_RESETN_ASIC1, 37, 9),
+
+ /* CRU-->SOFTRST_CON42 */
+ CRU_RESET_OFFSET(SRST_PRESETN_NVM0_GRF, 42, 3),
+ CRU_RESET_OFFSET(SRST_PRESETN_NVM0_BIU, 42, 4),
+ CRU_RESET_OFFSET(SRST_ARESETN_NVM0_BIU, 42, 5),
+ CRU_RESET_OFFSET(SRST_HRESETN_NVM0_BIU, 42, 6),
+ CRU_RESET_OFFSET(SRST_CRESETN_EMMC, 42, 7),
+ CRU_RESET_OFFSET(SRST_HRESETN_EMMC, 42, 8),
+ CRU_RESET_OFFSET(SRST_ARESETN_EMMC, 42, 9),
+ CRU_RESET_OFFSET(SRST_BRESETN_EMMC, 42, 10),
+ CRU_RESET_OFFSET(SRST_TRESETN_EMMC, 42, 11),
+ CRU_RESET_OFFSET(SRST_ARESETN_GMAC1, 42, 14),
+
+ /* CRU-->SOFTRST_CON43 */
+ CRU_RESET_OFFSET(SRST_SRESETN_FSPI0, 43, 0),
+ CRU_RESET_OFFSET(SRST_HRESETN_FSPI0, 43, 1),
+ CRU_RESET_OFFSET(SRST_HRESETN_SDMMC1, 43, 3),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_NVM0, 43, 5),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_NVM0, 43, 6),
+
+ /* CRU-->SOFTRST_CON44 */
+ CRU_RESET_OFFSET(SRST_ARESETN_DSMC_BIU, 44, 1),
+ CRU_RESET_OFFSET(SRST_ARESETN_DSMC, 44, 2),
+ CRU_RESET_OFFSET(SRST_HRESETN_DSMC_BIU, 44, 4),
+ CRU_RESET_OFFSET(SRST_HRESETN_DSMC, 44, 5),
+ CRU_RESET_OFFSET(SRST_PRESETN_DSMC_BIU, 44, 7),
+ CRU_RESET_OFFSET(SRST_PRESETN_DSMC, 44, 8),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_DSMC, 44, 10),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_DSMC, 44, 11),
+ CRU_RESET_OFFSET(SRST_PRESETN_DSMC_GRF, 44, 13),
+
+ /* CRU-->SOFTRST_CON45 */
+ CRU_RESET_OFFSET(SRST_PRESETN_NVM1_GRF, 45, 3),
+ CRU_RESET_OFFSET(SRST_PRESETN_NVM1_BIU, 45, 4),
+ CRU_RESET_OFFSET(SRST_HRESETN_NVM1_BIU, 45, 6),
+ CRU_RESET_OFFSET(SRST_HRESETN_SDMMC0, 45, 8),
+ CRU_RESET_OFFSET(SRST_SRESETN_FSPI1, 45, 11),
+ CRU_RESET_OFFSET(SRST_HRESETN_FSPI1, 45, 12),
+
+ /* CRU-->SOFTRST_CON46 */
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_NVM1, 46, 4),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_NVM1, 46, 5),
+
+ /* CRU-->SOFTRST_CON50 */
+ CRU_RESET_OFFSET(SRST_HRESETN_RKVDEC, 50, 3),
+ CRU_RESET_OFFSET(SRST_HRESETN_RKVDEC_BIU, 50, 5),
+ CRU_RESET_OFFSET(SRST_ARESETN_RKVDEC_BIU, 50, 6),
+ CRU_RESET_OFFSET(SRST_RESETN_RKVDEC_HEVC_CA, 50, 8),
+ CRU_RESET_OFFSET(SRST_RESETN_RKVDEC_CORE, 50, 9),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_VDEC, 50, 10),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_VDEC, 50, 11),
+ CRU_RESET_OFFSET(SRST_PRESETN_VDEC_BIU, 50, 14),
+ CRU_RESET_OFFSET(SRST_PRESETN_VDEC_GRF, 50, 15),
+
+ /* CRU-->SOFTRST_CON52 */
+ CRU_RESET_OFFSET(SRST_PRESETN_APB2ASB_MIPI_HDMI_SUBVO, 52, 1),
+ CRU_RESET_OFFSET(SRST_SRESETN_APB2ASB_MIPI_HDMI_SUBVO, 52, 2),
+ CRU_RESET_OFFSET(SRST_PRESETN_APB2ASB_VCCIO0_3_SUBVO, 52, 7),
+ CRU_RESET_OFFSET(SRST_SRESETN_APB2ASB_VCCIO0_3_SUBVO, 52, 8),
+ CRU_RESET_OFFSET(SRST_PRESETN_HDPTXPHY, 52, 9),
+ CRU_RESET_OFFSET(SRST_PRESETN_HDPTXPHY_GRF, 52, 10),
+ CRU_RESET_OFFSET(SRST_PRESETN_MIPI_DPHY0, 52, 11),
+
+ /* CRU-->SOFTRST_CON53 */
+ CRU_RESET_OFFSET(SRST_RESETN_HDPTX_INIT, 53, 0),
+ CRU_RESET_OFFSET(SRST_RESETN_HDPTX_CMN, 53, 1),
+ CRU_RESET_OFFSET(SRST_RESETN_HDPTX_LANE, 53, 2),
+ CRU_RESET_OFFSET(SRST_PRESETN_IOC_SUBVO, 53, 3),
+ CRU_RESET_OFFSET(SRST_RESETN_GMAC1_SUBVO_ASYNC, 53, 4),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_SUBSYSVO, 53, 5),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_SUBSYSVO, 53, 6),
+
+ /* CRU-->SOFTRST_CON54 */
+ CRU_RESET_OFFSET(SRST_PRESETN_APB2ASB_VCCIO1_2_4_SUBVI, 54, 1),
+ CRU_RESET_OFFSET(SRST_SRESETN_APB2ASB_VCCIO1_2_4_SUBVI, 54, 2),
+ CRU_RESET_OFFSET(SRST_PRESETN_APB2ASB_CSIPHY_SUBVI, 54, 3),
+ CRU_RESET_OFFSET(SRST_SRESETN_APB2ASB_CSIPHY_SUBVI, 54, 4),
+ CRU_RESET_OFFSET(SRST_PRESETN_CSIPHY0, 54, 5),
+ CRU_RESET_OFFSET(SRST_PRESETN_CSIPHY0_GRF, 54, 6),
+ CRU_RESET_OFFSET(SRST_PRESETN_CSIPHY1, 54, 7),
+ CRU_RESET_OFFSET(SRST_PRESETN_CSIPHY1_GRF, 54, 8),
+ CRU_RESET_OFFSET(SRST_PRESETN_IOC_SUBVI, 54, 9),
+ CRU_RESET_OFFSET(SRST_RESETN_GMAC0_SUBVI_ASYNC, 54, 10),
+ CRU_RESET_OFFSET(SRST_SCAN_RESETN_CSIPHY0, 54, 11),
+ CRU_RESET_OFFSET(SRST_SCAN_RESETN_CSIPHY1, 54, 12),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_SUBSYSVI, 54, 14),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_SUBSYSVI, 54, 15),
+
+ /* CRU-->SOFTRST_CON56 */
+ CRU_RESET_OFFSET(SRST_PRESETN_APB2ASB_VCCIO5_6_SUBDSMC, 56, 3),
+ CRU_RESET_OFFSET(SRST_SRESETN_APB2ASB_VCCIO5_6_SUBDSMC, 56, 4),
+ CRU_RESET_OFFSET(SRST_PRESETN_VCCIO5_6, 56, 5),
+ CRU_RESET_OFFSET(SRST_RESETN_GMAC1_ASYNC, 56, 6),
+
+ /* CRU-->SOFTRST_CON57 */
+ CRU_RESET_OFFSET(SRST_PRESETN_IMG_BIU, 57, 7),
+ CRU_RESET_OFFSET(SRST_PRESETN_IMG_GRF, 57, 8),
+ CRU_RESET_OFFSET(SRST_HRESETN_IMG_BIU, 57, 9),
+ CRU_RESET_OFFSET(SRST_ARESETN_JPEG_BIU, 57, 10),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_IMG, 57, 11),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_IMG, 57, 12),
+ CRU_RESET_OFFSET(SRST_ARESETN_RGA_BIU, 57, 13),
+ CRU_RESET_OFFSET(SRST_ARESETN_VDPP_BIU, 57, 14),
+ CRU_RESET_OFFSET(SRST_ARESETN_EBC_BIU, 57, 15),
+
+ /* CRU-->SOFTRST_CON58 */
+ CRU_RESET_OFFSET(SRST_HRESETN_RGA2E_0, 58, 0),
+ CRU_RESET_OFFSET(SRST_ARESETN_RGA2E_0, 58, 1),
+ CRU_RESET_OFFSET(SRST_RESETN_CORE_RGA2E_0, 58, 2),
+ CRU_RESET_OFFSET(SRST_ARESETN_JPEG, 58, 3),
+ CRU_RESET_OFFSET(SRST_HRESETN_JPEG, 58, 4),
+ CRU_RESET_OFFSET(SRST_HRESETN_VDPP, 58, 5),
+ CRU_RESET_OFFSET(SRST_ARESETN_VDPP, 58, 6),
+ CRU_RESET_OFFSET(SRST_RESETN_CORE_VDPP, 58, 7),
+ CRU_RESET_OFFSET(SRST_HRESETN_EBC, 58, 13),
+ CRU_RESET_OFFSET(SRST_ARESETN_EBC, 58, 14),
+ CRU_RESET_OFFSET(SRST_DRESETN_EBC, 58, 15),
+
+ /* CRU-->SOFTRST_CON60 */
+ CRU_RESET_OFFSET(SRST_HRESETN_RKVENC_BIU, 60, 2),
+ CRU_RESET_OFFSET(SRST_ARESETN_RKVENC_BIU, 60, 3),
+ CRU_RESET_OFFSET(SRST_HRESETN_RKVENC, 60, 4),
+ CRU_RESET_OFFSET(SRST_ARESETN_RKVENC, 60, 5),
+ CRU_RESET_OFFSET(SRST_RESETN_RKVENC_CORE, 60, 6),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_VENC, 60, 7),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_VENC, 60, 8),
+
+ /* CRU-->SOFTRST_CON63 */
+ CRU_RESET_OFFSET(SRST_ARESETN_VI_BIU, 63, 3),
+ CRU_RESET_OFFSET(SRST_HRESETN_VI_BIU, 63, 4),
+ CRU_RESET_OFFSET(SRST_PRESETN_VI_BIU, 63, 5),
+ CRU_RESET_OFFSET(SRST_DRESETN_VICAP, 63, 6),
+ CRU_RESET_OFFSET(SRST_ARESETN_VICAP, 63, 7),
+ CRU_RESET_OFFSET(SRST_HRESETN_VICAP, 63, 8),
+ CRU_RESET_OFFSET(SRST_RESETN_ISP, 63, 10),
+ CRU_RESET_OFFSET(SRST_RESETN_ISP_VICAP, 63, 11),
+
+ /* CRU-->SOFTRST_CON64 */
+ CRU_RESET_OFFSET(SRST_RESETN_CORE_VPSS, 64, 1),
+ CRU_RESET_OFFSET(SRST_PRESETN_VI_GRF, 64, 2),
+ CRU_RESET_OFFSET(SRST_PRESETN_CSI_HOST_0, 64, 4),
+ CRU_RESET_OFFSET(SRST_PRESETN_CSI_HOST_1, 64, 5),
+ CRU_RESET_OFFSET(SRST_PRESETN_CSI_HOST_2, 64, 6),
+ CRU_RESET_OFFSET(SRST_PRESETN_CSI_HOST_3, 64, 7),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_VI, 64, 14),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_VI, 64, 15),
+
+ /* CRU-->SOFTRST_CON72 */
+ CRU_RESET_OFFSET(SRST_RESETN_CIFIN, 72, 0),
+
+ /* CRU-->SOFTRST_CON74 */
+ CRU_RESET_OFFSET(SRST_ARESETN_VOP_BIU, 74, 4),
+ CRU_RESET_OFFSET(SRST_ARESETN_VOP_FW, 74, 5),
+ CRU_RESET_OFFSET(SRST_HRESETN_VOP_BIU, 74, 6),
+ CRU_RESET_OFFSET(SRST_PRESETN_VOP_BIU, 74, 7),
+ CRU_RESET_OFFSET(SRST_HRESETN_VOP, 74, 8),
+ CRU_RESET_OFFSET(SRST_ARESETN_VOP, 74, 9),
+ CRU_RESET_OFFSET(SRST_DRESETN_VP0, 74, 13),
+
+ /* CRU-->SOFTRST_CON75 */
+ CRU_RESET_OFFSET(SRST_DRESETN_VP1, 75, 0),
+ CRU_RESET_OFFSET(SRST_PRESETN_VOPGRF, 75, 3),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_VOP, 75, 4),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_VOP, 75, 5),
+
+ /* CRU-->SOFTRST_CON78 */
+ CRU_RESET_OFFSET(SRST_PRESETN_DSIHOST0, 78, 1),
+ CRU_RESET_OFFSET(SRST_HRESETN_VO_BIU, 78, 10),
+ CRU_RESET_OFFSET(SRST_PRESETN_VO_BIU, 78, 12),
+ CRU_RESET_OFFSET(SRST_ARESETN_HDCP0_BIU, 78, 14),
+ CRU_RESET_OFFSET(SRST_PRESETN_VO_GRF, 78, 15),
+
+ /* CRU-->SOFTRST_CON79 */
+ CRU_RESET_OFFSET(SRST_PRESETN_HDCP0_TRNG_NS, 79, 0),
+ CRU_RESET_OFFSET(SRST_ARESETN_HDCP0, 79, 1),
+ CRU_RESET_OFFSET(SRST_HRESETN_HDCP0, 79, 2),
+ CRU_RESET_OFFSET(SRST_RESETN_HDCP0, 79, 4),
+ CRU_RESET_OFFSET(SRST_PRESETN_HDMITX0, 79, 14),
+ CRU_RESET_OFFSET(SRST_RESETN_HDMITX0_EARC, 79, 15),
+
+ /* CRU-->SOFTRST_CON80 */
+ CRU_RESET_OFFSET(SRST_RESETN_HDMITX0_REF, 80, 0),
+ CRU_RESET_OFFSET(SRST_PRESETN_EDP0, 80, 2),
+ CRU_RESET_OFFSET(SRST_RESETN_EDP0_24M, 80, 3),
+ CRU_RESET_OFFSET(SRST_MRESETN_SAI4, 80, 6),
+ CRU_RESET_OFFSET(SRST_HRESETN_SAI4, 80, 7),
+ CRU_RESET_OFFSET(SRST_MRESETN_SAI5, 80, 9),
+ CRU_RESET_OFFSET(SRST_HRESETN_SAI5, 80, 10),
+ CRU_RESET_OFFSET(SRST_HRESETN_SPDIF_TX2, 80, 11),
+ CRU_RESET_OFFSET(SRST_MRESETN_SPDIF_TX2, 80, 13),
+ CRU_RESET_OFFSET(SRST_HRESETN_SPDIF_RX1, 80, 14),
+ CRU_RESET_OFFSET(SRST_MRESETN_SPDIF_RX1, 80, 15),
+
+ /* CRU-->SOFTRST_CON81 */
+ CRU_RESET_OFFSET(SRST_RESETN_EBC_VOP_DCLK_VO, 81, 2),
+
+ /* CRU-->SOFTRST_CON82 */
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_VO, 82, 9),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_VO, 82, 10),
+
+ /* CRU-->SOFTRST_CON84 */
+ CRU_RESET_OFFSET(SRST_RESETN_GPU, 84, 3),
+ CRU_RESET_OFFSET(SRST_SYSRESETN_GPU, 84, 4),
+ CRU_RESET_OFFSET(SRST_PRESETN_GPU_BIU, 84, 8),
+ CRU_RESET_OFFSET(SRST_PORESETN_GPU_JTAG, 84, 10),
+ CRU_RESET_OFFSET(SRST_PRESETN_GPU_GRF, 84, 12),
+ CRU_RESET_OFFSET(SRST_RESETN_GPU_PVTPLL, 84, 13),
+ CRU_RESET_OFFSET(SRST_PRESETN_PVTPLL_GPU, 84, 14),
+ CRU_RESET_OFFSET(SRST_ARESETN_SLV_GPU_BIU, 84, 15),
+
+ /* CRU-->SOFTRST_CON85 */
+ CRU_RESET_OFFSET(SRST_ARESETN_GPU_BIU, 85, 0),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_GPU, 85, 1),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_GPU, 85, 2),
+
+ /* CRU-->SOFTRST_CON86 */
+ CRU_RESET_OFFSET(SRST_ARESETN_CENTER_BIU, 86, 4),
+ CRU_RESET_OFFSET(SRST_ARESETN_CENTER_FW_DDR, 86, 5),
+ CRU_RESET_OFFSET(SRST_ARESETN_CENTER_FW_GPU, 86, 7),
+ CRU_RESET_OFFSET(SRST_ARESETN_DMA2DDR, 86, 8),
+ CRU_RESET_OFFSET(SRST_ARESETN_DDR_SHAREMEM, 86, 9),
+ CRU_RESET_OFFSET(SRST_ARESETN_DDR_SHAREMEM_BIU, 86, 10),
+ CRU_RESET_OFFSET(SRST_ARESETN_DDR_SHAREMEM_FW, 86, 11),
+ CRU_RESET_OFFSET(SRST_HRESETN_CENTER_BIU, 86, 12),
+ CRU_RESET_OFFSET(SRST_HRESETN_CENTER_FW, 86, 13),
+ CRU_RESET_OFFSET(SRST_PRESETN_CENTER_GRF, 86, 14),
+ CRU_RESET_OFFSET(SRST_PRESETN_DMA2DDR, 86, 15),
+
+ /* CRU-->SOFTRST_CON87 */
+ CRU_RESET_OFFSET(SRST_PRESETN_CENTER_BIU, 87, 1),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_CENTER, 87, 2),
+ CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_CENTER, 87, 3),
+ CRU_RESET_OFFSET(SRST_RESETN_LINKSYM_HDMITXPHY0, 87, 9),
+
+ /* PHPPHY_CRU-->SOFTRST_CON00 */
+ PHPPHY_CRU_RESET_OFFSET(SRST_PRESETN_PHPPHY_CRU, 0, 1),
+ PHPPHY_CRU_RESET_OFFSET(SRST_PRESETN_PCIE2_COMBOPHY0, 0, 4),
+ PHPPHY_CRU_RESET_OFFSET(SRST_PRESETN_PCIE2_COMBOPHY0_GRF, 0, 5),
+ PHPPHY_CRU_RESET_OFFSET(SRST_PRESETN_PCIE2_COMBOPHY1, 0, 6),
+ PHPPHY_CRU_RESET_OFFSET(SRST_PRESETN_PCIE2_COMBOPHY1_GRF, 0, 7),
+ PHPPHY_CRU_RESET_OFFSET(SRST_PRESETN_USBPHY_GRF_0, 0, 8),
+ PHPPHY_CRU_RESET_OFFSET(SRST_PRESETN_USBPHY_GRF_1, 0, 9),
+ PHPPHY_CRU_RESET_OFFSET(SRST_RESETN_MPHY_INIT, 0, 10),
+ PHPPHY_CRU_RESET_OFFSET(SRST_PRESETN_MPHY_GRF, 0, 11),
+ PHPPHY_CRU_RESET_OFFSET(SRST_PRESETN_VCCIO7_IOC, 0, 12),
+ PHPPHY_CRU_RESET_OFFSET(SRST_RESETN_USB2DEBUG, 0, 13),
+ PHPPHY_CRU_RESET_OFFSET(SRST_PRESETN_PCIEPHY2, 0, 14),
+ PHPPHY_CRU_RESET_OFFSET(SRST_PRESETN_PCIEPHY2_GRF, 0, 15),
+
+ /* PHPPHY_CRU-->SOFTRST_CON01 */
+ PHPPHY_CRU_RESET_OFFSET(SRST_SRESETN_APB2ASB_USBMPHY_PHPPHY, 1, 0),
+ PHPPHY_CRU_RESET_OFFSET(SRST_PRESETN_APB2ASB_USBMPHY_PHPPHY, 1, 1),
+ PHPPHY_CRU_RESET_OFFSET(SRST_RESETN_OTGPHY_0, 1, 4),
+ PHPPHY_CRU_RESET_OFFSET(SRST_RESETN_OTGPHY_1, 1, 5),
+ PHPPHY_CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_PHPPHY, 1, 6),
+ PHPPHY_CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_PHPPHY, 1, 7),
+
+ /* PHPPHY_CRU-->SOFTRST_CON02 */
+ PHPPHY_CRU_RESET_OFFSET(SRST_RESETN_PCIEPHY2, 2, 4),
+ PHPPHY_CRU_RESET_OFFSET(SRST_RESETN_PCIE0_PIPE_PHY, 2, 5),
+ PHPPHY_CRU_RESET_OFFSET(SRST_RESETN_PCIE1_PIPE_PHY, 2, 8),
+
+ /* SECURE_CRU-->SOFTRST_CON00 */
+ SECURE_CRU_RESET_OFFSET(SRST_HRESETN_CRYPTO_NS, 0, 3),
+ SECURE_CRU_RESET_OFFSET(SRST_HRESETN_TRNG_NS, 0, 4),
+ SECURE_CRU_RESET_OFFSET(SRST_PRESETN_SECURE_NS_BIU, 0, 5),
+ SECURE_CRU_RESET_OFFSET(SRST_ARESETN_SECURE_HIGH_BIU, 0, 6),
+ SECURE_CRU_RESET_OFFSET(SRST_HRESETN_SECURE_NS_BIU, 0, 7),
+ SECURE_CRU_RESET_OFFSET(SRST_PRESETN_OTPC_NS, 0, 8),
+ SECURE_CRU_RESET_OFFSET(SRST_RESETN_OTPC_NS, 0, 9),
+
+ /* PMU1_CRU-->SOFTRST_CON03 */
+ PMU1_CRU_RESET_OFFSET(SRST_PRESETN_APB2ASB_PMU1, 3, 6),
+ PMU1_CRU_RESET_OFFSET(SRST_SRESETN_APB2ASB_PMU1, 3, 7),
+ PMU1_CRU_RESET_OFFSET(SRST_HRESETN_PMU1_BIU, 3, 9),
+ PMU1_CRU_RESET_OFFSET(SRST_HRESETN_PMU1_FW, 3, 10),
+ PMU1_CRU_RESET_OFFSET(SRST_PRESETN_PMU1_BIU, 3, 11),
+ PMU1_CRU_RESET_OFFSET(SRST_HRESETN_PMU_CM0_BIU, 3, 12),
+ PMU1_CRU_RESET_OFFSET(SRST_CORERESETN_N100, 3, 13),
+ PMU1_CRU_RESET_OFFSET(SRST_PORESETN_N100, 3, 14),
+
+ /* PMU1_CRU-->SOFTRST_CON04 */
+ PMU1_CRU_RESET_OFFSET(SRST_PRESETN_CRU_PMU1, 4, 2),
+ PMU1_CRU_RESET_OFFSET(SRST_PRESETN_PMU1_GRF, 4, 4),
+ PMU1_CRU_RESET_OFFSET(SRST_PRESETN_PMU1_IOC, 4, 5),
+ PMU1_CRU_RESET_OFFSET(SRST_PRESETN_PMU1WDT, 4, 6),
+ PMU1_CRU_RESET_OFFSET(SRST_TRESETN_PMU1WDT, 4, 7),
+ PMU1_CRU_RESET_OFFSET(SRST_PRESETN_PMUTIMER, 4, 8),
+ PMU1_CRU_RESET_OFFSET(SRST_RESETN_PMUTIMER0, 4, 10),
+ PMU1_CRU_RESET_OFFSET(SRST_RESETN_PMUTIMER1, 4, 11),
+ PMU1_CRU_RESET_OFFSET(SRST_PRESETN_PWM0, 4, 12),
+ PMU1_CRU_RESET_OFFSET(SRST_RESETN_PWM0, 4, 13),
+
+ /* PMU1_CRU-->SOFTRST_CON05 */
+ PMU1_CRU_RESET_OFFSET(SRST_PRESETN_I2C0, 5, 2),
+ PMU1_CRU_RESET_OFFSET(SRST_RESETN_I2C0, 5, 3),
+ PMU1_CRU_RESET_OFFSET(SRST_SRESETN_UART1, 5, 6),
+ PMU1_CRU_RESET_OFFSET(SRST_PRESETN_UART1, 5, 7),
+ PMU1_CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_PMU1, 5, 12),
+ PMU1_CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_PMU1, 5, 13),
+ PMU1_CRU_RESET_OFFSET(SRST_RESETN_PDM0, 5, 14),
+
+ /* PMU1_CRU-->SOFTRST_CON06 */
+ PMU1_CRU_RESET_OFFSET(SRST_HRESETN_PDM0, 6, 0),
+ PMU1_CRU_RESET_OFFSET(SRST_MRESETN_PDM0, 6, 1),
+ PMU1_CRU_RESET_OFFSET(SRST_HRESETN_VAD, 6, 2),
+ PMU1_CRU_RESET_OFFSET(SRST_PRESETN_RCOSC, 6, 10),
+ PMU1_CRU_RESET_OFFSET(SRST_RESETN_RCOSC, 6, 11),
+
+ /* PMU1_CRU-->SOFTRST_CON07 */
+ PMU1_CRU_RESET_OFFSET(SRST_PRESETN_PMU0GRF, 7, 4),
+ PMU1_CRU_RESET_OFFSET(SRST_PRESETN_PMU0IOC, 7, 5),
+ PMU1_CRU_RESET_OFFSET(SRST_PRESETN_GPIO0, 7, 6),
+ PMU1_CRU_RESET_OFFSET(SRST_DBRESETN_GPIO0, 7, 7),
+
+ /* DDR0_CRU-->SOFTRST_CON00 */
+ DDR0_CRU_RESET_OFFSET(SRST_RESETN_DDRPHY1X, 0, 1),
+
+ /* DDR0_CRU-->SOFTRST_CON01 */
+ DDR0_CRU_RESET_OFFSET(SRST_PRESETN_DDRPHY_CRU, 1, 3),
+ DDR0_CRU_RESET_OFFSET(SRST_PRESETN_DDRPHY, 1, 4),
+
+ /* BIGCORE_CRU-->SOFTRST_CON00 */
+ BIGCORE_CRU_RESET_OFFSET(SRST_RESETN_REF_PVTPLL_BIGCORE, 0, 4),
+ BIGCORE_CRU_RESET_OFFSET(SRST_PRESETN_BIGCORE_BIU, 0, 6),
+ BIGCORE_CRU_RESET_OFFSET(SRST_PRESETN_BIGCORE_GRF, 0, 7),
+ BIGCORE_CRU_RESET_OFFSET(SRST_PRESETN_BIGCORE_CRU, 0, 8),
+ BIGCORE_CRU_RESET_OFFSET(SRST_PRESETN_PVTPLL_BIGCORE, 0, 9),
+ BIGCORE_CRU_RESET_OFFSET(SRST_NBIGCOREPORESET0, 0, 12),
+ BIGCORE_CRU_RESET_OFFSET(SRST_NBIGCOREPORESET1, 0, 13),
+ BIGCORE_CRU_RESET_OFFSET(SRST_NBIGCORESET0, 0, 14),
+ BIGCORE_CRU_RESET_OFFSET(SRST_NBIGCORESET1, 0, 15),
+
+ /* BIGCORE_CRU-->SOFTRST_CON01 */
+ BIGCORE_CRU_RESET_OFFSET(SRST_NL2RESET_BIGCORE, 1, 0),
+ BIGCORE_CRU_RESET_OFFSET(SRST_ARESETN_ADB400_A73_ACE, 1, 4),
+ BIGCORE_CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_BIGCORE, 1, 5),
+ BIGCORE_CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_BIGCORE, 1, 6),
+ BIGCORE_CRU_RESET_OFFSET(SRST_PRESETN_DBG_BIGCORE, 1, 7),
+
+ /* LITCORE0_CRU-->SOFTRST_CON00 */
+ LITCORE0_CRU_RESET_OFFSET(SRST_RESETN_REF_LITCORE0_PVTPLL, 0, 0),
+ LITCORE0_CRU_RESET_OFFSET(SRST_NLITCOREPORESET0, 0, 4),
+ LITCORE0_CRU_RESET_OFFSET(SRST_NLITCOREPORESET1, 0, 5),
+ LITCORE0_CRU_RESET_OFFSET(SRST_NLITCOREPORESET2, 0, 6),
+ LITCORE0_CRU_RESET_OFFSET(SRST_NLITCOREPORESET3, 0, 7),
+ LITCORE0_CRU_RESET_OFFSET(SRST_NLITCORESET0, 0, 8),
+ LITCORE0_CRU_RESET_OFFSET(SRST_NLITCORESET1, 0, 9),
+ LITCORE0_CRU_RESET_OFFSET(SRST_NLITCORESET2, 0, 10),
+ LITCORE0_CRU_RESET_OFFSET(SRST_NLITCORESET3, 0, 11),
+ LITCORE0_CRU_RESET_OFFSET(SRST_NL2RESET_LITCORE0, 0, 12),
+ LITCORE0_CRU_RESET_OFFSET(SRST_PRESETN_DBG_LITCORE0, 0, 14),
+ LITCORE0_CRU_RESET_OFFSET(SRST_ARESETN_ADB400_A53_ACE_LITCORE0, 0, 15),
+
+ /* LITCORE0_CRU-->SOFTRST_CON01 */
+ LITCORE0_CRU_RESET_OFFSET(SRST_PRESETN_LITCORE0_GRF, 1, 2),
+ LITCORE0_CRU_RESET_OFFSET(SRST_PRESETN_LITCORE0_BIU, 1, 3),
+ LITCORE0_CRU_RESET_OFFSET(SRST_PRESETN_PVTPLL_LITCORE0, 1, 4),
+ LITCORE0_CRU_RESET_OFFSET(SRST_PRESETN_LITCORE0_CRU, 1, 5),
+ LITCORE0_CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_LITCORE0, 1, 6),
+ LITCORE0_CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_LITCORE0, 1, 7),
+
+ /* LITCORE1_CRU-->SOFTRST_CON00 */
+ LITCORE1_CRU_RESET_OFFSET(SRST_RESETN_REF_LITCORE1_PVTPLL, 0, 0),
+ LITCORE1_CRU_RESET_OFFSET(SRST_NLITCOREPORESET4, 0, 4),
+ LITCORE1_CRU_RESET_OFFSET(SRST_NLITCOREPORESET5, 0, 5),
+ LITCORE1_CRU_RESET_OFFSET(SRST_NLITCORESET4, 0, 6),
+ LITCORE1_CRU_RESET_OFFSET(SRST_NLITCORESET5, 0, 7),
+ LITCORE1_CRU_RESET_OFFSET(SRST_NL2RESET_LITCORE1, 0, 8),
+ LITCORE1_CRU_RESET_OFFSET(SRST_PRESETN_DBG_LITCORE1, 0, 10),
+ LITCORE1_CRU_RESET_OFFSET(SRST_ARESETN_ADB400_A53_ACE_LITCORE1, 0, 11),
+ LITCORE1_CRU_RESET_OFFSET(SRST_PRESETN_LITCORE1_GRF, 0, 14),
+ LITCORE1_CRU_RESET_OFFSET(SRST_PRESETN_LITCORE1_BIU, 0, 15),
+
+ /* LITCORE1_CRU-->SOFTRST_CON01 */
+ LITCORE1_CRU_RESET_OFFSET(SRST_PRESETN_PVTPLL_LITCORE1, 1, 0),
+ LITCORE1_CRU_RESET_OFFSET(SRST_PRESETN_LITCORE1_CRU, 1, 1),
+ LITCORE1_CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_LITCORE1, 1, 2),
+ LITCORE1_CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_LITCORE1, 1, 3),
+
+ /* CCI_CRU-->SOFTRST_CON01 */
+ CCI_CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_24M_CCI, 1, 7),
+ CCI_CRU_RESET_OFFSET(SRST_RESETN_TEST_JUDGE_CCI, 1, 8),
+ CCI_CRU_RESET_OFFSET(SRST_ARESETN_CPE, 1, 11),
+ CCI_CRU_RESET_OFFSET(SRST_PRESETN_CCI_BIU, 1, 12),
+ CCI_CRU_RESET_OFFSET(SRST_PRESETN_CCI_FW, 1, 13),
+ CCI_CRU_RESET_OFFSET(SRST_ARESETN_CCI_BIU, 1, 14),
+ CCI_CRU_RESET_OFFSET(SRST_ARESETN_CCI_FW, 1, 15),
+
+ /* CCI_CRU-->SOFTRST_CON02 */
+ CCI_CRU_RESET_OFFSET(SRST_PRESETN_DBG_SYS, 2, 0),
+ CCI_CRU_RESET_OFFSET(SRST_PRESETN_CCI_GRF, 2, 1),
+ CCI_CRU_RESET_OFFSET(SRST_PRESETN_CCI_CRU, 2, 2),
+ CCI_CRU_RESET_OFFSET(SRST_ARESETN_CCI, 2, 3),
+ CCI_CRU_RESET_OFFSET(SRST_PORESETN_JTAG, 2, 4),
+ CCI_CRU_RESET_OFFSET(SRST_PRESETN_DBG_M, 2, 5),
+ CCI_CRU_RESET_OFFSET(SRST_ARESETN_ADB400_CCI_A73, 2, 6),
+ CCI_CRU_RESET_OFFSET(SRST_ARESETN_ADB400_CCI_A53_0, 2, 7),
+ CCI_CRU_RESET_OFFSET(SRST_ARESETN_ADB400_CCI_A53_1, 2, 8),
+ CCI_CRU_RESET_OFFSET(SRST_PRESETN_PVTPLL_CCI, 2, 9),
+ CCI_CRU_RESET_OFFSET(SRST_PRESETN_CCI_SPINLOCK, 2, 10),
+ CCI_CRU_RESET_OFFSET(SRST_PRESETN_DBG_M_BIU, 2, 11),
+ CCI_CRU_RESET_OFFSET(SRST_RESETN_REF_CCI_PVTPLL, 2, 12),
+};
+
+void rk3572_rst_init(struct device_node *np, void __iomem *reg_base)
+{
+ rockchip_register_softrst_lut(np,
+ rk3572_register_offset,
+ ARRAY_SIZE(rk3572_register_offset),
+ reg_base + RK3572_SOFTRST_CON(0),
+ ROCKCHIP_SOFTRST_HIWORD_MASK);
+}
+EXPORT_SYMBOL_GPL(rk3572_rst_init);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Rockchip RK3572 Soft Reset Driver");
+MODULE_AUTHOR("Elaine Zhang <zhangqing@rock-chips.com>");
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 08/27] pinctrl: rockchip: Add RK3572 support
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (6 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 07/27] clk: rockchip: Add RK3572 clock and reset support Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 09/27] gpio: rockchip: Add RK3572 GPIO support Cunhao Lu via B4 Relay
` (19 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Support RK3572 pinmux, bias, drive-strength, and Schmitt controls.
Enable input buffers during mux changes for the RGMII receive clocks.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 230 ++++++++++++++++++++++++++++++++++++-
drivers/pinctrl/pinctrl-rockchip.h | 1 +
2 files changed, 230 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index ba47b6f323cc..6d9a6510b343 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1363,6 +1363,10 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
if (bank->recalced_mask & BIT(pin))
rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
+ if (ctrl->type == RK3572 && bank->bank_num == 0 &&
+ pin >= RK_PB4 && pin <= RK_PB7)
+ reg += 0x2000;
+
if (ctrl->type == RK3576) {
if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
@@ -1421,6 +1425,24 @@ static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
return 0;
}
+static int rk3572_enable_input(struct rockchip_pin_bank *bank, int pin)
+{
+ static const u32 offsets[] = { 0x300, 0x10310, 0x12320, 0x14330, 0x14340 };
+ struct rockchip_pinctrl *info = bank->drvdata;
+ u32 reg, bit = pin % 8;
+
+ if (bank->bank_num >= ARRAY_SIZE(offsets))
+ return -EINVAL;
+
+ reg = offsets[bank->bank_num] + pin / 8 * 4;
+ if (bank->bank_num == 0 && pin >= RK_PB4)
+ reg += 0x2000;
+ else if (bank->bank_num == 4 && pin >= RK_PC0)
+ reg -= 0x10000;
+
+ return regmap_write(info->regmap_base, reg, BIT(bit + 16) | BIT(bit));
+}
+
/*
* Set a new mux function for a pin.
*
@@ -1498,6 +1520,10 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
if (bank->recalced_mask & BIT(pin))
rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
+ if (ctrl->type == RK3572 && bank->bank_num == 0 &&
+ pin >= RK_PB4 && pin <= RK_PB7)
+ reg += 0x2000;
+
if (ctrl->type == RK3576) {
if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
@@ -1568,8 +1594,13 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
rmask = data | (data >> 16);
data |= (mux & mask) << bit;
ret = regmap_update_bits(regmap, reg, rmask, data);
+ if (ret)
+ return ret;
- return ret;
+ if (ctrl->type == RK3572)
+ return rk3572_enable_input(bank, pin);
+
+ return 0;
}
#define PX30_PULL_PMU_OFFSET 0x10
@@ -3097,6 +3128,151 @@ static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
return 0;
}
+#define RK3572_DRV_BITS_PER_PIN 4
+#define RK3572_DRV_PINS_PER_REG 4
+#define RK3572_DRV_GPIO0_OFFSET 0x100
+#define RK3572_DRV_GPIO1_OFFSET 0x10120
+#define RK3572_DRV_GPIO2_OFFSET 0x12140
+#define RK3572_DRV_GPIO3_OFFSET 0x14160
+#define RK3572_DRV_GPIO4_OFFSET 0x14180
+
+static int rk3572_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ *regmap = info->regmap_base;
+
+ switch (bank->bank_num) {
+ case 0:
+ *reg = RK3572_DRV_GPIO0_OFFSET;
+ if (pin_num >= 12)
+ *reg += 0x2000;
+ break;
+ case 1:
+ *reg = RK3572_DRV_GPIO1_OFFSET;
+ break;
+ case 2:
+ *reg = RK3572_DRV_GPIO2_OFFSET;
+ break;
+ case 3:
+ *reg = RK3572_DRV_GPIO3_OFFSET;
+ break;
+ case 4:
+ *reg = RK3572_DRV_GPIO4_OFFSET;
+ if (pin_num >= 16)
+ *reg -= 0x10000;
+ break;
+ default:
+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
+ return -EINVAL;
+ }
+
+ *reg += ((pin_num / RK3572_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3572_DRV_PINS_PER_REG;
+ *bit *= RK3572_DRV_BITS_PER_PIN;
+
+ return 0;
+}
+
+#define RK3572_PULL_BITS_PER_PIN 2
+#define RK3572_PULL_PINS_PER_REG 8
+#define RK3572_PULL_GPIO0_OFFSET 0x200
+#define RK3572_PULL_GPIO1_OFFSET 0x10210
+#define RK3572_PULL_GPIO2_OFFSET 0x12220
+#define RK3572_PULL_GPIO3_OFFSET 0x14230
+#define RK3572_PULL_GPIO4_OFFSET 0x14240
+
+static int rk3572_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ *regmap = info->regmap_base;
+
+ switch (bank->bank_num) {
+ case 0:
+ *reg = RK3572_PULL_GPIO0_OFFSET;
+ if (pin_num >= 12)
+ *reg += 0x2000;
+ break;
+ case 1:
+ *reg = RK3572_PULL_GPIO1_OFFSET;
+ break;
+ case 2:
+ *reg = RK3572_PULL_GPIO2_OFFSET;
+ break;
+ case 3:
+ *reg = RK3572_PULL_GPIO3_OFFSET;
+ break;
+ case 4:
+ *reg = RK3572_PULL_GPIO4_OFFSET;
+ if (pin_num >= 16)
+ *reg -= 0x10000;
+ break;
+ default:
+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
+ return -EINVAL;
+ }
+
+ *reg += ((pin_num / RK3572_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3572_PULL_PINS_PER_REG;
+ *bit *= RK3572_PULL_BITS_PER_PIN;
+
+ return 0;
+}
+
+#define RK3572_SMT_BITS_PER_PIN 1
+#define RK3572_SMT_PINS_PER_REG 8
+#define RK3572_SMT_GPIO0_OFFSET 0x400
+#define RK3572_SMT_GPIO1_OFFSET 0x10410
+#define RK3572_SMT_GPIO2_OFFSET 0x12420
+#define RK3572_SMT_GPIO3_OFFSET 0x14430
+#define RK3572_SMT_GPIO4_OFFSET 0x14440
+
+static int rk3572_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ *regmap = info->regmap_base;
+
+ switch (bank->bank_num) {
+ case 0:
+ *reg = RK3572_SMT_GPIO0_OFFSET;
+ if (pin_num >= 12)
+ *reg += 0x2000;
+ break;
+ case 1:
+ *reg = RK3572_SMT_GPIO1_OFFSET;
+ break;
+ case 2:
+ *reg = RK3572_SMT_GPIO2_OFFSET;
+ break;
+ case 3:
+ *reg = RK3572_SMT_GPIO3_OFFSET;
+ break;
+ case 4:
+ *reg = RK3572_SMT_GPIO4_OFFSET;
+ if (pin_num >= 16)
+ *reg -= 0x10000;
+ break;
+ default:
+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
+ return -EINVAL;
+ }
+
+ *reg += ((pin_num / RK3572_SMT_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3572_SMT_PINS_PER_REG;
+ *bit *= RK3572_SMT_BITS_PER_PIN;
+
+ return 0;
+}
+
#define RK3576_DRV_BITS_PER_PIN 4
#define RK3576_DRV_PINS_PER_REG 4
#define RK3576_DRV_GPIO0_AL_OFFSET 0x10
@@ -3441,6 +3617,18 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
if (ret)
return ret;
+ if (ctrl->type == RK3572) {
+ ret = regmap_read(regmap, reg, &data);
+ if (ret)
+ return ret;
+ data >>= bit;
+ if ((bank->bank_num == 0 && pin_num < 12) ||
+ (bank->bank_num == 4 && (pin_num == 24 || pin_num == 25)))
+ return ((data & BIT(1)) >> 1) | ((data & BIT(0)) << 1);
+ return ((data & BIT(2)) >> 2) | ((data & BIT(0)) << 2) |
+ (data & BIT(1));
+ }
+
switch (drv_type) {
case DRV_TYPE_IO_1V8_3V0_AUTO:
case DRV_TYPE_IO_3V3_ONLY:
@@ -3559,6 +3747,22 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
rmask_bits = RK3568_DRV_BITS_PER_PIN;
ret = (1 << (strength + 1)) - 1;
goto config;
+ } else if (ctrl->type == RK3572) {
+ if (strength < 0 || strength > 7)
+ return -EINVAL;
+ rmask_bits = RK3572_DRV_BITS_PER_PIN;
+ if ((bank->bank_num == 0 && pin_num < 12) ||
+ (bank->bank_num == 4 && (pin_num == 24 || pin_num == 25))) {
+ /* Only four drive-strength levels are supported. */
+ if (strength > 3)
+ return -EINVAL;
+ ret = ((strength & BIT(1)) >> 1) | ((strength & BIT(0)) << 1);
+ } else {
+ ret = ((strength & BIT(2)) >> 2) |
+ ((strength & BIT(0)) << 2) |
+ (strength & BIT(1));
+ }
+ goto config;
} else if (ctrl->type == RK3576) {
rmask_bits = RK3576_DRV_BITS_PER_PIN;
ret = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1));
@@ -3717,6 +3921,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
case RK3528:
case RK3562:
case RK3568:
+ case RK3572:
case RK3576:
case RK3588:
pull_type = bank->pull_type[pin_num / 8];
@@ -3786,6 +3991,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
case RK3528:
case RK3562:
case RK3568:
+ case RK3572:
case RK3576:
case RK3588:
pull_type = bank->pull_type[pin_num / 8];
@@ -4084,6 +4290,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
case RK3528:
case RK3562:
case RK3568:
+ case RK3572:
case RK3576:
case RK3588:
return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
@@ -4296,6 +4503,7 @@ static const struct pinconf_ops rockchip_pinconf_ops = {
static const struct of_device_id rockchip_bank_match[] = {
{ .compatible = "rockchip,gpio-bank" },
+ { .compatible = "rockchip,rk3572-gpio-bank" },
{ .compatible = "rockchip,rk3188-gpio-bank0" },
{},
};
@@ -5643,6 +5851,24 @@ static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
PULL_TYPE_IO_1V8_ONLY, \
PULL_TYPE_IO_1V8_ONLY)
+static struct rockchip_pin_bank rk3572_pin_banks[] = {
+ RK3576_PIN_BANK(0, "gpio0", 0, 0x8, 0x2010, 0x2018),
+ RK3576_PIN_BANK(1, "gpio1", 0x10020, 0x10028, 0x10030, 0x10038),
+ RK3576_PIN_BANK(2, "gpio2", 0x12040, 0x12048, 0x12050, 0x12058),
+ RK3576_PIN_BANK(3, "gpio3", 0x14060, 0x14068, 0x14070, 0x14078),
+ RK3576_PIN_BANK(4, "gpio4", 0x14080, 0x14088, 0x4090, 0x4098),
+};
+
+static struct rockchip_pin_ctrl rk3572_pin_ctrl __maybe_unused = {
+ .pin_banks = rk3572_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3572_pin_banks),
+ .label = "RK3572-GPIO",
+ .type = RK3572,
+ .pull_calc_reg = rk3572_calc_pull_reg_and_bit,
+ .drv_calc_reg = rk3572_calc_drv_reg_and_bit,
+ .schmitt_calc_reg = rk3572_calc_schmitt_reg_and_bit,
+};
+
static struct rockchip_pin_bank rk3576_pin_banks[] = {
RK3576_PIN_BANK(0, "gpio0", 0, 0x8, 0x2004, 0x200C),
RK3576_PIN_BANK(1, "gpio1", 0x4020, 0x4028, 0x4030, 0x4038),
@@ -5727,6 +5953,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.data = &rk3562_pin_ctrl },
{ .compatible = "rockchip,rk3568-pinctrl",
.data = &rk3568_pin_ctrl },
+ { .compatible = "rockchip,rk3572-pinctrl",
+ .data = &rk3572_pin_ctrl },
{ .compatible = "rockchip,rk3576-pinctrl",
.data = &rk3576_pin_ctrl },
{ .compatible = "rockchip,rk3588-pinctrl",
diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h
index 950097699643..553197f6dc69 100644
--- a/drivers/pinctrl/pinctrl-rockchip.h
+++ b/drivers/pinctrl/pinctrl-rockchip.h
@@ -203,6 +203,7 @@ enum rockchip_pinctrl_type {
RK3528,
RK3562,
RK3568,
+ RK3572,
RK3576,
RK3588,
};
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 09/27] gpio: rockchip: Add RK3572 GPIO support
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (7 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 08/27] pinctrl: rockchip: Add RK3572 support Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 10/27] pmdomain: rockchip: Add RK3572 boot peripheral domains Cunhao Lu via B4 Relay
` (18 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Support GPIO V2.7, four parent interrupts, and firmware-provided
interrupt-group masks. Keep all pins on the primary interrupt when group
queries are unavailable.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
drivers/gpio/gpio-rockchip.c | 91 +++++++++++++++++++++++++++++++++----
drivers/pinctrl/pinctrl-rockchip.h | 8 +++-
include/soc/rockchip/rockchip_sip.h | 5 ++
3 files changed, 92 insertions(+), 12 deletions(-)
diff --git a/drivers/gpio/gpio-rockchip.c b/drivers/gpio/gpio-rockchip.c
index 77b239a9a601e..35894a68b5446 100644
--- a/drivers/gpio/gpio-rockchip.c
+++ b/drivers/gpio/gpio-rockchip.c
@@ -6,6 +6,7 @@
* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
*/
+#include <linux/arm-smccc.h>
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/device.h>
@@ -21,6 +22,7 @@
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include <soc/rockchip/rockchip_sip.h>
#include "../pinctrl/core.h"
#include "../pinctrl/pinctrl-rockchip.h"
@@ -35,6 +37,7 @@
#define GPIO_TYPE_V2 (0x01000C2B)
#define GPIO_TYPE_V2_1 (0x0101157C)
#define GPIO_TYPE_V2_2 (0x010219C8)
+#define GPIO_TYPE_V2_7 (0x01074D2E)
static const struct rockchip_gpio_regs gpio_regs_v1 = {
.port_dr = 0x00,
@@ -209,12 +212,27 @@ static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) {
div_debounce_support = true;
freq = clk_get_rate(bank->db_clk);
- max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq;
- if (debounce > max_debounce)
- return -EINVAL;
- div = debounce * freq;
- div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1;
+ if (of_device_is_compatible(bank->of_node, "rockchip,rk3572-gpio-bank")) {
+ if (!freq)
+ return -EINVAL;
+
+ div = (u64)(GENMASK(23, 0) + 1) * USEC_PER_SEC;
+ max_debounce = div_u64(div, 2 * freq);
+ if (debounce > max_debounce)
+ return -EINVAL;
+
+ div = (u64)debounce * freq * 2;
+ div_reg = DIV_ROUND_CLOSEST_ULL(div, USEC_PER_SEC);
+ div_reg = div_reg ? div_reg - 1 : 0;
+ } else {
+ max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq;
+ if (debounce > max_debounce)
+ return -EINVAL;
+
+ div = debounce * freq;
+ div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1;
+ }
} else {
div_debounce_support = false;
}
@@ -342,6 +360,12 @@ static void rockchip_irq_demux(struct irq_desc *desc)
chained_irq_enter(chip, desc);
pending = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status);
+ for (unsigned int i = 0; i < bank->nr_irqs; i++) {
+ if (bank->irqs[i] == irq_desc_get_irq(desc)) {
+ pending &= bank->irq_masks[i];
+ break;
+ }
+ }
for_each_set_bit(irq, &pending, 32) {
dev_dbg(bank->dev, "handling irq %d\n", irq);
@@ -568,8 +592,9 @@ static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en);
gc->mask_cache = 0xffffffff;
- irq_set_chained_handler_and_data(bank->irq,
- rockchip_irq_demux, bank);
+ for (unsigned int i = 0; i < bank->nr_irqs; i++)
+ irq_set_chained_handler_and_data(bank->irqs[i],
+ rockchip_irq_demux, bank);
return 0;
}
@@ -645,6 +670,36 @@ static void rockchip_clk_put(void *data)
clk_put(clk);
}
+static int rockchip_gpio_read_irq_groups(struct rockchip_pin_bank *bank)
+{
+ struct arm_smccc_res res;
+ u32 assigned = 0;
+ int status;
+
+ for (unsigned int i = 1; i < bank->nr_irqs; i++) {
+ arm_smccc_smc(ROCKCHIP_SIP_GPIO_CONFIG, ROCKCHIP_SIP_GPIO_GET_GROUP,
+ bank->bank_num, i, 0, 0, 0, 0, &res);
+ status = (int)res.a0;
+ if (i == 1 && (status == SMCCC_RET_NOT_SUPPORTED ||
+ status == ROCKCHIP_SIP_RET_NOT_SUPPORTED)) {
+ /* Older firmware leaves all pins on the primary IRQ. */
+ dev_dbg(bank->dev, "GPIO group query unsupported: %d\n",
+ status);
+ break;
+ }
+ if (status)
+ return dev_err_probe(bank->dev, -EIO,
+ "cannot read interrupt group %u: %d\n",
+ i, status);
+ bank->irq_masks[i] = res.a1;
+ if (assigned & bank->irq_masks[i])
+ return -EINVAL;
+ assigned |= bank->irq_masks[i];
+ }
+ bank->irq_masks[0] = ~assigned;
+ return 0;
+}
+
static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
{
struct platform_device *pdev = to_platform_device(bank->dev);
@@ -654,10 +709,23 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
if (IS_ERR(bank->reg_base))
return PTR_ERR(bank->reg_base);
- ret = platform_get_irq(pdev, 0);
+ ret = platform_irq_count(pdev);
if (ret < 0)
return ret;
- bank->irq = ret;
+ if (ret != (of_device_is_compatible(bank->of_node,
+ "rockchip,rk3572-gpio-bank") ? 4 : 1))
+ return -EINVAL;
+ bank->nr_irqs = ret;
+ for (unsigned int i = 0; i < bank->nr_irqs; i++) {
+ ret = platform_get_irq(pdev, i);
+ if (ret < 0)
+ return ret;
+ bank->irqs[i] = ret;
+ }
+
+ ret = rockchip_gpio_read_irq_groups(bank);
+ if (ret)
+ return ret;
bank->clk = devm_clk_get_enabled(bank->dev, NULL);
if (IS_ERR(bank->clk))
@@ -669,6 +737,7 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
case GPIO_TYPE_V2:
case GPIO_TYPE_V2_1:
case GPIO_TYPE_V2_2:
+ case GPIO_TYPE_V2_7:
bank->gpio_regs = &gpio_regs_v2;
bank->gpio_type = GPIO_TYPE_V2;
bank->db_clk = of_clk_get(bank->of_node, 1);
@@ -797,7 +866,8 @@ static void rockchip_gpio_remove(struct platform_device *pdev)
{
struct rockchip_pin_bank *bank = platform_get_drvdata(pdev);
- irq_set_chained_handler_and_data(bank->irq, NULL, NULL);
+ for (unsigned int i = 0; i < bank->nr_irqs; i++)
+ irq_set_chained_handler_and_data(bank->irqs[i], NULL, NULL);
if (bank->domain) {
irq_domain_remove_generic_chips(bank->domain);
irq_domain_remove(bank->domain);
@@ -807,6 +877,7 @@ static void rockchip_gpio_remove(struct platform_device *pdev)
static const struct of_device_id rockchip_gpio_match[] = {
{ .compatible = "rockchip,gpio-bank", },
+ { .compatible = "rockchip,rk3572-gpio-bank" },
{ .compatible = "rockchip,rk3188-gpio-bank0" },
{ },
};
diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h
index 553197f6dc690..058b58dcde404 100644
--- a/drivers/pinctrl/pinctrl-rockchip.h
+++ b/drivers/pinctrl/pinctrl-rockchip.h
@@ -302,7 +302,9 @@ struct rockchip_drv {
* bank has its own IOC block
* @clk: clock of the gpio bank
* @db_clk: clock of the gpio debounce
- * @irq: interrupt of the gpio bank
+ * @irqs: parent interrupts of the GPIO bank
+ * @irq_masks: pins assigned to each parent interrupt
+ * @nr_irqs: number of parent interrupts
* @saved_masks: Saved content of GPIO_INTEN at suspend time.
* @pin_base: first pin number
* @nr_pins: number of pins in this bank
@@ -331,7 +333,9 @@ struct rockchip_pin_bank {
struct regmap *regmap_ioc;
struct clk *clk;
struct clk *db_clk;
- int irq;
+ unsigned int irqs[4];
+ u32 irq_masks[4];
+ unsigned int nr_irqs;
u32 saved_masks;
u32 pin_base;
u8 nr_pins;
diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h
index 501ad1fedb201..984272ede3baf 100644
--- a/include/soc/rockchip/rockchip_sip.h
+++ b/include/soc/rockchip/rockchip_sip.h
@@ -20,4 +20,9 @@
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08
+#define ROCKCHIP_SIP_RET_NOT_SUPPORTED -2
+
+#define ROCKCHIP_SIP_GPIO_CONFIG 0x8200002c
+#define ROCKCHIP_SIP_GPIO_GET_GROUP 0
+
#endif
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 10/27] pmdomain: rockchip: Add RK3572 boot peripheral domains
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (8 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 09/27] gpio: rockchip: Add RK3572 GPIO support Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 11/27] dt-bindings: i2c: rk3x: Add RK3572 Cunhao Lu via B4 Relay
` (17 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Add the NVM0, NVM1, PHP, and VOP power domains. Wait for the GRF firewall
before restoring consumers and retry power-on failures without cycling
the domain again.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
drivers/pmdomain/rockchip/pm-domains.c | 141 ++++++++++++++++++++++++++++++---
1 file changed, 131 insertions(+), 10 deletions(-)
diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
index e193f978d5f3..86a6ffd43254 100644
--- a/drivers/pmdomain/rockchip/pm-domains.c
+++ b/drivers/pmdomain/rockchip/pm-domains.c
@@ -39,6 +39,7 @@
#include <dt-bindings/power/rockchip,rk3528-power.h>
#include <dt-bindings/power/rockchip,rk3562-power.h>
#include <dt-bindings/power/rk3568-power.h>
+#include <dt-bindings/power/rockchip,rk3572-power-controller.h>
#include <dt-bindings/power/rockchip,rk3576-power.h>
#include <dt-bindings/power/rk3588-power.h>
@@ -59,6 +60,9 @@ struct rockchip_domain_info {
u32 pwr_offset;
u32 mem_offset;
u32 req_offset;
+ u32 status_offset;
+ u32 firewall_mask;
+ u32 clk_ungate_offset;
};
struct rockchip_pmu_info {
@@ -72,6 +76,8 @@ struct rockchip_pmu_info {
u32 mem_status_offset;
u32 repair_status_offset;
u32 clk_ungate_offset;
+ u32 firewall_status_offset;
+ bool chain_status_inverted;
u32 core_pwrcnt_offset;
u32 gpu_pwrcnt_offset;
@@ -101,11 +107,13 @@ struct rockchip_pm_domain {
struct clk_bulk_data *clks;
struct device_node *node;
struct regulator *supply;
+ bool power_on_pending;
};
struct rockchip_pmu {
struct device *dev;
struct regmap *regmap;
+ struct regmap *grf;
const struct rockchip_pmu_info *info;
struct mutex mutex; /* mutex lock for pmu */
struct genpd_onecell_data genpd_data;
@@ -373,15 +381,16 @@ static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
const struct rockchip_domain_info *pd_info = pd->info;
unsigned int val;
- regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
+ regmap_read(pmu->regmap, pmu->info->idle_offset + pd_info->status_offset, &val);
return (val & pd_info->idle_mask) == pd_info->idle_mask;
}
-static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu)
+static unsigned int rockchip_pmu_read_ack(struct rockchip_pm_domain *pd)
{
+ struct rockchip_pmu *pmu = pd->pmu;
unsigned int val;
- regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
+ regmap_read(pmu->regmap, pmu->info->ack_offset + pd->info->status_offset, &val);
return val;
}
@@ -400,7 +409,8 @@ static int rockchip_pmu_ungate_clk(struct rockchip_pm_domain *pd, bool ungate)
val = ungate ? (pd_info->clk_ungate_mask | clk_ungate_w_mask) :
clk_ungate_w_mask;
- regmap_write(pmu->regmap, pmu->info->clk_ungate_offset, val);
+ regmap_write(pmu->regmap, pmu->info->clk_ungate_offset +
+ pd_info->clk_ungate_offset, val);
return 0;
}
@@ -431,7 +441,7 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
/* Wait util idle_ack = 1 */
target_ack = idle ? pd_info->ack_mask : 0;
- ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val,
+ ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pd, val,
(val & pd_info->ack_mask) == target_ack,
0, 10000);
if (ret) {
@@ -543,6 +553,9 @@ static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd)
regmap_read(pmu->regmap,
pmu->info->chain_status_offset + pd->info->mem_offset, &val);
+ if (pmu->info->chain_status_inverted)
+ return !(val & pd->info->mem_status_mask);
+
/* 1'b1: power on, 1'b0: power off */
return val & pd->info->mem_status_mask;
}
@@ -644,14 +657,29 @@ static int rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
return 0;
}
+static int rockchip_pmu_wait_firewall(struct rockchip_pm_domain *pd)
+{
+ struct rockchip_pmu *pmu = pd->pmu;
+ u32 mask = pd->info->firewall_mask;
+ u32 val;
+
+ if (!mask)
+ return 0;
+
+ return regmap_read_poll_timeout(pmu->grf, pmu->info->firewall_status_offset,
+ val, (val & mask) == mask, 0, 10000);
+}
+
static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
{
struct rockchip_pmu *pmu = pd->pmu;
+ bool is_on;
int ret;
guard(mutex)(&pmu->mutex);
- if (rockchip_pmu_domain_is_on(pd) == power_on)
+ is_on = rockchip_pmu_domain_is_on(pd);
+ if (is_on == power_on && !pd->power_on_pending)
return 0;
ret = clk_bulk_enable(pd->num_clks, pd->clks);
@@ -663,7 +691,8 @@ static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
rockchip_pmu_ungate_clk(pd, true);
if (!power_on) {
- rockchip_pmu_save_qos(pd);
+ if (!pd->power_on_pending)
+ rockchip_pmu_save_qos(pd);
/* if powering down, idle request to NIU first */
ret = rockchip_pmu_set_idle_request(pd, true);
@@ -671,18 +700,29 @@ static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
goto out;
}
- ret = rockchip_do_pmu_set_power_domain(pd, power_on);
- if (ret < 0)
- goto out;
+ /* A failed firewall wait must not restart powered memory on retry. */
+ if (is_on != power_on) {
+ ret = rockchip_do_pmu_set_power_domain(pd, power_on);
+ if (ret < 0)
+ goto out;
+ }
if (power_on) {
+ if (pd->info->firewall_mask)
+ pd->power_on_pending = true;
+
/* if powering up, leave idle mode */
ret = rockchip_pmu_set_idle_request(pd, false);
if (ret < 0)
goto out;
+ ret = rockchip_pmu_wait_firewall(pd);
+ if (ret)
+ goto out;
+
rockchip_pmu_restore_qos(pd);
}
+ pd->power_on_pending = false;
out:
rockchip_pmu_ungate_clk(pd, false);
@@ -1064,6 +1104,11 @@ static int rockchip_pm_domain_probe(struct platform_device *pdev)
mutex_init(&pmu->mutex);
pmu->info = pmu_info;
+ if (pmu_info->firewall_status_offset) {
+ pmu->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+ if (IS_ERR(pmu->grf))
+ return dev_err_probe(dev, PTR_ERR(pmu->grf), "failed to get system GRF\n");
+ }
pmu->genpd_data.domains = pmu->domains;
pmu->genpd_data.num_domains = pmu_info->num_domains;
@@ -1313,6 +1358,62 @@ static const struct rockchip_domain_info rk3568_pm_domains[] = {
[RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false, false),
};
+static const struct rockchip_domain_info rk3572_pm_domains[] = {
+ [RK3572_PD_NVM1] = {
+ .name = "nvm1",
+ .pwr_mask = BIT(4),
+ .pwr_w_mask = BIT(20),
+ .mem_status_mask = BIT(4),
+ .repair_status_mask = BIT(3),
+ .req_mask = BIT(6),
+ .req_w_mask = BIT(22),
+ .idle_mask = BIT(6),
+ .ack_mask = BIT(6),
+ .clk_ungate_mask = BIT(6),
+ },
+ [RK3572_PD_PHP] = {
+ .name = "php",
+ .pwr_mask = BIT(7),
+ .pwr_w_mask = BIT(23),
+ .mem_status_mask = BIT(7),
+ .repair_status_mask = BIT(5),
+ .req_mask = BIT(9),
+ .req_w_mask = BIT(25),
+ .idle_mask = BIT(9),
+ .ack_mask = BIT(9),
+ .clk_ungate_mask = BIT(9),
+ .firewall_mask = BIT(28),
+ },
+ [RK3572_PD_VOP] = {
+ .name = "vop",
+ .pwr_mask = BIT(12),
+ .pwr_w_mask = BIT(28),
+ .mem_status_mask = BIT(12),
+ .repair_status_mask = BIT(10),
+ .req_mask = BIT(14),
+ .req_w_mask = BIT(30),
+ .idle_mask = BIT(14),
+ .ack_mask = BIT(14),
+ .clk_ungate_mask = BIT(14),
+ .firewall_mask = BIT(23),
+ },
+ [RK3572_PD_NVM0] = {
+ .name = "nvm0",
+ .pwr_mask = BIT(15),
+ .pwr_w_mask = BIT(31),
+ .mem_status_mask = BIT(15),
+ .repair_status_mask = BIT(13),
+ .req_mask = BIT(0),
+ .req_w_mask = BIT(16),
+ .idle_mask = BIT(0),
+ .ack_mask = BIT(0),
+ .clk_ungate_mask = BIT(0),
+ .req_offset = 4,
+ .status_offset = 4,
+ .clk_ungate_offset = 4,
+ },
+};
+
static const struct rockchip_domain_info rk3576_pm_domains[] = {
[RK3576_PD_NPU] = DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, 0x0, 0, 0, 0, false),
[RK3576_PD_NVM] = DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(6), 0x4, BIT(2), BIT(18), BIT(2), false),
@@ -1536,6 +1637,23 @@ static const struct rockchip_pmu_info rk3568_pmu = {
.domain_info = rk3568_pm_domains,
};
+static const struct rockchip_pmu_info rk3572_pmu = {
+ .pwr_offset = 0x210,
+ .status_offset = 0x230,
+ .chain_status_offset = 0x250,
+ .chain_status_inverted = true,
+ .mem_status_offset = 0x260,
+ .mem_pwr_offset = 0x300,
+ .req_offset = 0x110,
+ .idle_offset = 0x130,
+ .ack_offset = 0x120,
+ .repair_status_offset = 0x570,
+ .clk_ungate_offset = 0x150,
+ .firewall_status_offset = 0x140,
+ .num_domains = ARRAY_SIZE(rk3572_pm_domains),
+ .domain_info = rk3572_pm_domains,
+};
+
static const struct rockchip_pmu_info rk3576_pmu = {
.pwr_offset = 0x210,
.status_offset = 0x230,
@@ -1648,6 +1766,9 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = {
.data = (void *)&rk3568_pmu,
},
{
+ .compatible = "rockchip,rk3572-power-controller",
+ .data = &rk3572_pmu,
+ }, {
.compatible = "rockchip,rk3576-power-controller",
.data = (void *)&rk3576_pmu,
},
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 11/27] dt-bindings: i2c: rk3x: Add RK3572
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (9 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 10/27] pmdomain: rockchip: Add RK3572 boot peripheral domains Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 12/27] dt-bindings: serial: snps-dw-apb-uart: " Cunhao Lu via B4 Relay
` (16 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Add the RK3572 I2C compatible using the RK3399 fallback.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
index 91805fe8f3936..bec2b9cfdd118 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
@@ -41,6 +41,7 @@ properties:
- rockchip,rk3528-i2c
- rockchip,rk3562-i2c
- rockchip,rk3568-i2c
+ - rockchip,rk3572-i2c
- rockchip,rk3576-i2c
- rockchip,rk3588-i2c
- rockchip,rv1126-i2c
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 12/27] dt-bindings: serial: snps-dw-apb-uart: Add RK3572
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (10 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 11/27] dt-bindings: i2c: rk3x: Add RK3572 Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 13/27] dt-bindings: mmc: rockchip: Add RK3572 controllers Cunhao Lu via B4 Relay
` (15 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Add the RK3572 UART compatible using the Synopsys fallback.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
index 664305de4986..4567f8e76c9f 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
@@ -70,6 +70,7 @@ properties:
- rockchip,rk3528-uart
- rockchip,rk3562-uart
- rockchip,rk3568-uart
+ - rockchip,rk3572-uart
- rockchip,rk3576-uart
- rockchip,rk3588-uart
- rockchip,rv1103b-uart
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 13/27] dt-bindings: mmc: rockchip: Add RK3572 controllers
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (11 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 12/27] dt-bindings: serial: snps-dw-apb-uart: " Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 14/27] dt-bindings: net: rockchip-dwmac: Add RK3572 Cunhao Lu via B4 Relay
` (14 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Add the RK3572 SD and eMMC compatibles using the RK3576 fallbacks.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml | 1 +
Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml | 3 +++
2 files changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
index 21ecfaa454f45..08db29af3e969 100644
--- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
+++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
@@ -50,6 +50,7 @@ properties:
# for Rockchip RK3576 with phase tuning inside the controller
- items:
- enum:
+ - rockchip,rk3572-dw-mshc
- rockchip,rv1103b-dw-mshc
- const: rockchip,rk3576-dw-mshc
- const: rockchip,rk3576-dw-mshc
diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
index cd823a3ef2130..a4e04fedfd33d 100644
--- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
@@ -13,6 +13,9 @@ maintainers:
properties:
compatible:
oneOf:
+ - items:
+ - const: rockchip,rk3572-dwcmshc
+ - const: rockchip,rk3576-dwcmshc
- items:
- enum:
- rockchip,rk3528-dwcmshc
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 14/27] dt-bindings: net: rockchip-dwmac: Add RK3572
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (12 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 13/27] dt-bindings: mmc: rockchip: Add RK3572 controllers Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 17:14 ` Andrew Lunn
2026-10-21 16:11 ` [PATCH 15/27] dt-bindings: thermal: rockchip: " Cunhao Lu via B4 Relay
` (13 subsequent siblings)
27 siblings, 1 reply; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Add the RK3572 GMAC compatible using the snps,dwmac-4.20a fallback.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
Documentation/devicetree/bindings/net/rockchip-dwmac.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
index 80c252845349c..83b0a81b4f3b7 100644
--- a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
@@ -27,6 +27,7 @@ select:
- rockchip,rk3506-gmac
- rockchip,rk3528-gmac
- rockchip,rk3568-gmac
+ - rockchip,rk3572-gmac
- rockchip,rk3576-gmac
- rockchip,rk3588-gmac
- rockchip,rv1108-gmac
@@ -54,6 +55,7 @@ properties:
- rockchip,rk3506-gmac
- rockchip,rk3528-gmac
- rockchip,rk3568-gmac
+ - rockchip,rk3572-gmac
- rockchip,rk3576-gmac
- rockchip,rk3588-gmac
- rockchip,rv1126-gmac
@@ -137,6 +139,7 @@ allOf:
compatible:
contains:
enum:
+ - rockchip,rk3572-gmac
- rockchip,rk3576-gmac
- rockchip,rk3588-gmac
then:
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 15/27] dt-bindings: thermal: rockchip: Add RK3572
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (13 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 14/27] dt-bindings: net: rockchip-dwmac: Add RK3572 Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 16/27] net: stmmac: dwmac-rk: Add RK3572 support Cunhao Lu via B4 Relay
` (12 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Add the RK3572 thermal sensor compatible.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml
index 9fa5c4c49d76e..7102a581ef72b 100644
--- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml
+++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml
@@ -21,6 +21,7 @@ properties:
- rockchip,rk3368-tsadc
- rockchip,rk3399-tsadc
- rockchip,rk3568-tsadc
+ - rockchip,rk3572-tsadc
- rockchip,rk3576-tsadc
- rockchip,rk3588-tsadc
- rockchip,rv1108-tsadc
@@ -151,6 +152,7 @@ allOf:
contains:
enum:
- rockchip,rk3568-tsadc
+ - rockchip,rk3572-tsadc
- rockchip,rk3576-tsadc
then:
patternProperties:
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 16/27] net: stmmac: dwmac-rk: Add RK3572 support
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (14 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 15/27] dt-bindings: thermal: rockchip: " Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 17:09 ` Andrew Lunn
2026-10-21 16:11 ` [PATCH 17/27] thermal: rockchip: " Cunhao Lu via B4 Relay
` (11 subsequent siblings)
27 siblings, 1 reply; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Configure RGMII delays and clocks for both RK3572 GMAC controllers,
using GMAC-specific GRF registers.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 53 ++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 72bdbcb5e863..1a22233179ab 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -872,6 +872,58 @@ static const struct rk_gmac_ops rk3568_ops = {
},
};
+#define RK3572_VCCIO0_3_VO_IOC_CON1 0x10608
+#define RK3572_VCCIO1_2_4_VI_IOC_CON1 0x12604
+#define RK3572_VCCIO5_6_IOC_MISC0 0x14630
+#define RK3572_PHP_GRF_GMAC0_CON 0x0070
+#define RK3572_NVM0_GRF_GMAC1_CON 0x0020
+
+static int rk3572_init(struct rk_priv_data *bsp_priv)
+{
+ switch (bsp_priv->id) {
+ case 0:
+ bsp_priv->gmac_grf_reg = RK3572_PHP_GRF_GMAC0_CON;
+ break;
+ case 1:
+ bsp_priv->gmac_grf_reg = RK3572_NVM0_GRF_GMAC1_CON;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ bsp_priv->clock_grf_reg = bsp_priv->gmac_grf_reg;
+ return 0;
+}
+
+static void rk3572_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+{
+ u32 val = GRF_FIELD(14, 8, rx_delay) | GRF_FIELD(6, 0, tx_delay) |
+ GRF_FIELD(15, 15, !!rx_delay) | GRF_FIELD(7, 7, !!tx_delay);
+
+ if (bsp_priv->id == 1) {
+ regmap_write(bsp_priv->php_grf, RK3572_VCCIO0_3_VO_IOC_CON1, val);
+ regmap_write(bsp_priv->php_grf, RK3572_VCCIO5_6_IOC_MISC0, val);
+ } else {
+ regmap_write(bsp_priv->php_grf, RK3572_VCCIO1_2_4_VI_IOC_CON1, val);
+ }
+}
+
+static const struct rk_gmac_ops rk3572_ops = {
+ .init = rk3572_init,
+ .set_to_rgmii = rk3572_set_to_rgmii,
+ .gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
+ .gmac_rmii_mode_mask = BIT_U16(3),
+ .clock.io_clksel_io_mask = BIT_U16(7),
+ .clock.gmii_clk_sel_mask = GENMASK_U16(6, 5),
+ .clock.rmii_clk_sel_mask = BIT_U16(5),
+ .clock.rmii_gate_en_mask = BIT_U16(4),
+ .supports_rmii = true,
+ .php_grf_required = true,
+ .regs_valid = true,
+ .regs = { 0x29d20000, 0x2a040000, 0 },
+};
+
/* VCCIO0_1_3_IOC */
#define RK3576_VCCIO0_1_3_IOC_CON2 0X6408
#define RK3576_VCCIO0_1_3_IOC_CON3 0X640c
@@ -1629,6 +1681,7 @@ static const struct of_device_id rk_gmac_dwmac_match[] = {
{ .compatible = "rockchip,rk3506-gmac", .data = &rk3506_ops },
{ .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },
{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
+ { .compatible = "rockchip,rk3572-gmac", .data = &rk3572_ops },
{ .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops },
{ .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
{ .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 17/27] thermal: rockchip: Add RK3572 support
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (15 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 16/27] net: stmmac: dwmac-rk: Add RK3572 support Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 18/27] dt-bindings: phy: rockchip-inno-usb2: Add RK3572 Cunhao Lu via B4 Relay
` (10 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Support all five RK3572 thermal sensor channels.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
drivers/thermal/rockchip_thermal.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c
index 08891608baa6..745aad53beba 100644
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -1303,6 +1303,31 @@ static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
},
};
+static const struct rockchip_tsadc_chip rk3572_tsadc_data = {
+ /* center, gpu_npu, ddr, little_core, big_core */
+ .chn_offset = 0,
+ .chn_num = 5,
+ .grf_required = false,
+ .tshut_mode = TSHUT_MODE_GPIO,
+ .tshut_polarity = TSHUT_LOW_ACTIVE,
+ .tshut_temp = 95000,
+ .initialize = rk_tsadcv8_initialize,
+ .irq_ack = rk_tsadcv4_irq_ack,
+ .control = rk_tsadcv4_control,
+ .get_temp = rk_tsadcv4_get_temp,
+ .set_alarm_temp = rk_tsadcv3_alarm_temp,
+ .set_tshut_temp = rk_tsadcv3_tshut_temp,
+ .set_tshut_mode = rk_tsadcv4_tshut_mode,
+ .get_trim_code = rk_tsadcv2_get_trim_code,
+ .trim_slope = 923,
+ .table = {
+ .id = rk3588_code_table,
+ .length = ARRAY_SIZE(rk3588_code_table),
+ .data_mask = TSADCV4_DATA_MASK,
+ .mode = ADC_INCREMENT,
+ },
+};
+
static const struct rockchip_tsadc_chip rk3576_tsadc_data = {
/* top, big_core, little_core, ddr, npu, gpu */
.chn_offset = 0,
@@ -1388,6 +1413,9 @@ static const struct of_device_id of_rockchip_thermal_match[] = {
.data = (void *)&rk3568_tsadc_data,
},
{
+ .compatible = "rockchip,rk3572-tsadc",
+ .data = &rk3572_tsadc_data,
+ }, {
.compatible = "rockchip,rk3576-tsadc",
.data = (void *)&rk3576_tsadc_data,
},
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 18/27] dt-bindings: phy: rockchip-inno-usb2: Add RK3572
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (16 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 17/27] thermal: rockchip: " Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 19/27] dt-bindings: phy: rockchip-naneng-combphy: " Cunhao Lu via B4 Relay
` (9 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Add the RK3572 USB2 PHY compatible.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
.../devicetree/bindings/phy/rockchip,inno-usb2phy.yaml | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
index f50fc69fbbe49..9bb9295c332c3 100644
--- a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
+++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
@@ -23,6 +23,7 @@ properties:
- rockchip,rk3528-usb2phy
- rockchip,rk3562-usb2phy
- rockchip,rk3568-usb2phy
+ - rockchip,rk3572-usb2phy
- rockchip,rk3576-usb2phy
- rockchip,rk3588-usb2phy
- rockchip,rv1108-usb2phy
@@ -253,6 +254,19 @@ allOf:
clock-names:
minItems: 3
+ - if:
+ properties:
+ compatible:
+ const: rockchip,rk3572-usb2phy
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ minItems: 2
+ maxItems: 2
+
additionalProperties: false
examples:
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 19/27] dt-bindings: phy: rockchip-naneng-combphy: Add RK3572
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (17 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 18/27] dt-bindings: phy: rockchip-inno-usb2: Add RK3572 Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 20/27] dt-bindings: usb: rockchip: Add RK3572 DWC3 controller Cunhao Lu via B4 Relay
` (8 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
The RK3572 combo PHY uses two input clocks and one reset.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
.../bindings/phy/phy-rockchip-naneng-combphy.yaml | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
index 379b08bd9e97a..80cee3f8874d9 100644
--- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
@@ -15,6 +15,7 @@ properties:
- rockchip,rk3528-naneng-combphy
- rockchip,rk3562-naneng-combphy
- rockchip,rk3568-naneng-combphy
+ - rockchip,rk3572-naneng-combphy
- rockchip,rk3576-naneng-combphy
- rockchip,rk3588-naneng-combphy
@@ -22,12 +23,14 @@ properties:
maxItems: 1
clocks:
+ minItems: 2
items:
- description: reference clock
- description: apb clock
- description: pipe clock
clock-names:
+ minItems: 2
items:
- const: ref
- const: apb
@@ -94,6 +97,26 @@ required:
- "#phy-cells"
allOf:
+ - if:
+ properties:
+ compatible:
+ const: rockchip,rk3572-naneng-combphy
+ then:
+ properties:
+ clocks:
+ maxItems: 2
+ clock-names:
+ maxItems: 2
+ resets:
+ maxItems: 1
+ reset-names:
+ maxItems: 1
+ else:
+ properties:
+ clocks:
+ minItems: 3
+ clock-names:
+ minItems: 3
- if:
properties:
compatible:
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 20/27] dt-bindings: usb: rockchip: Add RK3572 DWC3 controller
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (18 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 19/27] dt-bindings: phy: rockchip-naneng-combphy: " Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 21/27] phy: rockchip-inno-usb2: Add RK3572 support Cunhao Lu via B4 Relay
` (7 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Describe the PHP GRF register used to configure the DWC3 PIPE port before
controller discovery.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
.../bindings/usb/rockchip,rk3572-dwc3.yaml | 100 +++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/rockchip,rk3572-dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,rk3572-dwc3.yaml
new file mode 100644
index 000000000000..47ff5e16dce6
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/rockchip,rk3572-dwc3.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/rockchip,rk3572-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3572 DWC3 USB controller
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+ - Cunhao Lu <1579567540@qq.com>
+
+allOf:
+ - $ref: snps,dwc3-common.yaml#
+
+properties:
+ compatible:
+ const: rockchip,rk3572-dwc3
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ dma-coherent: true
+
+ clocks:
+ minItems: 3
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: ref_clk
+ - const: suspend_clk
+ - const: bus_clk
+
+ phys:
+ minItems: 1
+ items:
+ - description: USB2 PHY
+ - description: USB3 PHY
+
+ phy-names:
+ minItems: 1
+ items:
+ - const: usb2-phy
+ - const: usb3-phy
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ PHP GRF and the controller's PIPE configuration register offset.
+ items:
+ - items:
+ - description: PHP GRF phandle
+ - enum: [0x14, 0x34]
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - phys
+ - phy-names
+ - power-domains
+ - resets
+ - rockchip,grf
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rockchip,rk3572-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/power/rockchip,rk3572-power-controller.h>
+ #include <dt-bindings/reset/rockchip,rk3572-cru.h>
+
+ usb@24400000 {
+ compatible = "rockchip,rk3572-dwc3";
+ reg = <0x24400000 0x400000>;
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_REF_USB3OTG1>, <&cru CLK_SUSPEND_USB3OTG1>,
+ <&cru ACLK_USB3OTG1>;
+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
+ phys = <&u2phy1_otg>, <&combphy1 PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ power-domains = <&power RK3572_PD_PHP>;
+ resets = <&cru SRST_ARESETN_USB3OTG1>;
+ rockchip,grf = <&php_grf 0x34>;
+ dr_mode = "host";
+ };
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 21/27] phy: rockchip-inno-usb2: Add RK3572 support
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (19 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 20/27] dt-bindings: usb: rockchip: Add RK3572 DWC3 controller Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 22/27] phy: rockchip-naneng-combphy: " Cunhao Lu via B4 Relay
` (6 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Support both RK3572 USB2 PHY instances.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 136 ++++++++++++++++++++++++++
1 file changed, 136 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 7d8a533f24aea..16a36e68cb6d3 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -1544,6 +1544,49 @@ static int rk3528_usb2phy_tuning(struct rockchip_usb2phy *rphy)
return 0;
}
+static int rk3572_usb2phy_tuning(struct rockchip_usb2phy *rphy)
+{
+ u32 reg = rphy->phy_cfg->reg;
+ struct clk *refclk;
+ unsigned long rate;
+ u32 val;
+ int ret;
+
+ refclk = devm_clk_get(rphy->dev, "phyclk");
+ if (IS_ERR(refclk))
+ return PTR_ERR(refclk);
+ rate = clk_get_rate(refclk);
+ if (rate != 24000000 && rate != 26000000)
+ return -EINVAL;
+
+ ret = regmap_write(rphy->grf, reg + 0x0004,
+ GENMASK(18, 16) | (rate == 24000000 ? 2 : 6));
+ if (ret)
+ return ret;
+
+ ret = regmap_read(rphy->grf, reg + 0x0010, &val);
+ if (ret)
+ return ret;
+ if (val & BIT(13)) {
+ ret = regmap_write(rphy->grf, reg + 0x0010, BIT(29));
+ if (ret)
+ return ret;
+ ret = rockchip_usb2phy_reset(rphy);
+ if (ret)
+ return ret;
+ }
+
+ /* Set the normal line-state filter interval. */
+ ret = regmap_write(rphy->grf, reg + 0x0020, 0x30100);
+ if (ret)
+ return ret;
+ /* Increase HS voltage by 5.89% and double pre-emphasis current. */
+ ret = regmap_write(rphy->grf, reg + 0x000c, GENMASK(27, 24) | 0x0900);
+ if (ret)
+ return ret;
+ return regmap_write(rphy->grf, reg + 0x0010, GENMASK(20, 19) | 0x0010);
+}
+
static int rk3576_usb2phy_tuning(struct rockchip_usb2phy *rphy)
{
int ret;
@@ -2126,6 +2169,98 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
{ /* sentinel */ }
};
+static const struct rockchip_usb2phy_cfg rk3572_phy_cfgs[] = {
+ {
+ .reg = 0x0,
+ .num_ports = 1,
+ .phy_tuning = rk3572_usb2phy_tuning,
+ .clkout_ctl = { 0x0008, 0, 0, 1, 0 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 },
+ .bvalid_det_en = { 0x00c0, 1, 1, 0, 1 },
+ .bvalid_det_st = { 0x00c4, 1, 1, 0, 1 },
+ .bvalid_det_clr = { 0x00c8, 1, 1, 0, 1 },
+ .idfall_det_en = { 0x00c0, 4, 4, 0, 1 },
+ .idfall_det_st = { 0x00c4, 4, 4, 0, 1 },
+ .idfall_det_clr = { 0x00c8, 4, 4, 0, 1 },
+ .idrise_det_en = { 0x00c0, 3, 3, 0, 1 },
+ .idrise_det_st = { 0x00c4, 3, 3, 0, 1 },
+ .idrise_det_clr = { 0x00c8, 3, 3, 0, 1 },
+ .ls_det_en = { 0x00c0, 0, 0, 0, 1 },
+ .ls_det_st = { 0x00c4, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x00c8, 0, 0, 0, 1 },
+ .disfall_en = { 0x00c0, 6, 6, 0, 1 },
+ .disfall_st = { 0x00c4, 6, 6, 0, 1 },
+ .disfall_clr = { 0x00c8, 6, 6, 0, 1 },
+ .disrise_en = { 0x00c0, 5, 5, 0, 1 },
+ .disrise_st = { 0x00c4, 5, 5, 0, 1 },
+ .disrise_clr = { 0x00c8, 5, 5, 0, 1 },
+ .utmi_avalid = { 0x0080, 1, 1, 0, 1 },
+ .utmi_bvalid = { 0x0080, 0, 0, 0, 1 },
+ .utmi_id = { 0x0080, 6, 6, 0, 1 },
+ .utmi_ls = { 0x0080, 5, 4, 0, 1 },
+ }
+ },
+ .chg_det = {
+ .cp_det = { 0x0080, 8, 8, 0, 1 },
+ .dcp_det = { 0x0080, 8, 8, 0, 1 },
+ .dp_det = { 0x0080, 9, 9, 1, 0 },
+ .idm_sink_en = { 0x0010, 5, 5, 1, 0 },
+ .idp_sink_en = { 0x0010, 5, 5, 0, 1 },
+ .idp_src_en = { 0x0010, 14, 14, 0, 1 },
+ .rdm_pdwn_en = { 0x0010, 14, 14, 0, 1 },
+ .vdm_src_en = { 0x0010, 7, 6, 0, 3 },
+ .vdp_src_en = { 0x0010, 7, 6, 0, 3 },
+ },
+ },
+ {
+ .reg = 0x2000,
+ .num_ports = 1,
+ .phy_tuning = rk3572_usb2phy_tuning,
+ .clkout_ctl = { 0x2008, 0, 0, 1, 0 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x2000, 8, 0, 0, 0x1d1 },
+ .bvalid_det_en = { 0x20c0, 1, 1, 0, 1 },
+ .bvalid_det_st = { 0x20c4, 1, 1, 0, 1 },
+ .bvalid_det_clr = { 0x20c8, 1, 1, 0, 1 },
+ .idfall_det_en = { 0x20c0, 4, 4, 0, 1 },
+ .idfall_det_st = { 0x20c4, 4, 4, 0, 1 },
+ .idfall_det_clr = { 0x20c8, 4, 4, 0, 1 },
+ .idrise_det_en = { 0x20c0, 3, 3, 0, 1 },
+ .idrise_det_st = { 0x20c4, 3, 3, 0, 1 },
+ .idrise_det_clr = { 0x20c8, 3, 3, 0, 1 },
+ .ls_det_en = { 0x20c0, 0, 0, 0, 1 },
+ .ls_det_st = { 0x20c4, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x20c8, 0, 0, 0, 1 },
+ .disfall_en = { 0x20c0, 6, 6, 0, 1 },
+ .disfall_st = { 0x20c4, 6, 6, 0, 1 },
+ .disfall_clr = { 0x20c8, 6, 6, 0, 1 },
+ .disrise_en = { 0x20c0, 5, 5, 0, 1 },
+ .disrise_st = { 0x20c4, 5, 5, 0, 1 },
+ .disrise_clr = { 0x20c8, 5, 5, 0, 1 },
+ .utmi_avalid = { 0x2080, 1, 1, 0, 1 },
+ .utmi_bvalid = { 0x2080, 0, 0, 0, 1 },
+ .utmi_id = { 0x2080, 6, 6, 0, 1 },
+ .utmi_ls = { 0x2080, 5, 4, 0, 1 },
+ }
+ },
+ .chg_det = {
+ .cp_det = { 0x2080, 8, 8, 0, 1 },
+ .dcp_det = { 0x2080, 8, 8, 0, 1 },
+ .dp_det = { 0x2080, 9, 9, 1, 0 },
+ .idm_sink_en = { 0x2010, 5, 5, 1, 0 },
+ .idp_sink_en = { 0x2010, 5, 5, 0, 1 },
+ .idp_src_en = { 0x2010, 14, 14, 0, 1 },
+ .rdm_pdwn_en = { 0x2010, 14, 14, 0, 1 },
+ .vdm_src_en = { 0x2010, 7, 6, 0, 3 },
+ .vdp_src_en = { 0x2010, 7, 6, 0, 3 },
+ },
+ },
+ { /* sentinel */ }
+};
+
static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = {
{
.reg = 0x0,
@@ -2378,6 +2513,7 @@ static const struct of_device_id rockchip_usb2phy_dt_match[] = {
{ .compatible = "rockchip,rk3528-usb2phy", .data = &rk3528_phy_cfgs },
{ .compatible = "rockchip,rk3562-usb2phy", .data = &rk3562_phy_cfgs },
{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
+ { .compatible = "rockchip,rk3572-usb2phy", .data = &rk3572_phy_cfgs },
{ .compatible = "rockchip,rk3576-usb2phy", .data = &rk3576_phy_cfgs },
{ .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs },
{ .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 22/27] phy: rockchip-naneng-combphy: Add RK3572 support
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (20 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 21/27] phy: rockchip-inno-usb2: Add RK3572 support Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 23/27] usb: dwc3: Configure RK3572 PIPE port before discovery Cunhao Lu via B4 Relay
` (5 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Support PCIe, USB3, and SATA operation on the RK3572 combo PHY.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 201 +++++++++++++++++++++
1 file changed, 201 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index 7843356a4dd4..e13a78ab5777 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -1000,6 +1000,204 @@ static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
.combphy_cfg = rk3568_combphy_cfg,
};
+static int rk3572_combphy_cfg(struct rockchip_combphy_priv *priv)
+{
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+ unsigned long rate;
+
+ switch (priv->type) {
+ case PHY_TYPE_PCIE:
+ /* Set SSC downward spread spectrum */
+ rockchip_combphy_updatel(priv, GENMASK(5, 4), BIT(4), 0x7c);
+
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
+ break;
+ case PHY_TYPE_USB3:
+ /* Set SSC downward spread spectrum */
+ rockchip_combphy_updatel(priv, GENMASK(5, 4), BIT(4), 0x7c);
+
+ /* Enable adaptive CTLE for USB3.0 Rx */
+ rockchip_combphy_updatel(priv, GENMASK(0, 0), BIT(0), 0x38);
+
+ /* Set PLL KVCO fine tuning signals */
+ rockchip_combphy_updatel(priv, GENMASK(4, 2), BIT(3), 0x80);
+
+ /* Set PLL LPF R1 to su_trim[10:7]=1001 */
+ writel(0x4, priv->mmio + (0xb << 2));
+
+ /* Set PLL input clock divider 1/2 */
+ rockchip_combphy_updatel(priv, GENMASK(7, 6), BIT(6), 0x14);
+
+ writel(0x32, priv->mmio + (0x11 << 2));
+
+ /* Set PLL KVCO to min and set PLL charge pump current to max */
+ writel(0xf0, priv->mmio + (0xa << 2));
+
+ /* Set Rx squelch input filter bandwidth */
+ writel(0x0d, priv->mmio + (0x14 << 2));
+
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
+ break;
+ case PHY_TYPE_SATA:
+ /* Enable adaptive CTLE for SATA Rx */
+ rockchip_combphy_updatel(priv, GENMASK(0, 0), BIT(0), 0x38);
+
+ /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */
+ writel(0x8f, priv->mmio + (0x06 << 2));
+
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
+ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
+ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
+ break;
+ default:
+ dev_err(priv->dev, "incompatible PHY type\n");
+ return -EINVAL;
+ }
+
+ rate = clk_get_rate(priv->refclk);
+
+ switch (rate) {
+ case 24000000:
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
+ if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
+ /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
+ rockchip_combphy_updatel(priv, GENMASK(7, 6), BIT(6), 0xe << 2);
+
+ rockchip_combphy_updatel(priv, GENMASK(7, 0), 0x5f, 0xf << 2);
+ } else if (priv->type == PHY_TYPE_PCIE) {
+ /* PLL KVCO tuning fine */
+ rockchip_combphy_updatel(priv, GENMASK(4, 2), 0x4 << 2, 0x20 << 2);
+
+ writel(0x0, priv->mmio + (0x1b << 2));
+
+ /* Set up su_trim: T0_1 */
+ writel(0x90, priv->mmio + (0xa << 2));
+ writel(0x02, priv->mmio + (0xb << 2));
+ writel(0x57, priv->mmio + (0xd << 2));
+
+ writel(0x5f, priv->mmio + (0xf << 2));
+ }
+ break;
+ case 25000000:
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
+ break;
+ case 100000000:
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+ if (priv->type == PHY_TYPE_PCIE) {
+ /* gate_tx_pck_sel length select work for L1SS */
+ writel(0xc0, priv->mmio + 0x74);
+
+ /* PLL KVCO tuning fine */
+ rockchip_combphy_updatel(priv, GENMASK(4, 2), 0x4 << 2, 0x20 << 2);
+
+ /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
+ writel(0x4c, priv->mmio + (0x1b << 2));
+
+ /* Set up su_trim: T3_P1 650mv */
+ writel(0x90, priv->mmio + (0xa << 2));
+ writel(0x43, priv->mmio + (0xb << 2));
+ writel(0x88, priv->mmio + (0xc << 2));
+ writel(0x56, priv->mmio + (0xd << 2));
+ } else if (priv->type == PHY_TYPE_SATA) {
+ /* downward spread spectrum +500ppm */
+ rockchip_combphy_updatel(priv, GENMASK(7, 4), 0x50, 0x1f << 2);
+
+ /* ssc ppm adjust to 3500ppm */
+ rockchip_combphy_updatel(priv, GENMASK(3, 0), 0x7, 0x9 << 2);
+ }
+ break;
+ default:
+ dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
+ return -EINVAL;
+ }
+
+ if (priv->ext_refclk) {
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
+ if (priv->type == PHY_TYPE_PCIE && rate == 100000000) {
+ writel(0x10, priv->mmio + (0x20 << 2));
+
+ writel(0x0c, priv->mmio + (0x1b << 2));
+
+ /*
+ * Set up su_trim: T3_P1 650mv
+ * CKRCV termination resistor adjust 11: Hi-Z
+ */
+ writel(0x90, priv->mmio + (0xa << 2));
+ writel(0x43, priv->mmio + (0xb << 2));
+ writel(0xb8, priv->mmio + (0xc << 2));
+ writel(0x56, priv->mmio + (0xd << 2));
+ }
+ }
+
+ if (priv->enable_ssc) {
+ rockchip_combphy_updatel(priv, GENMASK(4, 4), BIT(4), 0x7 << 2);
+ /* PLL control SSC module period should be set */
+ rockchip_combphy_updatel(priv, GENMASK(5, 5), BIT(5), 0x20 << 2);
+
+ if (priv->type == PHY_TYPE_PCIE && rate == 24000000) {
+ /* xin24m T0_1 650mV */
+ writel(0x00, priv->mmio + (0x10 << 2));
+ writel(0x32, priv->mmio + (0x11 << 2));
+ writel(0x00, priv->mmio + (0x1b << 2));
+ writel(0x90, priv->mmio + (0x0a << 2));
+ writel(0x02, priv->mmio + (0x0b << 2));
+ writel(0x08, priv->mmio + (0x0c << 2));
+ writel(0x57, priv->mmio + (0x0d << 2));
+ writel(0x40, priv->mmio + (0x0e << 2));
+ writel(0x5f, priv->mmio + (0x0f << 2));
+ writel(0x10, priv->mmio + (0x20 << 2));
+ /* ssc_cnt: 0101111101 & 31.5KHz */
+ rockchip_combphy_updatel(priv, GENMASK(7, 6), BIT(6), 0xe << 2);
+ rockchip_combphy_updatel(priv, GENMASK(7, 0), 0x5f, 0xf << 2);
+ } else if (priv->type == PHY_TYPE_PCIE && rate == 100000000) {
+ /* ssc_cnt: 1000110001 & 31.5KHz */
+ rockchip_combphy_updatel(priv, GENMASK(7, 6), BIT(6), 0xe << 2);
+ rockchip_combphy_updatel(priv, GENMASK(7, 0), 0x8c, 0xf << 2);
+ }
+ }
+
+ if (priv->type == PHY_TYPE_PCIE)
+ rockchip_combphy_updatel(priv, BIT(5), BIT(5), 0x64);
+
+ return 0;
+}
+
+static const struct rockchip_combphy_grfcfg rk3572_combphy_grfcfgs = {
+ /* pipe-phy-grf */
+ .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
+ .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 },
+ .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
+ .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
+ .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
+ .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
+ .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
+ .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
+ .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
+ .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
+ .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
+ .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
+ .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
+ .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
+ .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
+ .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
+ /* php-grf */
+ .pipe_con0_for_sata = { 0x0058, 2, 0, 0x00, 0x2 },
+ .pipe_con1_for_sata = { 0x005c, 2, 0, 0x00, 0x2 },
+};
+
+static const struct rockchip_combphy_cfg rk3572_combphy_cfgs = {
+ .grfcfg = &rk3572_combphy_grfcfgs,
+ .combphy_cfg = rk3572_combphy_cfg,
+};
+
static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
{
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
@@ -1407,6 +1605,9 @@ static const struct of_device_id rockchip_combphy_of_match[] = {
.data = &rk3568_combphy_cfgs,
},
{
+ .compatible = "rockchip,rk3572-naneng-combphy",
+ .data = &rk3572_combphy_cfgs,
+ }, {
.compatible = "rockchip,rk3576-naneng-combphy",
.data = &rk3576_combphy_cfgs,
},
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 23/27] usb: dwc3: Configure RK3572 PIPE port before discovery
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (21 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 22/27] phy: rockchip-naneng-combphy: " Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 24/27] mmc: dw_mmc-rockchip: Keep RK3572 NVM domain powered Cunhao Lu via B4 Relay
` (4 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Firmware may leave the USB3 PIPE port disabled, causing DWC3 to discover
only USB2. Configure the port before reading controller capabilities.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
drivers/usb/dwc3/dwc3-generic-plat.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
index ca69ac0eb07ce..11e71fc76be1a 100644
--- a/drivers/usb/dwc3/dwc3-generic-plat.c
+++ b/drivers/usb/dwc3/dwc3-generic-plat.c
@@ -22,6 +22,10 @@
#define EIC7700_HSP_AXI_LP_XM_CSYSREQ BIT(0)
#define EIC7700_HSP_AXI_LP_XS_CSYSREQ BIT(16)
+#define RK3572_PIPE_USB3 0x1100
+#define RK3572_PIPE_USB2_ONLY 0x0189
+#define RK3572_PIPE_WRITE_MASK GENMASK(31, 16)
+
struct dwc3_generic {
struct device *dev;
struct dwc3 dwc;
@@ -85,6 +89,27 @@ static int dwc3_spacemit_k1_init(struct dwc3_generic *dwc3g)
return 0;
}
+static int dwc3_rk3572_init(struct dwc3_generic *dwc3g)
+{
+ struct device *dev = dwc3g->dev;
+ enum usb_device_speed speed = usb_get_maximum_speed(dev);
+ struct regmap *grf;
+ u32 offset, value = RK3572_PIPE_USB2_ONLY;
+
+ grf = syscon_regmap_lookup_by_phandle_args(dev->of_node, "rockchip,grf",
+ 1, &offset);
+ if (IS_ERR(grf))
+ return dev_err_probe(dev, PTR_ERR(grf), "failed to get PHP GRF\n");
+
+ if (device_property_match_string(dev, "phy-names", "usb3-phy") >= 0 &&
+ speed != USB_SPEED_LOW && speed != USB_SPEED_FULL &&
+ speed != USB_SPEED_HIGH)
+ value = RK3572_PIPE_USB3;
+
+ /* Configure the PIPE port before the core reads its port count. */
+ return regmap_write(grf, offset, RK3572_PIPE_WRITE_MASK | value);
+}
+
static int dwc3_generic_probe(struct platform_device *pdev)
{
const struct dwc3_generic_config *plat_config;
@@ -231,11 +256,17 @@ static const struct dwc3_generic_config eic7700_dwc3 = {
.properties = DWC3_DEFAULT_PROPERTIES,
};
+static const struct dwc3_generic_config rk3572_dwc3 = {
+ .init = dwc3_rk3572_init,
+ .properties = DWC3_DEFAULT_PROPERTIES,
+};
+
static const struct of_device_id dwc3_generic_of_match[] = {
{ .compatible = "spacemit,k1-dwc3", &spacemit_k1_dwc3},
{ .compatible = "spacemit,k3-dwc3", },
{ .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3},
{ .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3},
+ { .compatible = "rockchip,rk3572-dwc3", &rk3572_dwc3 },
{ .compatible = "starfive,jhb100-dwc3", },
{ /* sentinel */ }
};
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 24/27] mmc: dw_mmc-rockchip: Keep RK3572 NVM domain powered
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (22 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 23/27] usb: dwc3: Configure RK3572 PIPE port before discovery Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 25/27] dt-bindings: arm: rockchip: Add Forlinx OK3572-C Cunhao Lu via B4 Relay
` (3 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Power cycling the RK3572 NVM domain causes repeated SD recovery. Keep it
powered during runtime suspend without disabling controller runtime PM.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
drivers/mmc/host/dw_mmc-rockchip.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
index 75c82ff20f177..8bc55d4b996c6 100644
--- a/drivers/mmc/host/dw_mmc-rockchip.c
+++ b/drivers/mmc/host/dw_mmc-rockchip.c
@@ -10,6 +10,7 @@
#include <linux/mmc/host.h>
#include <linux/of_address.h>
#include <linux/mmc/slot-gpio.h>
+#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
@@ -528,6 +529,19 @@ static int dw_mci_rockchip_init(struct dw_mci *host)
return 0;
}
+static int dw_mci_rk3572_init(struct dw_mci *host)
+{
+ int ret;
+
+ /* Power cycling the NVM domain disrupts SDMMC recovery. */
+ ret = dev_pm_genpd_rpm_always_on(host->dev, true);
+ if (ret && ret != -EOPNOTSUPP)
+ dev_warn(host->dev, "failed to keep power domain on: %pe\n",
+ ERR_PTR(ret));
+
+ return dw_mci_rockchip_init(host);
+}
+
static const struct dw_mci_drv_data rk2928_drv_data = {
.init = dw_mci_rockchip_init,
.parse_dt = dw_mci_rk2928_parse_dt,
@@ -541,6 +555,14 @@ static const struct dw_mci_drv_data rk3288_drv_data = {
.init = dw_mci_rockchip_init,
};
+static const struct dw_mci_drv_data rk3572_drv_data = {
+ .common_caps = MMC_CAP_CMD23,
+ .set_ios = dw_mci_rk3288_set_ios,
+ .execute_tuning = dw_mci_rk3288_execute_tuning,
+ .parse_dt = dw_mci_rk3576_parse_dt,
+ .init = dw_mci_rk3572_init,
+};
+
static const struct dw_mci_drv_data rk3576_drv_data = {
.common_caps = MMC_CAP_CMD23,
.set_ios = dw_mci_rk3288_set_ios,
@@ -554,6 +576,8 @@ static const struct of_device_id dw_mci_rockchip_match[] = {
.data = &rk2928_drv_data },
{ .compatible = "rockchip,rk3288-dw-mshc",
.data = &rk3288_drv_data },
+ { .compatible = "rockchip,rk3572-dw-mshc",
+ .data = &rk3572_drv_data },
{ .compatible = "rockchip,rk3576-dw-mshc",
.data = &rk3576_drv_data },
{},
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 25/27] dt-bindings: arm: rockchip: Add Forlinx OK3572-C
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (23 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 24/27] mmc: dw_mmc-rockchip: Keep RK3572 NVM domain powered Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 26/27] arm64: dts: rockchip: Add RK3572 SoC Cunhao Lu via B4 Relay
` (2 subsequent siblings)
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
The board uses the FET3572-C system-on-module and falls back to the
RK3572 SoC compatible.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index a799bb843f74..2880ea741e73 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -331,6 +331,12 @@ properties:
- const: forlinx,fet3588-c
- const: rockchip,rk3588
+ - description: Forlinx OK3572-C with FET3572-C
+ items:
+ - const: forlinx,ok3572-c
+ - const: forlinx,fet3572-c
+ - const: rockchip,rk3572
+
- description: FriendlyElec NanoPi R2 series boards
items:
- enum:
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 26/27] arm64: dts: rockchip: Add RK3572 SoC
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (24 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 25/27] dt-bindings: arm: rockchip: Add Forlinx OK3572-C Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 27/27] arm64: dts: rockchip: Add initial support for Forlinx OK3572-C Cunhao Lu via B4 Relay
2026-10-21 23:00 ` [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Shawn Lin
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Describe the RK3572 CPU, SCMI, thermal, pinctrl, and boot-peripheral
blocks.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
arch/arm64/boot/dts/rockchip/rk3572-opp.dtsi | 165 +
arch/arm64/boot/dts/rockchip/rk3572-pinctrl.dtsi | 3935 ++++++++++++++++++++++
arch/arm64/boot/dts/rockchip/rk3572.dtsi | 1325 ++++++++
3 files changed, 5425 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3572-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3572-opp.dtsi
new file mode 100644
index 000000000000..e5432fe06705
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3572-opp.dtsi
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ */
+
+/ {
+ cluster0_opp_table: opp-table-cluster0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-600000000 {
+ clock-latency-ns = <40000>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <850000 850000 950000>;
+ };
+
+ opp-816000000 {
+ clock-latency-ns = <40000>;
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <850000 850000 950000>;
+ };
+
+ opp-1008000000 {
+ clock-latency-ns = <40000>;
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <850000 850000 950000>;
+ };
+
+ opp-1200000000 {
+ clock-latency-ns = <40000>;
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <850000 850000 950000>;
+ };
+ };
+
+ cluster1_opp_table: opp-table-cluster1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-600000000 {
+ clock-latency-ns = <40000>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <850000 850000 950000>;
+ };
+
+ opp-816000000 {
+ clock-latency-ns = <40000>;
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <850000 850000 950000>;
+ };
+
+ opp-1008000000 {
+ clock-latency-ns = <40000>;
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <850000 850000 950000>;
+ };
+
+ opp-1200000000 {
+ clock-latency-ns = <40000>;
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <850000 850000 950000>;
+ };
+ };
+
+ cluster2_opp_table: opp-table-cluster2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-600000000 {
+ clock-latency-ns = <40000>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <850000 850000 950000>;
+ };
+
+ opp-816000000 {
+ clock-latency-ns = <40000>;
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <850000 850000 950000>;
+ };
+
+ opp-1008000000 {
+ clock-latency-ns = <40000>;
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <850000 850000 950000>;
+ };
+
+ opp-1200000000 {
+ clock-latency-ns = <40000>;
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <850000 850000 950000>;
+ };
+ };
+};
+
+&cpu_b0 {
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cluster2_opp_table>;
+};
+
+&cpu_b1 {
+ operating-points-v2 = <&cluster2_opp_table>;
+};
+
+&cpu_l0 {
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cluster0_opp_table>;
+};
+
+&cpu_l1 {
+ operating-points-v2 = <&cluster0_opp_table>;
+};
+
+&cpu_l2 {
+ operating-points-v2 = <&cluster0_opp_table>;
+};
+
+&cpu_l3 {
+ operating-points-v2 = <&cluster0_opp_table>;
+};
+
+&cpu_l4 {
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cluster1_opp_table>;
+};
+
+&cpu_l5 {
+ operating-points-v2 = <&cluster1_opp_table>;
+};
+
+&big_core_thermal {
+ cooling-maps {
+ map0 {
+ cooling-device =
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ trip = <&big_core_hot>;
+ };
+ };
+
+ trips {
+ big_core_hot: big-core-hot {
+ hysteresis = <2000>;
+ temperature = <85000>;
+ type = "passive";
+ };
+ };
+};
+
+&little_core_thermal {
+ cooling-maps {
+ map0 {
+ cooling-device =
+ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ trip = <&little_core_hot>;
+ };
+ };
+
+ trips {
+ little_core_hot: little-core-hot {
+ hysteresis = <2000>;
+ temperature = <85000>;
+ type = "passive";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3572-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3572-pinctrl.dtsi
new file mode 100644
index 000000000000..8440feea419b
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3572-pinctrl.dtsi
@@ -0,0 +1,3935 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rockchip-pinconf.dtsi"
+
+&pinctrl {
+ aupll_clk {
+ /omit-if-no-ref/
+ aupll_clk_pins: aupll-clk-pins {
+ rockchip,pins =
+ <0 RK_PA0 3 &pcfg_pull_none>;
+ };
+ };
+
+ cam_clk0 {
+ /omit-if-no-ref/
+ cam_clk0m0_clk0_pins: cam-clk0m0-clk0-pins {
+ rockchip,pins =
+ <3 RK_PD7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cam_clk0m1_clk0_pins: cam-clk0m1-clk0-pins {
+ rockchip,pins =
+ <2 RK_PD4 3 &pcfg_pull_none>;
+ };
+ };
+
+ cam_clk1 {
+ /omit-if-no-ref/
+ cam_clk1m0_clk1_pins: cam-clk1m0-clk1-pins {
+ rockchip,pins =
+ <4 RK_PA0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cam_clk1m1_clk1_pins: cam-clk1m1-clk1-pins {
+ rockchip,pins =
+ <2 RK_PD5 3 &pcfg_pull_none>;
+ };
+ };
+
+ cam_clk2 {
+ /omit-if-no-ref/
+ cam_clk2m0_clk2_pins: cam-clk2m0-clk2-pins {
+ rockchip,pins =
+ <4 RK_PA1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cam_clk2m1_clk2_pins: cam-clk2m1-clk2-pins {
+ rockchip,pins =
+ <2 RK_PD6 3 &pcfg_pull_none>;
+ };
+ };
+
+ can0 {
+ /omit-if-no-ref/
+ can0m0_pins: can0m0-pins {
+ rockchip,pins =
+ <2 RK_PA2 13 &pcfg_pull_none>,
+ <2 RK_PA3 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can0m1_pins: can0m1-pins {
+ rockchip,pins =
+ <4 RK_PB3 14 &pcfg_pull_none>,
+ <4 RK_PB2 14 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can0m2_pins: can0m2-pins {
+ rockchip,pins =
+ <2 RK_PB3 13 &pcfg_pull_none>,
+ <2 RK_PB1 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can0m3_pins: can0m3-pins {
+ rockchip,pins =
+ <3 RK_PC1 13 &pcfg_pull_none>,
+ <3 RK_PC4 13 &pcfg_pull_none>;
+ };
+ };
+
+ can1 {
+ /omit-if-no-ref/
+ can1m0_pins: can1m0-pins {
+ rockchip,pins =
+ <2 RK_PA0 13 &pcfg_pull_none>,
+ <2 RK_PA1 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can1m1_pins: can1m1-pins {
+ rockchip,pins =
+ <4 RK_PB7 13 &pcfg_pull_none>,
+ <4 RK_PB6 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can1m2_pins: can1m2-pins {
+ rockchip,pins =
+ <2 RK_PC2 13 &pcfg_pull_none>,
+ <2 RK_PC3 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can1m3_pins: can1m3-pins {
+ rockchip,pins =
+ <2 RK_PD7 13 &pcfg_pull_none>,
+ <2 RK_PD6 13 &pcfg_pull_none>;
+ };
+ };
+
+ can2 {
+ /omit-if-no-ref/
+ can2m0_pins: can2m0-pins {
+ rockchip,pins =
+ <2 RK_PA4 13 &pcfg_pull_none>,
+ <2 RK_PA5 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can2m1_pins: can2m1-pins {
+ rockchip,pins =
+ <1 RK_PC2 13 &pcfg_pull_none>,
+ <1 RK_PC3 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can2m2_pins: can2m2-pins {
+ rockchip,pins =
+ <3 RK_PB7 13 &pcfg_pull_none>,
+ <3 RK_PC0 13 &pcfg_pull_none>;
+ };
+ };
+
+ can3 {
+ /omit-if-no-ref/
+ can3m0_pins: can3m0-pins {
+ rockchip,pins =
+ <1 RK_PD6 13 &pcfg_pull_none>,
+ <1 RK_PD5 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can3m1_pins: can3m1-pins {
+ rockchip,pins =
+ <2 RK_PD5 13 &pcfg_pull_none>,
+ <2 RK_PD4 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can3m2_pins: can3m2-pins {
+ rockchip,pins =
+ <3 RK_PC2 13 &pcfg_pull_none>,
+ <3 RK_PC3 13 &pcfg_pull_none>;
+ };
+ };
+
+ clk0_32k {
+ /omit-if-no-ref/
+ clk0_32k_pins: clk0-32k-pins {
+ rockchip,pins =
+ <0 RK_PA2 10 &pcfg_pull_none>;
+ };
+ };
+
+ clk1_32k {
+ /omit-if-no-ref/
+ clk1_32k_pins: clk1-32k-pins {
+ rockchip,pins =
+ <1 RK_PD5 7 &pcfg_pull_none>;
+ };
+ };
+
+ clk_32k {
+ /omit-if-no-ref/
+ clk_32k_pins: clk-32k-pins {
+ rockchip,pins =
+ <0 RK_PA2 9 &pcfg_pull_none>;
+ };
+ };
+
+ cpubig {
+ /omit-if-no-ref/
+ cpubig_pins: cpubig-pins {
+ rockchip,pins =
+ <0 RK_PD2 13 &pcfg_pull_none>;
+ };
+ };
+
+ cpulit {
+ /omit-if-no-ref/
+ cpulit_pins: cpulit-pins {
+ rockchip,pins =
+ <0 RK_PC0 13 &pcfg_pull_none>;
+ };
+ };
+
+ dsm_aud {
+ /omit-if-no-ref/
+ dsm_audm0_ln_pins: dsm-audm0-ln-pins {
+ rockchip,pins =
+ <2 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dsm_audm0_lp_pins: dsm-audm0-lp-pins {
+ rockchip,pins =
+ <2 RK_PA0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dsm_audm0_rn_pins: dsm-audm0-rn-pins {
+ rockchip,pins =
+ <2 RK_PA3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dsm_audm0_rp_pins: dsm-audm0-rp-pins {
+ rockchip,pins =
+ <2 RK_PA2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dsm_audm1_ln_pins: dsm-audm1-ln-pins {
+ rockchip,pins =
+ <4 RK_PB1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dsm_audm1_lp_pins: dsm-audm1-lp-pins {
+ rockchip,pins =
+ <4 RK_PB0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dsm_audm1_rn_pins: dsm-audm1-rn-pins {
+ rockchip,pins =
+ <4 RK_PB3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dsm_audm1_rp_pins: dsm-audm1-rp-pins {
+ rockchip,pins =
+ <4 RK_PB2 3 &pcfg_pull_none>;
+ };
+ };
+
+ dsmc {
+ /omit-if-no-ref/
+ dsmc_bus16_pins: dsmc-bus16-pins {
+ rockchip,pins =
+ <3 RK_PD6 2 &pcfg_pull_none>,
+ <3 RK_PD5 2 &pcfg_pull_none>,
+ <3 RK_PD3 2 &pcfg_pull_none>,
+ <3 RK_PB0 2 &pcfg_pull_none>,
+ <3 RK_PD1 2 &pcfg_pull_none>,
+ <3 RK_PD2 2 &pcfg_pull_none>,
+ <3 RK_PD4 2 &pcfg_pull_none>,
+ <3 RK_PD0 2 &pcfg_pull_none>,
+ <3 RK_PC7 2 &pcfg_pull_none>,
+ <3 RK_PC6 2 &pcfg_pull_none>,
+ <3 RK_PC5 2 &pcfg_pull_none>,
+ <3 RK_PC4 2 &pcfg_pull_none>,
+ <3 RK_PC1 2 &pcfg_pull_none>,
+ <3 RK_PC0 2 &pcfg_pull_none>,
+ <3 RK_PB5 2 &pcfg_pull_none>,
+ <3 RK_PB4 2 &pcfg_pull_none>,
+ <3 RK_PB3 2 &pcfg_pull_none>,
+ <3 RK_PB2 2 &pcfg_pull_none>,
+ <3 RK_PB1 2 &pcfg_pull_none>,
+ <3 RK_PA7 2 &pcfg_pull_none>,
+ <3 RK_PA6 2 &pcfg_pull_none>,
+ <3 RK_PA5 2 &pcfg_pull_none>,
+ <3 RK_PB7 2 &pcfg_pull_none>,
+ <3 RK_PB6 2 &pcfg_pull_none>,
+ <4 RK_PA0 2 &pcfg_pull_none>,
+ <3 RK_PC2 2 &pcfg_pull_none>,
+ <4 RK_PA1 2 &pcfg_pull_none>,
+ <3 RK_PC3 2 &pcfg_pull_none>,
+ <3 RK_PA4 2 &pcfg_pull_none>,
+ <3 RK_PD7 2 &pcfg_pull_none>;
+ };
+ };
+
+ edp_tx {
+ /omit-if-no-ref/
+ edp_txm0_pins: edp-txm0-pins {
+ rockchip,pins =
+ <4 RK_PB1 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ edp_txm1_pins: edp-txm1-pins {
+ rockchip,pins =
+ <0 RK_PB6 10 &pcfg_pull_none>;
+ };
+ };
+
+ emmc {
+ /omit-if-no-ref/
+ emmc_rstnout_pins: emmc-rstnout-pins {
+ rockchip,pins =
+ <1 RK_PB3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ emmc_bus8_pins: emmc-bus8-pins {
+ rockchip,pins =
+ <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
+ <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
+ <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
+ <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
+ <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
+ <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+ <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
+ <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_clk_pins: emmc-clk-pins {
+ rockchip,pins =
+ <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_cmd_pins: emmc-cmd-pins {
+ rockchip,pins =
+ <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_strb_pins: emmc-strb-pins {
+ rockchip,pins =
+ <1 RK_PB2 1 &pcfg_pull_none>;
+ };
+ };
+
+ eth0 {
+ /omit-if-no-ref/
+ eth0_miim_pins: eth0-miim-pins {
+ rockchip,pins =
+ <2 RK_PC6 1 &pcfg_pull_none>,
+ <2 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0_rx_bus2_pins: eth0-rx-bus2-pins {
+ rockchip,pins =
+ <2 RK_PC7 1 &pcfg_pull_none>,
+ <2 RK_PD2 1 &pcfg_pull_none>,
+ <2 RK_PD1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0_tx_bus2_pins: eth0-tx-bus2-pins {
+ rockchip,pins =
+ <2 RK_PD3 1 &pcfg_pull_none>,
+ <2 RK_PD4 1 &pcfg_pull_none>,
+ <2 RK_PD5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0_rgmii_clk_pins: eth0-rgmii-clk-pins {
+ rockchip,pins =
+ <2 RK_PD7 1 &pcfg_pull_none>,
+ <2 RK_PD6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0_rgmii_bus_pins: eth0-rgmii-bus-pins {
+ rockchip,pins =
+ <2 RK_PC1 1 &pcfg_pull_none>,
+ <2 RK_PC0 1 &pcfg_pull_none>,
+ <2 RK_PC2 1 &pcfg_pull_none>,
+ <2 RK_PC3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0_mclk_pins: eth0-mclk-pins {
+ rockchip,pins =
+ <2 RK_PD0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0_ppsclk_pins: eth0-ppsclk-pins {
+ rockchip,pins =
+ <2 RK_PB6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0_ppstrig_pins: eth0-ppstrig-pins {
+ rockchip,pins =
+ <2 RK_PB7 1 &pcfg_pull_none>;
+ };
+ };
+
+ eth0_ptp {
+ /omit-if-no-ref/
+ eth0_ptp_refclk_pins: eth0-ptp-refclk-pins {
+ rockchip,pins =
+ <2 RK_PB5 1 &pcfg_pull_none>;
+ };
+ };
+
+ eth1 {
+ /omit-if-no-ref/
+ eth1m0_miim_pins: eth1m0-miim-pins {
+ rockchip,pins =
+ <3 RK_PA6 1 &pcfg_pull_none>,
+ <3 RK_PA5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m0_rx_bus2_pins: eth1m0-rx-bus2-pins {
+ rockchip,pins =
+ <3 RK_PA7 1 &pcfg_pull_none>,
+ <3 RK_PB2 1 &pcfg_pull_none>,
+ <3 RK_PB1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m0_tx_bus2_pins: eth1m0-tx-bus2-pins {
+ rockchip,pins =
+ <3 RK_PB3 1 &pcfg_pull_none>,
+ <3 RK_PB5 1 &pcfg_pull_none>,
+ <3 RK_PB4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m0_rgmii_clk_pins: eth1m0-rgmii-clk-pins {
+ rockchip,pins =
+ <3 RK_PD1 1 &pcfg_pull_none>,
+ <3 RK_PB6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m0_rgmii_bus_pins: eth1m0-rgmii-bus-pins {
+ rockchip,pins =
+ <3 RK_PD3 1 &pcfg_pull_none>,
+ <3 RK_PD2 1 &pcfg_pull_none>,
+ <3 RK_PC3 1 &pcfg_pull_none>,
+ <3 RK_PC2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m0_mclk_pins: eth1m0-mclk-pins {
+ rockchip,pins =
+ <3 RK_PB0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m0_ppsclk_pins: eth1m0-ppsclk-pins {
+ rockchip,pins =
+ <3 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m0_ppstrig_pins: eth1m0-ppstrig-pins {
+ rockchip,pins =
+ <3 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m1_miim_pins: eth1m1-miim-pins {
+ rockchip,pins =
+ <1 RK_PD2 1 &pcfg_pull_none>,
+ <1 RK_PD3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m1_rx_bus2_pins: eth1m1-rx-bus2-pins {
+ rockchip,pins =
+ <1 RK_PD1 1 &pcfg_pull_none>,
+ <1 RK_PC7 1 &pcfg_pull_none>,
+ <1 RK_PD0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m1_tx_bus2_pins: eth1m1-tx-bus2-pins {
+ rockchip,pins =
+ <1 RK_PC6 1 &pcfg_pull_none>,
+ <1 RK_PC4 1 &pcfg_pull_none>,
+ <1 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m1_rgmii_clk_pins: eth1m1-rgmii-clk-pins {
+ rockchip,pins =
+ <1 RK_PB6 1 &pcfg_pull_none>,
+ <1 RK_PC1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m1_rgmii_bus_pins: eth1m1-rgmii-bus-pins {
+ rockchip,pins =
+ <1 RK_PB4 1 &pcfg_pull_none>,
+ <1 RK_PB5 1 &pcfg_pull_none>,
+ <1 RK_PB7 1 &pcfg_pull_none>,
+ <1 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m1_mclk_pins: eth1m1-mclk-pins {
+ rockchip,pins =
+ <1 RK_PD4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m1_ppsclk_pins: eth1m1-ppsclk-pins {
+ rockchip,pins =
+ <1 RK_PC2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m1_ppstrig_pins: eth1m1-ppstrig-pins {
+ rockchip,pins =
+ <1 RK_PC3 1 &pcfg_pull_none>;
+ };
+ };
+
+ eth1_ptp {
+ /omit-if-no-ref/
+ eth1m0_ptp_refclk_pins: eth1m0-ptp-refclk-pins {
+ rockchip,pins =
+ <3 RK_PC1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m1_ptp_refclk_pins: eth1m1-ptp-refclk-pins {
+ rockchip,pins =
+ <1 RK_PD6 1 &pcfg_pull_none>;
+ };
+ };
+
+ eth_clk0_25m {
+ /omit-if-no-ref/
+ eth_clk0_25m_out_pins: eth-clk0-25m-out-pins {
+ rockchip,pins =
+ <2 RK_PC4 1 &pcfg_pull_none>;
+ };
+ };
+
+ eth_clk1_25m {
+ /omit-if-no-ref/
+ ethm0_clk1_25m_out_pins: ethm0-clk1-25m-out-pins {
+ rockchip,pins =
+ <3 RK_PA4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ ethm1_clk1_25m_out_pins: ethm1-clk1-25m-out-pins {
+ rockchip,pins =
+ <1 RK_PD5 1 &pcfg_pull_none>;
+ };
+ };
+
+ fspi0 {
+ /omit-if-no-ref/
+ fspi0_pins: fspi0-pins {
+ rockchip,pins =
+ <1 RK_PB1 2 &pcfg_pull_none>,
+ <1 RK_PA0 2 &pcfg_pull_none>,
+ <1 RK_PA1 2 &pcfg_pull_none>,
+ <1 RK_PA2 2 &pcfg_pull_none>,
+ <1 RK_PA3 2 &pcfg_pull_none>,
+ <1 RK_PA4 2 &pcfg_pull_none>,
+ <1 RK_PA5 2 &pcfg_pull_none>,
+ <1 RK_PA6 2 &pcfg_pull_none>,
+ <1 RK_PA7 2 &pcfg_pull_none>,
+ <1 RK_PB2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fspi0_csn0_pins: fspi0-csn0-pins {
+ rockchip,pins =
+ <1 RK_PB3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fspi0_csn1_pins: fspi0-csn1-pins {
+ rockchip,pins =
+ <1 RK_PB0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fspi0_rst_pins: fspi0-rst-pins {
+ rockchip,pins =
+ <1 RK_PB0 3 &pcfg_pull_none>;
+ };
+ };
+
+ fspi1 {
+ /omit-if-no-ref/
+ fspi1m0_pins: fspi1m0-pins {
+ rockchip,pins =
+ <2 RK_PA5 1 &pcfg_pull_none>,
+ <2 RK_PA0 1 &pcfg_pull_none>,
+ <2 RK_PA1 1 &pcfg_pull_none>,
+ <2 RK_PA2 1 &pcfg_pull_none>,
+ <2 RK_PA3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fspi1m0_csn0_pins: fspi1m0-csn0-pins {
+ rockchip,pins =
+ <2 RK_PA4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fspi1m1_pins: fspi1m1-pins {
+ rockchip,pins =
+ <2 RK_PD5 2 &pcfg_pull_none>,
+ <2 RK_PD3 2 &pcfg_pull_none>,
+ <2 RK_PD2 2 &pcfg_pull_none>,
+ <2 RK_PD1 2 &pcfg_pull_none>,
+ <2 RK_PD0 2 &pcfg_pull_none>,
+ <2 RK_PC7 2 &pcfg_pull_none>,
+ <2 RK_PC6 2 &pcfg_pull_none>,
+ <2 RK_PC5 2 &pcfg_pull_none>,
+ <2 RK_PC4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fspi1m1_csn0_pins: fspi1m1-csn0-pins {
+ rockchip,pins =
+ <2 RK_PD6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fspi1m1_csn1_pins: fspi1m1-csn1-pins {
+ rockchip,pins =
+ <2 RK_PD7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fspi1_pins: fspi1-pins {
+ rockchip,pins =
+ <2 RK_PD4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fspi1_rst_pins: fspi1-rst-pins {
+ rockchip,pins =
+ <2 RK_PD7 3 &pcfg_pull_none>;
+ };
+ };
+
+ gpu {
+ /omit-if-no-ref/
+ gpu_pins: gpu-pins {
+ rockchip,pins =
+ <0 RK_PD3 13 &pcfg_pull_none>;
+ };
+ };
+
+ hdmi_tx {
+ /omit-if-no-ref/
+ hdmi_txm0_cec_pins: hdmi-txm0-cec-pins {
+ rockchip,pins =
+ <4 RK_PB0 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_txm0_hpdin_pins: hdmi-txm0-hpdin-pins {
+ rockchip,pins =
+ <4 RK_PB1 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_txm0_ddc_pins: hdmi-txm0-ddc-pins {
+ rockchip,pins =
+ <4 RK_PB2 13 &pcfg_pull_none>,
+ <4 RK_PB3 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_txm1_cec_pins: hdmi-txm1-cec-pins {
+ rockchip,pins =
+ <0 RK_PC3 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_txm1_hpdin_pins: hdmi-txm1-hpdin-pins {
+ rockchip,pins =
+ <0 RK_PB6 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_txm1_ddc_pins: hdmi-txm1-ddc-pins {
+ rockchip,pins =
+ <1 RK_PC6 14 &pcfg_pull_none>,
+ <1 RK_PC7 14 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ /omit-if-no-ref/
+ i2c0m0_xfer_pins: i2c0m0-xfer-pins {
+ rockchip,pins =
+ <0 RK_PB0 11 &pcfg_pull_none_smt>,
+ <0 RK_PB1 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c0m1_xfer_pins: i2c0m1-xfer-pins {
+ rockchip,pins =
+ <0 RK_PC1 11 &pcfg_pull_none_smt>,
+ <0 RK_PC2 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c1 {
+ /omit-if-no-ref/
+ i2c1m0_xfer_pins: i2c1m0-xfer-pins {
+ rockchip,pins =
+ <0 RK_PB2 11 &pcfg_pull_none_smt>,
+ <0 RK_PB3 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c1m1_xfer_pins: i2c1m1-xfer-pins {
+ rockchip,pins =
+ <0 RK_PB4 11 &pcfg_pull_none_smt>,
+ <0 RK_PB5 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c2 {
+ /omit-if-no-ref/
+ i2c2m0_xfer_pins: i2c2m0-xfer-pins {
+ rockchip,pins =
+ <0 RK_PB7 11 &pcfg_pull_none_smt>,
+ <0 RK_PC0 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c2m1_xfer_pins: i2c2m1-xfer-pins {
+ rockchip,pins =
+ <1 RK_PA0 11 &pcfg_pull_none_smt>,
+ <1 RK_PA1 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c2m2_xfer_pins: i2c2m2-xfer-pins {
+ rockchip,pins =
+ <2 RK_PB1 11 &pcfg_pull_none_smt>,
+ <2 RK_PB3 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c2m3_xfer_pins: i2c2m3-xfer-pins {
+ rockchip,pins =
+ <4 RK_PB2 11 &pcfg_pull_none_smt>,
+ <4 RK_PB3 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c3 {
+ /omit-if-no-ref/
+ i2c3m0_xfer_pins: i2c3m0-xfer-pins {
+ rockchip,pins =
+ <2 RK_PC3 11 &pcfg_pull_none_smt>,
+ <2 RK_PC2 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c3m1_xfer_pins: i2c3m1-xfer-pins {
+ rockchip,pins =
+ <0 RK_PC6 11 &pcfg_pull_none_smt>,
+ <0 RK_PC7 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c3m2_xfer_pins: i2c3m2-xfer-pins {
+ rockchip,pins =
+ <3 RK_PD4 11 &pcfg_pull_none_smt>,
+ <3 RK_PD5 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c3m3_xfer_pins: i2c3m3-xfer-pins {
+ rockchip,pins =
+ <4 RK_PB0 11 &pcfg_pull_none_smt>,
+ <4 RK_PB1 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c4 {
+ /omit-if-no-ref/
+ i2c4m0_xfer_pins: i2c4m0-xfer-pins {
+ rockchip,pins =
+ <0 RK_PD2 11 &pcfg_pull_none_smt>,
+ <0 RK_PD3 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c4m1_xfer_pins: i2c4m1-xfer-pins {
+ rockchip,pins =
+ <2 RK_PB2 11 &pcfg_pull_none_smt>,
+ <2 RK_PB4 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c4m2_xfer_pins: i2c4m2-xfer-pins {
+ rockchip,pins =
+ <2 RK_PD6 11 &pcfg_pull_none_smt>,
+ <2 RK_PD7 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c4m3_xfer_pins: i2c4m3-xfer-pins {
+ rockchip,pins =
+ <3 RK_PC0 11 &pcfg_pull_none_smt>,
+ <3 RK_PB7 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c5 {
+ /omit-if-no-ref/
+ i2c5m0_xfer_pins: i2c5m0-xfer-pins {
+ rockchip,pins =
+ <2 RK_PA5 11 &pcfg_pull_none_smt>,
+ <2 RK_PA4 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c5m1_xfer_pins: i2c5m1-xfer-pins {
+ rockchip,pins =
+ <1 RK_PD4 11 &pcfg_pull_none_smt>,
+ <1 RK_PD5 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c5m2_xfer_pins: i2c5m2-xfer-pins {
+ rockchip,pins =
+ <2 RK_PD4 11 &pcfg_pull_none_smt>,
+ <2 RK_PD5 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c5m3_xfer_pins: i2c5m3-xfer-pins {
+ rockchip,pins =
+ <3 RK_PC4 11 &pcfg_pull_none_smt>,
+ <3 RK_PC1 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c6 {
+ /omit-if-no-ref/
+ i2c6m0_xfer_pins: i2c6m0-xfer-pins {
+ rockchip,pins =
+ <0 RK_PA2 11 &pcfg_pull_none_smt>,
+ <0 RK_PA5 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c6m1_xfer_pins: i2c6m1-xfer-pins {
+ rockchip,pins =
+ <1 RK_PC2 11 &pcfg_pull_none_smt>,
+ <1 RK_PC3 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c6m2_xfer_pins: i2c6m2-xfer-pins {
+ rockchip,pins =
+ <2 RK_PD2 11 &pcfg_pull_none_smt>,
+ <2 RK_PD3 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c6m3_xfer_pins: i2c6m3-xfer-pins {
+ rockchip,pins =
+ <4 RK_PB6 11 &pcfg_pull_none_smt>,
+ <4 RK_PB7 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c7 {
+ /omit-if-no-ref/
+ i2c7m0_xfer_pins: i2c7m0-xfer-pins {
+ rockchip,pins =
+ <1 RK_PB0 11 &pcfg_pull_none_smt>,
+ <1 RK_PB3 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c7m1_xfer_pins: i2c7m1-xfer-pins {
+ rockchip,pins =
+ <2 RK_PD0 11 &pcfg_pull_none_smt>,
+ <2 RK_PD1 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c7m2_xfer_pins: i2c7m2-xfer-pins {
+ rockchip,pins =
+ <4 RK_PA0 11 &pcfg_pull_none_smt>,
+ <4 RK_PA1 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c7m3_xfer_pins: i2c7m3-xfer-pins {
+ rockchip,pins =
+ <4 RK_PB4 11 &pcfg_pull_none_smt>,
+ <4 RK_PB5 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c8 {
+ /omit-if-no-ref/
+ i2c8m0_xfer_pins: i2c8m0-xfer-pins {
+ rockchip,pins =
+ <2 RK_PA0 11 &pcfg_pull_none_smt>,
+ <2 RK_PA1 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c8m1_xfer_pins: i2c8m1-xfer-pins {
+ rockchip,pins =
+ <1 RK_PC6 11 &pcfg_pull_none_smt>,
+ <1 RK_PC7 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c8m2_xfer_pins: i2c8m2-xfer-pins {
+ rockchip,pins =
+ <2 RK_PC4 11 &pcfg_pull_none_smt>,
+ <2 RK_PC5 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c8m3_xfer_pins: i2c8m3-xfer-pins {
+ rockchip,pins =
+ <3 RK_PB3 11 &pcfg_pull_none_smt>,
+ <3 RK_PB2 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c9 {
+ /omit-if-no-ref/
+ i2c9m0_xfer_pins: i2c9m0-xfer-pins {
+ rockchip,pins =
+ <1 RK_PA5 11 &pcfg_pull_none_smt>,
+ <1 RK_PA6 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c9m1_xfer_pins: i2c9m1-xfer-pins {
+ rockchip,pins =
+ <1 RK_PB5 11 &pcfg_pull_none_smt>,
+ <1 RK_PB4 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c9m2_xfer_pins: i2c9m2-xfer-pins {
+ rockchip,pins =
+ <2 RK_PC7 11 &pcfg_pull_none_smt>,
+ <2 RK_PC6 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c9m3_xfer_pins: i2c9m3-xfer-pins {
+ rockchip,pins =
+ <3 RK_PC2 11 &pcfg_pull_none_smt>,
+ <3 RK_PC3 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i3c0 {
+ /omit-if-no-ref/
+ i3c0m0_xfer_pins: i3c0m0-xfer-pins {
+ rockchip,pins =
+ <0 RK_PC1 12 &pcfg_pull_none_smt>,
+ <0 RK_PC2 12 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i3c0m1_xfer_pins: i3c0m1-xfer-pins {
+ rockchip,pins =
+ <1 RK_PD2 11 &pcfg_pull_none_smt>,
+ <1 RK_PD3 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i3c0_sda {
+ /omit-if-no-ref/
+ i3c0_sdam0_pu_pins: i3c0-sdam0-pu-pins {
+ rockchip,pins =
+ <0 RK_PC5 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i3c0_sdam1_pu_pins: i3c0-sdam1-pu-pins {
+ rockchip,pins =
+ <1 RK_PD1 11 &pcfg_pull_none>;
+ };
+ };
+
+ isp_flash {
+ /omit-if-no-ref/
+ isp_flashm0_pins: isp-flashm0-pins {
+ rockchip,pins =
+ <2 RK_PD0 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ isp_flashm1_pins: isp-flashm1-pins {
+ rockchip,pins =
+ <4 RK_PB5 1 &pcfg_pull_none>;
+ };
+ };
+
+ isp_prelight {
+ /omit-if-no-ref/
+ isp_prelightm0_pins: isp-prelightm0-pins {
+ rockchip,pins =
+ <2 RK_PC7 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ isp_prelightm1_pins: isp-prelightm1-pins {
+ rockchip,pins =
+ <4 RK_PB4 1 &pcfg_pull_none>;
+ };
+ };
+
+ jtag {
+ /omit-if-no-ref/
+ jtagm0_pins: jtagm0-pins {
+ rockchip,pins =
+ <2 RK_PA2 11 &pcfg_pull_none>,
+ <2 RK_PA3 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ jtagm1_pins: jtagm1-pins {
+ rockchip,pins =
+ <0 RK_PD4 10 &pcfg_pull_none>,
+ <0 RK_PD5 10 &pcfg_pull_none>;
+ };
+ };
+
+ mipi {
+ /omit-if-no-ref/
+ mipim0_pins: mipim0-pins {
+ rockchip,pins =
+ <2 RK_PC2 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim1_pins: mipim1-pins {
+ rockchip,pins =
+ <2 RK_PD6 14 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim2_pins: mipim2-pins {
+ rockchip,pins =
+ <4 RK_PA0 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim3_pins: mipim3-pins {
+ rockchip,pins =
+ <1 RK_PB3 13 &pcfg_pull_none>;
+ };
+ };
+
+ npu {
+ /omit-if-no-ref/
+ npu_pins: npu-pins {
+ rockchip,pins =
+ <0 RK_PB7 13 &pcfg_pull_none>;
+ };
+ };
+
+ pcie0 {
+ /omit-if-no-ref/
+ pcie0m0_pins: pcie0m0-pins {
+ rockchip,pins =
+ <2 RK_PD0 14 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ pcie0m1_pins: pcie0m1-pins {
+ rockchip,pins =
+ <1 RK_PB6 14 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ pcie0m2_pins: pcie0m2-pins {
+ rockchip,pins =
+ <2 RK_PC3 14 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ pcie0m3_pins: pcie0m3-pins {
+ rockchip,pins =
+ <4 RK_PB1 14 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ pcie0_buttonrstn_pins: pcie0-buttonrstn-pins {
+ rockchip,pins =
+ <1 RK_PC4 14 &pcfg_pull_none>;
+ };
+ };
+
+ pcie1 {
+ /omit-if-no-ref/
+ pcie1m0_pins: pcie1m0-pins {
+ rockchip,pins =
+ <2 RK_PD1 14 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ pcie1m1_pins: pcie1m1-pins {
+ rockchip,pins =
+ <1 RK_PB4 14 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ pcie1m2_pins: pcie1m2-pins {
+ rockchip,pins =
+ <2 RK_PB3 14 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ pcie1m3_pins: pcie1m3-pins {
+ rockchip,pins =
+ <4 RK_PB6 14 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ pcie1_buttonrstn_pins: pcie1-buttonrstn-pins {
+ rockchip,pins =
+ <1 RK_PC5 14 &pcfg_pull_none>;
+ };
+ };
+
+ pdm {
+ /omit-if-no-ref/
+ pdmm0_clk0_pins: pdmm0-clk0-pins {
+ rockchip,pins =
+ <0 RK_PC4 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_clk1_pins: pdmm0-clk1-pins {
+ rockchip,pins =
+ <0 RK_PC3 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_sdi0_pins: pdmm0-sdi0-pins {
+ rockchip,pins =
+ <0 RK_PD0 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_sdi1_pins: pdmm0-sdi1-pins {
+ rockchip,pins =
+ <0 RK_PD1 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_sdi2_pins: pdmm0-sdi2-pins {
+ rockchip,pins =
+ <0 RK_PD2 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_sdi3_pins: pdmm0-sdi3-pins {
+ rockchip,pins =
+ <0 RK_PD3 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_clk0_pins: pdmm1-clk0-pins {
+ rockchip,pins =
+ <2 RK_PB2 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_clk1_pins: pdmm1-clk1-pins {
+ rockchip,pins =
+ <2 RK_PB4 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_sdi0_pins: pdmm1-sdi0-pins {
+ rockchip,pins =
+ <2 RK_PC1 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_sdi1_pins: pdmm1-sdi1-pins {
+ rockchip,pins =
+ <2 RK_PC0 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_sdi2_pins: pdmm1-sdi2-pins {
+ rockchip,pins =
+ <2 RK_PB7 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_sdi3_pins: pdmm1-sdi3-pins {
+ rockchip,pins =
+ <2 RK_PB6 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm2_clk0_pins: pdmm2-clk0-pins {
+ rockchip,pins =
+ <1 RK_PC1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm2_clk1_pins: pdmm2-clk1-pins {
+ rockchip,pins =
+ <1 RK_PD5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm2_sdi0_pins: pdmm2-sdi0-pins {
+ rockchip,pins =
+ <1 RK_PC6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm2_sdi1_pins: pdmm2-sdi1-pins {
+ rockchip,pins =
+ <1 RK_PC7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm2_sdi2_pins: pdmm2-sdi2-pins {
+ rockchip,pins =
+ <1 RK_PC0 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm2_sdi3_pins: pdmm2-sdi3-pins {
+ rockchip,pins =
+ <1 RK_PD4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm3_clk0_pins: pdmm3-clk0-pins {
+ rockchip,pins =
+ <2 RK_PC5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm3_clk1_pins: pdmm3-clk1-pins {
+ rockchip,pins =
+ <2 RK_PC7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm3_sdi0_pins: pdmm3-sdi0-pins {
+ rockchip,pins =
+ <2 RK_PC4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm3_sdi1_pins: pdmm3-sdi1-pins {
+ rockchip,pins =
+ <2 RK_PC6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm3_sdi2_pins: pdmm3-sdi2-pins {
+ rockchip,pins =
+ <2 RK_PD0 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm3_sdi3_pins: pdmm3-sdi3-pins {
+ rockchip,pins =
+ <2 RK_PD1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm4_clk0_pins: pdmm4-clk0-pins {
+ rockchip,pins =
+ <3 RK_PB1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm4_clk1_pins: pdmm4-clk1-pins {
+ rockchip,pins =
+ <3 RK_PA7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm4_sdi0_pins: pdmm4-sdi0-pins {
+ rockchip,pins =
+ <3 RK_PB3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm4_sdi1_pins: pdmm4-sdi1-pins {
+ rockchip,pins =
+ <3 RK_PB2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm4_sdi2_pins: pdmm4-sdi2-pins {
+ rockchip,pins =
+ <3 RK_PA6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm4_sdi3_pins: pdmm4-sdi3-pins {
+ rockchip,pins =
+ <3 RK_PA5 5 &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ /omit-if-no-ref/
+ pmic_pins: pmic-pins {
+ rockchip,pins =
+ <0 RK_PA6 9 &pcfg_pull_none>;
+ };
+ };
+
+ pwm0 {
+ /omit-if-no-ref/
+ pwm0m0_ch0_pins: pwm0m0-ch0-pins {
+ rockchip,pins =
+ <0 RK_PC4 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m0_ch1_pins: pwm0m0-ch1-pins {
+ rockchip,pins =
+ <0 RK_PC3 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m1_ch0_pins: pwm0m1-ch0-pins {
+ rockchip,pins =
+ <1 RK_PC0 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m1_ch1_pins: pwm0m1-ch1-pins {
+ rockchip,pins =
+ <4 RK_PB1 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m2_ch0_pins: pwm0m2-ch0-pins {
+ rockchip,pins =
+ <2 RK_PD1 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m2_ch1_pins: pwm0m2-ch1-pins {
+ rockchip,pins =
+ <3 RK_PB6 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m3_ch0_pins: pwm0m3-ch0-pins {
+ rockchip,pins =
+ <3 RK_PB0 12 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ /omit-if-no-ref/
+ pwm1m0_ch0_pins: pwm1m0-ch0-pins {
+ rockchip,pins =
+ <0 RK_PB4 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m0_ch1_pins: pwm1m0-ch1-pins {
+ rockchip,pins =
+ <0 RK_PB5 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m0_ch2_pins: pwm1m0-ch2-pins {
+ rockchip,pins =
+ <0 RK_PB6 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m0_ch3_pins: pwm1m0-ch3-pins {
+ rockchip,pins =
+ <0 RK_PC0 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m0_ch4_pins: pwm1m0-ch4-pins {
+ rockchip,pins =
+ <0 RK_PB7 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m0_ch5_pins: pwm1m0-ch5-pins {
+ rockchip,pins =
+ <0 RK_PD2 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_ch0_pins: pwm1m1-ch0-pins {
+ rockchip,pins =
+ <1 RK_PB4 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_ch1_pins: pwm1m1-ch1-pins {
+ rockchip,pins =
+ <1 RK_PB5 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_ch2_pins: pwm1m1-ch2-pins {
+ rockchip,pins =
+ <1 RK_PD6 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_ch3_pins: pwm1m1-ch3-pins {
+ rockchip,pins =
+ <1 RK_PD2 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_ch4_pins: pwm1m1-ch4-pins {
+ rockchip,pins =
+ <1 RK_PD3 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_ch5_pins: pwm1m1-ch5-pins {
+ rockchip,pins =
+ <4 RK_PB0 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m2_ch0_pins: pwm1m2-ch0-pins {
+ rockchip,pins =
+ <3 RK_PA4 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m2_ch1_pins: pwm1m2-ch1-pins {
+ rockchip,pins =
+ <3 RK_PA5 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m2_ch2_pins: pwm1m2-ch2-pins {
+ rockchip,pins =
+ <2 RK_PD0 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m2_ch3_pins: pwm1m2-ch3-pins {
+ rockchip,pins =
+ <2 RK_PD2 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m2_ch4_pins: pwm1m2-ch4-pins {
+ rockchip,pins =
+ <2 RK_PD3 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m2_ch5_pins: pwm1m2-ch5-pins {
+ rockchip,pins =
+ <3 RK_PB5 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m3_ch2_pins: pwm1m3-ch2-pins {
+ rockchip,pins =
+ <3 RK_PA6 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m3_ch3_pins: pwm1m3-ch3-pins {
+ rockchip,pins =
+ <3 RK_PB1 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m3_ch4_pins: pwm1m3-ch4-pins {
+ rockchip,pins =
+ <3 RK_PB4 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m3_ch5_pins: pwm1m3-ch5-pins {
+ rockchip,pins =
+ <1 RK_PD4 12 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ /omit-if-no-ref/
+ pwm2m0_ch0_pins: pwm2m0-ch0-pins {
+ rockchip,pins =
+ <0 RK_PD3 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m0_ch1_pins: pwm2m0-ch1-pins {
+ rockchip,pins =
+ <1 RK_PB3 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m0_ch2_pins: pwm2m0-ch2-pins {
+ rockchip,pins =
+ <2 RK_PA0 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m0_ch3_pins: pwm2m0-ch3-pins {
+ rockchip,pins =
+ <2 RK_PA1 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m0_ch4_pins: pwm2m0-ch4-pins {
+ rockchip,pins =
+ <2 RK_PA4 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m0_ch5_pins: pwm2m0-ch5-pins {
+ rockchip,pins =
+ <2 RK_PB0 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m0_ch6_pins: pwm2m0-ch6-pins {
+ rockchip,pins =
+ <2 RK_PB5 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m0_ch7_pins: pwm2m0-ch7-pins {
+ rockchip,pins =
+ <2 RK_PC1 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_ch0_pins: pwm2m1-ch0-pins {
+ rockchip,pins =
+ <4 RK_PB2 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_ch1_pins: pwm2m1-ch1-pins {
+ rockchip,pins =
+ <4 RK_PB3 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_ch2_pins: pwm2m1-ch2-pins {
+ rockchip,pins =
+ <4 RK_PB6 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_ch3_pins: pwm2m1-ch3-pins {
+ rockchip,pins =
+ <4 RK_PB7 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_ch4_pins: pwm2m1-ch4-pins {
+ rockchip,pins =
+ <2 RK_PB1 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_ch5_pins: pwm2m1-ch5-pins {
+ rockchip,pins =
+ <4 RK_PB5 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_ch6_pins: pwm2m1-ch6-pins {
+ rockchip,pins =
+ <4 RK_PB4 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_ch7_pins: pwm2m1-ch7-pins {
+ rockchip,pins =
+ <1 RK_PB1 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m2_ch0_pins: pwm2m2-ch0-pins {
+ rockchip,pins =
+ <3 RK_PC2 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m2_ch1_pins: pwm2m2-ch1-pins {
+ rockchip,pins =
+ <3 RK_PC3 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m2_ch2_pins: pwm2m2-ch2-pins {
+ rockchip,pins =
+ <2 RK_PD6 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m2_ch3_pins: pwm2m2-ch3-pins {
+ rockchip,pins =
+ <2 RK_PD7 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m2_ch4_pins: pwm2m2-ch4-pins {
+ rockchip,pins =
+ <2 RK_PC4 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m2_ch5_pins: pwm2m2-ch5-pins {
+ rockchip,pins =
+ <2 RK_PC5 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m2_ch6_pins: pwm2m2-ch6-pins {
+ rockchip,pins =
+ <3 RK_PD6 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m2_ch7_pins: pwm2m2-ch7-pins {
+ rockchip,pins =
+ <3 RK_PD7 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m3_ch2_pins: pwm2m3-ch2-pins {
+ rockchip,pins =
+ <3 RK_PC5 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m3_ch3_pins: pwm2m3-ch3-pins {
+ rockchip,pins =
+ <3 RK_PD0 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m3_ch4_pins: pwm2m3-ch4-pins {
+ rockchip,pins =
+ <3 RK_PD2 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m3_ch5_pins: pwm2m3-ch5-pins {
+ rockchip,pins =
+ <3 RK_PD3 12 &pcfg_pull_none>;
+ };
+ };
+
+ pwr {
+ /omit-if-no-ref/
+ pwr_ctrl1_pins: pwr-ctrl1-pins {
+ rockchip,pins =
+ <0 RK_PA3 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwr_ctrl2_pins: pwr-ctrl2-pins {
+ rockchip,pins =
+ <0 RK_PA4 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwr_ctrl3_pins: pwr-ctrl3-pins {
+ rockchip,pins =
+ <0 RK_PA5 9 &pcfg_pull_none>;
+ };
+ };
+
+ ref_clk0 {
+ /omit-if-no-ref/
+ ref_clk0_clk0_pins: ref-clk0-clk0-pins {
+ rockchip,pins =
+ <0 RK_PA0 1 &pcfg_pull_none>;
+ };
+ };
+
+ ref_clk1 {
+ /omit-if-no-ref/
+ ref_clk1_clk1_pins: ref-clk1-clk1-pins {
+ rockchip,pins =
+ <0 RK_PB4 1 &pcfg_pull_none>;
+ };
+ };
+
+ ref_clk2 {
+ /omit-if-no-ref/
+ ref_clk2_clk2_pins: ref-clk2-clk2-pins {
+ rockchip,pins =
+ <0 RK_PB5 1 &pcfg_pull_none>;
+ };
+ };
+
+ sai0 {
+ /omit-if-no-ref/
+ sai0m0_lrck_pins: sai0m0-lrck-pins {
+ rockchip,pins =
+ <2 RK_PD1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_mclk_pins: sai0m0-mclk-pins {
+ rockchip,pins =
+ <2 RK_PC7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_sclk_pins: sai0m0-sclk-pins {
+ rockchip,pins =
+ <2 RK_PD0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_sdi0_pins: sai0m0-sdi0-pins {
+ rockchip,pins =
+ <2 RK_PD3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_sdi1_pins: sai0m0-sdi1-pins {
+ rockchip,pins =
+ <2 RK_PC5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_sdi2_pins: sai0m0-sdi2-pins {
+ rockchip,pins =
+ <2 RK_PC4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_sdi3_pins: sai0m0-sdi3-pins {
+ rockchip,pins =
+ <2 RK_PD6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_sdo0_pins: sai0m0-sdo0-pins {
+ rockchip,pins =
+ <2 RK_PD2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_sdo1_pins: sai0m0-sdo1-pins {
+ rockchip,pins =
+ <2 RK_PC6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_sdo2_pins: sai0m0-sdo2-pins {
+ rockchip,pins =
+ <2 RK_PD4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_sdo3_pins: sai0m0-sdo3-pins {
+ rockchip,pins =
+ <2 RK_PD5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_lrck_pins: sai0m1-lrck-pins {
+ rockchip,pins =
+ <0 RK_PC7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_mclk_pins: sai0m1-mclk-pins {
+ rockchip,pins =
+ <0 RK_PC4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_sclk_pins: sai0m1-sclk-pins {
+ rockchip,pins =
+ <0 RK_PC6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_sdi0_pins: sai0m1-sdi0-pins {
+ rockchip,pins =
+ <0 RK_PD0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_sdi1_pins: sai0m1-sdi1-pins {
+ rockchip,pins =
+ <0 RK_PD1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_sdi2_pins: sai0m1-sdi2-pins {
+ rockchip,pins =
+ <0 RK_PD2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_sdi3_pins: sai0m1-sdi3-pins {
+ rockchip,pins =
+ <0 RK_PD3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_sdo0_pins: sai0m1-sdo0-pins {
+ rockchip,pins =
+ <0 RK_PC5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_sdo1_pins: sai0m1-sdo1-pins {
+ rockchip,pins =
+ <0 RK_PD3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_sdo2_pins: sai0m1-sdo2-pins {
+ rockchip,pins =
+ <0 RK_PD2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_sdo3_pins: sai0m1-sdo3-pins {
+ rockchip,pins =
+ <0 RK_PD1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m2_lrck_pins: sai0m2-lrck-pins {
+ rockchip,pins =
+ <2 RK_PB4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m2_mclk_pins: sai0m2-mclk-pins {
+ rockchip,pins =
+ <2 RK_PB0 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m2_sclk_pins: sai0m2-sclk-pins {
+ rockchip,pins =
+ <2 RK_PB2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m2_sdi0_pins: sai0m2-sdi0-pins {
+ rockchip,pins =
+ <2 RK_PB5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m2_sdi1_pins: sai0m2-sdi1-pins {
+ rockchip,pins =
+ <2 RK_PB1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m2_sdi2_pins: sai0m2-sdi2-pins {
+ rockchip,pins =
+ <2 RK_PB3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m2_sdi3_pins: sai0m2-sdi3-pins {
+ rockchip,pins =
+ <2 RK_PC2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m2_sdo0_pins: sai0m2-sdo0-pins {
+ rockchip,pins =
+ <2 RK_PC1 5 &pcfg_pull_none>;
+ };
+ };
+
+ sai1 {
+ /omit-if-no-ref/
+ sai1m0_lrck_pins: sai1m0-lrck-pins {
+ rockchip,pins =
+ <2 RK_PB3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_mclk_pins: sai1m0-mclk-pins {
+ rockchip,pins =
+ <2 RK_PB0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_sclk_pins: sai1m0-sclk-pins {
+ rockchip,pins =
+ <2 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_sdi0_pins: sai1m0-sdi0-pins {
+ rockchip,pins =
+ <2 RK_PC1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_sdi1_pins: sai1m0-sdi1-pins {
+ rockchip,pins =
+ <2 RK_PC0 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_sdi2_pins: sai1m0-sdi2-pins {
+ rockchip,pins =
+ <2 RK_PB7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_sdi3_pins: sai1m0-sdi3-pins {
+ rockchip,pins =
+ <2 RK_PB6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_sdo0_pins: sai1m0-sdo0-pins {
+ rockchip,pins =
+ <2 RK_PB5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_sdo1_pins: sai1m0-sdo1-pins {
+ rockchip,pins =
+ <2 RK_PB6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_sdo2_pins: sai1m0-sdo2-pins {
+ rockchip,pins =
+ <2 RK_PB7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_sdo3_pins: sai1m0-sdo3-pins {
+ rockchip,pins =
+ <2 RK_PC0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_lrck_pins: sai1m1-lrck-pins {
+ rockchip,pins =
+ <4 RK_PA1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_mclk_pins: sai1m1-mclk-pins {
+ rockchip,pins =
+ <3 RK_PB0 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_sclk_pins: sai1m1-sclk-pins {
+ rockchip,pins =
+ <3 RK_PA4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_sdi0_pins: sai1m1-sdi0-pins {
+ rockchip,pins =
+ <3 RK_PB7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_sdi1_pins: sai1m1-sdi1-pins {
+ rockchip,pins =
+ <3 RK_PD4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_sdi2_pins: sai1m1-sdi2-pins {
+ rockchip,pins =
+ <3 RK_PD5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_sdi3_pins: sai1m1-sdi3-pins {
+ rockchip,pins =
+ <3 RK_PD6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_sdo0_pins: sai1m1-sdo0-pins {
+ rockchip,pins =
+ <4 RK_PA0 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_sdo1_pins: sai1m1-sdo1-pins {
+ rockchip,pins =
+ <3 RK_PD7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_sdo2_pins: sai1m1-sdo2-pins {
+ rockchip,pins =
+ <3 RK_PC1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_sdo3_pins: sai1m1-sdo3-pins {
+ rockchip,pins =
+ <3 RK_PC0 5 &pcfg_pull_none>;
+ };
+ };
+
+ sai2 {
+ /omit-if-no-ref/
+ sai2m0_lrck_pins: sai2m0-lrck-pins {
+ rockchip,pins =
+ <1 RK_PD2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m0_mclk_pins: sai2m0-mclk-pins {
+ rockchip,pins =
+ <1 RK_PD4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m0_sclk_pins: sai2m0-sclk-pins {
+ rockchip,pins =
+ <1 RK_PD1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m0_sdi_pins: sai2m0-sdi-pins {
+ rockchip,pins =
+ <1 RK_PD3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m0_sdo_pins: sai2m0-sdo-pins {
+ rockchip,pins =
+ <1 RK_PD0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m1_lrck_pins: sai2m1-lrck-pins {
+ rockchip,pins =
+ <3 RK_PC3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m1_mclk_pins: sai2m1-mclk-pins {
+ rockchip,pins =
+ <3 RK_PC4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m1_sclk_pins: sai2m1-sclk-pins {
+ rockchip,pins =
+ <3 RK_PC2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m1_sdi_pins: sai2m1-sdi-pins {
+ rockchip,pins =
+ <3 RK_PD2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m1_sdo_pins: sai2m1-sdo-pins {
+ rockchip,pins =
+ <3 RK_PD3 5 &pcfg_pull_none>;
+ };
+ };
+
+ sai3 {
+ /omit-if-no-ref/
+ sai3m0_lrck_pins: sai3m0-lrck-pins {
+ rockchip,pins =
+ <1 RK_PA6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m0_mclk_pins: sai3m0-mclk-pins {
+ rockchip,pins =
+ <1 RK_PA4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m0_sclk_pins: sai3m0-sclk-pins {
+ rockchip,pins =
+ <1 RK_PA5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m0_sdi_pins: sai3m0-sdi-pins {
+ rockchip,pins =
+ <1 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m0_sdo_pins: sai3m0-sdo-pins {
+ rockchip,pins =
+ <1 RK_PB2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m1_lrck_pins: sai3m1-lrck-pins {
+ rockchip,pins =
+ <2 RK_PA2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m1_mclk_pins: sai3m1-mclk-pins {
+ rockchip,pins =
+ <2 RK_PA1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m1_sclk_pins: sai3m1-sclk-pins {
+ rockchip,pins =
+ <2 RK_PA5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m1_sdi_pins: sai3m1-sdi-pins {
+ rockchip,pins =
+ <2 RK_PA3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m1_sdo_pins: sai3m1-sdo-pins {
+ rockchip,pins =
+ <2 RK_PA4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m2_lrck_pins: sai3m2-lrck-pins {
+ rockchip,pins =
+ <4 RK_PB2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m2_mclk_pins: sai3m2-mclk-pins {
+ rockchip,pins =
+ <4 RK_PB0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m2_sclk_pins: sai3m2-sclk-pins {
+ rockchip,pins =
+ <4 RK_PB3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m2_sdi_pins: sai3m2-sdi-pins {
+ rockchip,pins =
+ <4 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m2_sdo_pins: sai3m2-sdo-pins {
+ rockchip,pins =
+ <4 RK_PB4 4 &pcfg_pull_none>;
+ };
+ };
+
+ sai4 {
+ /omit-if-no-ref/
+ sai4m0_lrck_pins: sai4m0-lrck-pins {
+ rockchip,pins =
+ <1 RK_PA1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m0_mclk_pins: sai4m0-mclk-pins {
+ rockchip,pins =
+ <1 RK_PA4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m0_sclk_pins: sai4m0-sclk-pins {
+ rockchip,pins =
+ <1 RK_PA0 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m0_sdi0_pins: sai4m0-sdi0-pins {
+ rockchip,pins =
+ <1 RK_PB2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m0_sdi1_pins: sai4m0-sdi1-pins {
+ rockchip,pins =
+ <1 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m0_sdi2_pins: sai4m0-sdi2-pins {
+ rockchip,pins =
+ <1 RK_PA3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m0_sdi3_pins: sai4m0-sdi3-pins {
+ rockchip,pins =
+ <1 RK_PA2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m0_sdo0_pins: sai4m0-sdo0-pins {
+ rockchip,pins =
+ <1 RK_PA7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m0_sdo1_pins: sai4m0-sdo1-pins {
+ rockchip,pins =
+ <1 RK_PA2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m0_sdo2_pins: sai4m0-sdo2-pins {
+ rockchip,pins =
+ <1 RK_PA3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m0_sdo3_pins: sai4m0-sdo3-pins {
+ rockchip,pins =
+ <1 RK_PB1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m1_lrck_pins: sai4m1-lrck-pins {
+ rockchip,pins =
+ <1 RK_PB5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m1_mclk_pins: sai4m1-mclk-pins {
+ rockchip,pins =
+ <1 RK_PB4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m1_sclk_pins: sai4m1-sclk-pins {
+ rockchip,pins =
+ <1 RK_PC0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m1_sdi0_pins: sai4m1-sdi0-pins {
+ rockchip,pins =
+ <1 RK_PB6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m1_sdo0_pins: sai4m1-sdo0-pins {
+ rockchip,pins =
+ <1 RK_PB7 4 &pcfg_pull_none>;
+ };
+ };
+
+ sata0 {
+ /omit-if-no-ref/
+ sata0m0_sata_pins: sata0m0-sata-pins {
+ rockchip,pins =
+ <1 RK_PC3 14 &pcfg_pull_none>,
+ <1 RK_PC2 14 &pcfg_pull_none>,
+ <1 RK_PD6 14 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sata0m1_sata_pins: sata0m1-sata-pins {
+ rockchip,pins =
+ <3 RK_PD0 14 &pcfg_pull_none>,
+ <3 RK_PC7 14 &pcfg_pull_none>,
+ <3 RK_PC4 14 &pcfg_pull_none>;
+ };
+ };
+
+ sata1 {
+ /omit-if-no-ref/
+ sata1m0_sata_pins: sata1m0-sata-pins {
+ rockchip,pins =
+ <1 RK_PD2 14 &pcfg_pull_none>,
+ <1 RK_PD1 14 &pcfg_pull_none>,
+ <1 RK_PD3 14 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sata1m1_sata_pins: sata1m1-sata-pins {
+ rockchip,pins =
+ <4 RK_PA1 14 &pcfg_pull_none>,
+ <4 RK_PA0 14 &pcfg_pull_none>,
+ <3 RK_PD7 14 &pcfg_pull_none>;
+ };
+ };
+
+ sata30_port0 {
+ /omit-if-no-ref/
+ sata30_port0m0_port0_pins: sata30-port0m0-port0-pins {
+ rockchip,pins =
+ <2 RK_PD2 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sata30_port0m1_port0_pins: sata30-port0m1-port0-pins {
+ rockchip,pins =
+ <4 RK_PB5 6 &pcfg_pull_none>;
+ };
+ };
+
+ sata30_port1 {
+ /omit-if-no-ref/
+ sata30_port1m0_port1_pins: sata30-port1m0-port1-pins {
+ rockchip,pins =
+ <2 RK_PD1 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sata30_port1m1_port1_pins: sata30-port1m1-port1-pins {
+ rockchip,pins =
+ <4 RK_PB6 6 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc0 {
+ /omit-if-no-ref/
+ sdmmc0m0_bus4_pins: sdmmc0m0-bus4-pins {
+ rockchip,pins =
+ <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>,
+ <2 RK_PA1 2 &pcfg_pull_up_drv_level_2>,
+ <2 RK_PA2 2 &pcfg_pull_up_drv_level_2>,
+ <2 RK_PA3 2 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0m0_clk_pins: sdmmc0m0-clk-pins {
+ rockchip,pins =
+ <2 RK_PA5 2 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0m0_cmd_pins: sdmmc0m0-cmd-pins {
+ rockchip,pins =
+ <2 RK_PA4 2 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0m0_det_pins: sdmmc0m0-det-pins {
+ rockchip,pins =
+ <0 RK_PA7 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0m1_bus4_pins: sdmmc0m1-bus4-pins {
+ rockchip,pins =
+ <2 RK_PC4 3 &pcfg_pull_up_drv_level_2>,
+ <2 RK_PC5 3 &pcfg_pull_up_drv_level_2>,
+ <2 RK_PC6 3 &pcfg_pull_up_drv_level_2>,
+ <2 RK_PC7 3 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0m1_clk_pins: sdmmc0m1-clk-pins {
+ rockchip,pins =
+ <2 RK_PD1 3 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0m1_cmd_pins: sdmmc0m1-cmd-pins {
+ rockchip,pins =
+ <2 RK_PD0 3 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0m1_det_pins: sdmmc0m1-det-pins {
+ rockchip,pins =
+ <2 RK_PD3 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0m1_pwren_pins: sdmmc0m1-pwren-pins {
+ rockchip,pins =
+ <2 RK_PD2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_pwren_pins: sdmmc0-pwren-pins {
+ rockchip,pins =
+ <0 RK_PB6 1 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc1 {
+ /omit-if-no-ref/
+ sdmmc1m0_det_pins: sdmmc1m0-det-pins {
+ rockchip,pins =
+ <1 RK_PC3 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1m1_det_pins: sdmmc1m1-det-pins {
+ rockchip,pins =
+ <0 RK_PB6 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1_bus4_pins: sdmmc1-bus4-pins {
+ rockchip,pins =
+ <1 RK_PB4 2 &pcfg_pull_up_drv_level_2>,
+ <1 RK_PB5 2 &pcfg_pull_up_drv_level_2>,
+ <1 RK_PB6 2 &pcfg_pull_up_drv_level_2>,
+ <1 RK_PB7 2 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1_clk_pins: sdmmc1-clk-pins {
+ rockchip,pins =
+ <1 RK_PC1 2 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1_cmd_pins: sdmmc1-cmd-pins {
+ rockchip,pins =
+ <1 RK_PC0 2 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1_pwren_pins: sdmmc1-pwren-pins {
+ rockchip,pins =
+ <1 RK_PC2 2 &pcfg_pull_none>;
+ };
+ };
+
+ spdif {
+ /omit-if-no-ref/
+ spdifm0_rx0_pins: spdifm0-rx0-pins {
+ rockchip,pins =
+ <2 RK_PC2 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm0_tx0_pins: spdifm0-tx0-pins {
+ rockchip,pins =
+ <2 RK_PC3 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm0_tx1_pins: spdifm0-tx1-pins {
+ rockchip,pins =
+ <2 RK_PB4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm1_rx0_pins: spdifm1-rx0-pins {
+ rockchip,pins =
+ <1 RK_PD4 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm1_tx0_pins: spdifm1-tx0-pins {
+ rockchip,pins =
+ <1 RK_PD5 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm1_tx1_pins: spdifm1-tx1-pins {
+ rockchip,pins =
+ <1 RK_PD6 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm2_rx0_pins: spdifm2-rx0-pins {
+ rockchip,pins =
+ <2 RK_PD6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm2_tx0_pins: spdifm2-tx0-pins {
+ rockchip,pins =
+ <2 RK_PD7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm2_tx1_pins: spdifm2-tx1-pins {
+ rockchip,pins =
+ <2 RK_PD5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm3_rx0_pins: spdifm3-rx0-pins {
+ rockchip,pins =
+ <3 RK_PB4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm3_tx0_pins: spdifm3-tx0-pins {
+ rockchip,pins =
+ <3 RK_PB5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm3_tx1_pins: spdifm3-tx1-pins {
+ rockchip,pins =
+ <3 RK_PB6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm4_rx0_pins: spdifm4-rx0-pins {
+ rockchip,pins =
+ <4 RK_PA0 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm4_tx0_pins: spdifm4-tx0-pins {
+ rockchip,pins =
+ <4 RK_PA1 6 &pcfg_pull_none>;
+ };
+ };
+
+ spdif_rx0 {
+ /omit-if-no-ref/
+ spdif_rx0_rx0_pins: spdif-rx0-rx0-pins {
+ rockchip,pins =
+ <2 RK_PB7 7 &pcfg_pull_none>;
+ };
+ };
+
+ spdif_rx1 {
+ /omit-if-no-ref/
+ spdif_rx1_rx1_pins: spdif-rx1-rx1-pins {
+ rockchip,pins =
+ <1 RK_PD6 7 &pcfg_pull_none>;
+ };
+ };
+
+ spi0 {
+ /omit-if-no-ref/
+ spi0m0_pins: spi0m0-pins {
+ rockchip,pins =
+ <0 RK_PC7 10 &pcfg_pull_none>,
+ <0 RK_PD1 10 &pcfg_pull_none>,
+ <0 RK_PD0 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m0_csn0_pins: spi0m0-csn0-pins {
+ rockchip,pins =
+ <0 RK_PC6 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m0_csn1_pins: spi0m0-csn1-pins {
+ rockchip,pins =
+ <0 RK_PC3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_pins: spi0m1-pins {
+ rockchip,pins =
+ <2 RK_PA5 10 &pcfg_pull_none>,
+ <2 RK_PA1 10 &pcfg_pull_none>,
+ <2 RK_PA0 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_csn0_pins: spi0m1-csn0-pins {
+ rockchip,pins =
+ <2 RK_PA4 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_csn1_pins: spi0m1-csn1-pins {
+ rockchip,pins =
+ <2 RK_PA2 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m2_pins: spi0m2-pins {
+ rockchip,pins =
+ <1 RK_PA7 10 &pcfg_pull_none>,
+ <1 RK_PA6 10 &pcfg_pull_none>,
+ <1 RK_PA5 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m2_csn0_pins: spi0m2-csn0-pins {
+ rockchip,pins =
+ <1 RK_PA4 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m2_csn1_pins: spi0m2-csn1-pins {
+ rockchip,pins =
+ <1 RK_PB2 10 &pcfg_pull_none>;
+ };
+ };
+
+ spi1 {
+ /omit-if-no-ref/
+ spi1m0_pins: spi1m0-pins {
+ rockchip,pins =
+ <1 RK_PB4 10 &pcfg_pull_none>,
+ <1 RK_PB6 10 &pcfg_pull_none>,
+ <1 RK_PB5 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m0_csn0_pins: spi1m0-csn0-pins {
+ rockchip,pins =
+ <1 RK_PB7 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m0_csn1_pins: spi1m0-csn1-pins {
+ rockchip,pins =
+ <1 RK_PC0 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m1_pins: spi1m1-pins {
+ rockchip,pins =
+ <2 RK_PD3 10 &pcfg_pull_none>,
+ <2 RK_PD1 10 &pcfg_pull_none>,
+ <2 RK_PD0 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m1_csn0_pins: spi1m1-csn0-pins {
+ rockchip,pins =
+ <2 RK_PD2 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m1_csn1_pins: spi1m1-csn1-pins {
+ rockchip,pins =
+ <2 RK_PC7 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m2_pins: spi1m2-pins {
+ rockchip,pins =
+ <3 RK_PC7 10 &pcfg_pull_none>,
+ <3 RK_PC5 10 &pcfg_pull_none>,
+ <3 RK_PC6 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m2_csn0_pins: spi1m2-csn0-pins {
+ rockchip,pins =
+ <3 RK_PD0 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m2_csn1_pins: spi1m2-csn1-pins {
+ rockchip,pins =
+ <4 RK_PA0 10 &pcfg_pull_none>;
+ };
+ };
+
+ spi2 {
+ /omit-if-no-ref/
+ spi2m0_pins: spi2m0-pins {
+ rockchip,pins =
+ <0 RK_PB2 10 &pcfg_pull_none>,
+ <0 RK_PB1 10 &pcfg_pull_none>,
+ <0 RK_PB3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m0_csn0_pins: spi2m0-csn0-pins {
+ rockchip,pins =
+ <0 RK_PB0 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m0_csn1_pins: spi2m0-csn1-pins {
+ rockchip,pins =
+ <0 RK_PA7 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_pins: spi2m1-pins {
+ rockchip,pins =
+ <1 RK_PD5 10 &pcfg_pull_none>,
+ <1 RK_PC5 10 &pcfg_pull_none>,
+ <1 RK_PC4 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_csn0_pins: spi2m1-csn0-pins {
+ rockchip,pins =
+ <1 RK_PC6 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_csn1_pins: spi2m1-csn1-pins {
+ rockchip,pins =
+ <1 RK_PC7 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m2_pins: spi2m2-pins {
+ rockchip,pins =
+ <3 RK_PA4 10 &pcfg_pull_none>,
+ <3 RK_PC1 10 &pcfg_pull_none>,
+ <3 RK_PB0 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m2_csn0_pins: spi2m2-csn0-pins {
+ rockchip,pins =
+ <3 RK_PC4 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m2_csn1_pins: spi2m2-csn1-pins {
+ rockchip,pins =
+ <3 RK_PA5 10 &pcfg_pull_none>;
+ };
+ };
+
+ spi3 {
+ /omit-if-no-ref/
+ spi3m0_pins: spi3m0-pins {
+ rockchip,pins =
+ <2 RK_PD4 10 &pcfg_pull_none>,
+ <2 RK_PD6 10 &pcfg_pull_none>,
+ <2 RK_PD5 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m0_csn0_pins: spi3m0-csn0-pins {
+ rockchip,pins =
+ <2 RK_PD7 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m0_csn1_pins: spi3m0-csn1-pins {
+ rockchip,pins =
+ <2 RK_PC6 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_pins: spi3m1-pins {
+ rockchip,pins =
+ <3 RK_PD4 10 &pcfg_pull_none>,
+ <3 RK_PD5 10 &pcfg_pull_none>,
+ <3 RK_PD6 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_csn0_pins: spi3m1-csn0-pins {
+ rockchip,pins =
+ <3 RK_PB6 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_csn1_pins: spi3m1-csn1-pins {
+ rockchip,pins =
+ <3 RK_PD3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m2_pins: spi3m2-pins {
+ rockchip,pins =
+ <2 RK_PB5 10 &pcfg_pull_none>,
+ <2 RK_PB4 10 &pcfg_pull_none>,
+ <2 RK_PB2 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m2_csn0_pins: spi3m2-csn0-pins {
+ rockchip,pins =
+ <2 RK_PB1 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m2_csn1_pins: spi3m2-csn1-pins {
+ rockchip,pins =
+ <2 RK_PC1 11 &pcfg_pull_none>;
+ };
+ };
+
+ spi4 {
+ /omit-if-no-ref/
+ spi4m0_pins: spi4m0-pins {
+ rockchip,pins =
+ <4 RK_PB7 10 &pcfg_pull_none>,
+ <4 RK_PB6 10 &pcfg_pull_none>,
+ <4 RK_PB5 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi4m0_csn0_pins: spi4m0-csn0-pins {
+ rockchip,pins =
+ <4 RK_PB4 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi4m0_csn1_pins: spi4m0-csn1-pins {
+ rockchip,pins =
+ <4 RK_PB0 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi4m1_pins: spi4m1-pins {
+ rockchip,pins =
+ <3 RK_PD1 10 &pcfg_pull_none>,
+ <3 RK_PC2 10 &pcfg_pull_none>,
+ <3 RK_PC3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi4m1_csn0_pins: spi4m1-csn0-pins {
+ rockchip,pins =
+ <3 RK_PB1 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi4m1_csn1_pins: spi4m1-csn1-pins {
+ rockchip,pins =
+ <3 RK_PD2 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi4m2_pins: spi4m2-pins {
+ rockchip,pins =
+ <2 RK_PB6 10 &pcfg_pull_none>,
+ <2 RK_PC0 10 &pcfg_pull_none>,
+ <2 RK_PB7 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi4m2_csn0_pins: spi4m2-csn0-pins {
+ rockchip,pins =
+ <2 RK_PC1 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi4m2_csn1_pins: spi4m2-csn1-pins {
+ rockchip,pins =
+ <2 RK_PB3 10 &pcfg_pull_none>;
+ };
+ };
+
+ tsadc {
+ /omit-if-no-ref/
+ tsadcm0_pins: tsadcm0-pins {
+ rockchip,pins =
+ <0 RK_PA1 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ tsadcm1_pins: tsadcm1-pins {
+ rockchip,pins =
+ <0 RK_PA3 10 &pcfg_pull_none>;
+ };
+ };
+
+ tsadc_ctrl {
+ /omit-if-no-ref/
+ tsadc_ctrl_pins: tsadc-ctrl-pins {
+ rockchip,pins =
+ <0 RK_PA1 10 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ /omit-if-no-ref/
+ uart0m0_xfer_pins: uart0m0-xfer-pins {
+ rockchip,pins =
+ <0 RK_PD5 9 &pcfg_pull_up>,
+ <0 RK_PD4 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart0m1_xfer_pins: uart0m1-xfer-pins {
+ rockchip,pins =
+ <2 RK_PA0 9 &pcfg_pull_up>,
+ <2 RK_PA1 9 &pcfg_pull_up>;
+ };
+ };
+
+ uart1 {
+ /omit-if-no-ref/
+ uart1m0_xfer_pins: uart1m0-xfer-pins {
+ rockchip,pins =
+ <0 RK_PC0 9 &pcfg_pull_up>,
+ <0 RK_PB7 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m0_ctsn_pins: uart1m0-ctsn-pins {
+ rockchip,pins =
+ <0 RK_PD2 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m0_rtsn_pins: uart1m0-rtsn-pins {
+ rockchip,pins =
+ <0 RK_PD3 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_xfer_pins: uart1m1-xfer-pins {
+ rockchip,pins =
+ <2 RK_PD3 9 &pcfg_pull_up>,
+ <2 RK_PD2 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_ctsn_pins: uart1m1-ctsn-pins {
+ rockchip,pins =
+ <2 RK_PD0 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_rtsn_pins: uart1m1-rtsn-pins {
+ rockchip,pins =
+ <2 RK_PD1 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m2_xfer_pins: uart1m2-xfer-pins {
+ rockchip,pins =
+ <3 RK_PA6 9 &pcfg_pull_up>,
+ <3 RK_PA7 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m2_ctsn_pins: uart1m2-ctsn-pins {
+ rockchip,pins =
+ <3 RK_PA4 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m2_rtsn_pins: uart1m2-rtsn-pins {
+ rockchip,pins =
+ <3 RK_PA5 9 &pcfg_pull_none>;
+ };
+ };
+
+ uart2 {
+ /omit-if-no-ref/
+ uart2m0_xfer_pins: uart2m0-xfer-pins {
+ rockchip,pins =
+ <1 RK_PC7 9 &pcfg_pull_up>,
+ <1 RK_PC6 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m0_ctsn_pins: uart2m0-ctsn-pins {
+ rockchip,pins =
+ <1 RK_PC5 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart2m0_rtsn_pins: uart2m0-rtsn-pins {
+ rockchip,pins =
+ <1 RK_PC4 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart2m1_xfer_pins: uart2m1-xfer-pins {
+ rockchip,pins =
+ <2 RK_PB4 9 &pcfg_pull_up>,
+ <2 RK_PB5 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m1_ctsn_pins: uart2m1-ctsn-pins {
+ rockchip,pins =
+ <2 RK_PB7 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart2m1_rtsn_pins: uart2m1-rtsn-pins {
+ rockchip,pins =
+ <2 RK_PB6 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart2m2_xfer_pins: uart2m2-xfer-pins {
+ rockchip,pins =
+ <3 RK_PB7 9 &pcfg_pull_up>,
+ <3 RK_PC0 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m2_ctsn_pins: uart2m2-ctsn-pins {
+ rockchip,pins =
+ <3 RK_PD3 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart2m2_rtsn_pins: uart2m2-rtsn-pins {
+ rockchip,pins =
+ <3 RK_PD2 9 &pcfg_pull_none>;
+ };
+ };
+
+ uart3 {
+ /omit-if-no-ref/
+ uart3m0_xfer_pins: uart3m0-xfer-pins {
+ rockchip,pins =
+ <2 RK_PD5 9 &pcfg_pull_up>,
+ <2 RK_PD4 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3m0_ctsn_pins: uart3m0-ctsn-pins {
+ rockchip,pins =
+ <2 RK_PD6 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart3m0_rtsn_pins: uart3m0-rtsn-pins {
+ rockchip,pins =
+ <2 RK_PD7 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart3m1_xfer_pins: uart3m1-xfer-pins {
+ rockchip,pins =
+ <3 RK_PB2 9 &pcfg_pull_up>,
+ <3 RK_PB3 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3m1_ctsn_pins: uart3m1-ctsn-pins {
+ rockchip,pins =
+ <3 RK_PB5 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart3m1_rtsn_pins: uart3m1-rtsn-pins {
+ rockchip,pins =
+ <3 RK_PB4 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart3m2_xfer_pins: uart3m2-xfer-pins {
+ rockchip,pins =
+ <1 RK_PC1 9 &pcfg_pull_up>,
+ <1 RK_PC0 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3m2_ctsn_pins: uart3m2-ctsn-pins {
+ rockchip,pins =
+ <1 RK_PB6 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart3m2_rtsn_pins: uart3m2-rtsn-pins {
+ rockchip,pins =
+ <1 RK_PB7 9 &pcfg_pull_none>;
+ };
+ };
+
+ uart4 {
+ /omit-if-no-ref/
+ uart4m0_xfer_pins: uart4m0-xfer-pins {
+ rockchip,pins =
+ <3 RK_PC1 9 &pcfg_pull_up>,
+ <3 RK_PC4 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart4m0_ctsn_pins: uart4m0-ctsn-pins {
+ rockchip,pins =
+ <3 RK_PC3 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart4m0_rtsn_pins: uart4m0-rtsn-pins {
+ rockchip,pins =
+ <3 RK_PC2 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart4m1_xfer_pins: uart4m1-xfer-pins {
+ rockchip,pins =
+ <1 RK_PC5 9 &pcfg_pull_up>,
+ <1 RK_PC4 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart4m1_ctsn_pins: uart4m1-ctsn-pins {
+ rockchip,pins =
+ <1 RK_PC3 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart4m1_rtsn_pins: uart4m1-rtsn-pins {
+ rockchip,pins =
+ <1 RK_PC2 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart4m2_xfer_pins: uart4m2-xfer-pins {
+ rockchip,pins =
+ <0 RK_PB5 9 &pcfg_pull_up>,
+ <0 RK_PB4 9 &pcfg_pull_up>;
+ };
+ };
+
+ uart5 {
+ /omit-if-no-ref/
+ uart5m0_xfer_pins: uart5m0-xfer-pins {
+ rockchip,pins =
+ <3 RK_PD4 9 &pcfg_pull_up>,
+ <3 RK_PD5 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart5m0_ctsn_pins: uart5m0-ctsn-pins {
+ rockchip,pins =
+ <3 RK_PD6 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m0_rtsn_pins: uart5m0-rtsn-pins {
+ rockchip,pins =
+ <3 RK_PD7 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m1_xfer_pins: uart5m1-xfer-pins {
+ rockchip,pins =
+ <2 RK_PC2 9 &pcfg_pull_up>,
+ <2 RK_PC3 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart5m1_ctsn_pins: uart5m1-ctsn-pins {
+ rockchip,pins =
+ <2 RK_PC1 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m1_rtsn_pins: uart5m1-rtsn-pins {
+ rockchip,pins =
+ <2 RK_PC0 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m2_xfer_pins: uart5m2-xfer-pins {
+ rockchip,pins =
+ <2 RK_PA4 9 &pcfg_pull_up>,
+ <2 RK_PA5 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart5m2_ctsn_pins: uart5m2-ctsn-pins {
+ rockchip,pins =
+ <2 RK_PA3 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m2_rtsn_pins: uart5m2-rtsn-pins {
+ rockchip,pins =
+ <2 RK_PA2 9 &pcfg_pull_none>;
+ };
+ };
+
+ uart6 {
+ /omit-if-no-ref/
+ uart6m0_xfer_pins: uart6m0-xfer-pins {
+ rockchip,pins =
+ <2 RK_PB0 9 &pcfg_pull_up>,
+ <2 RK_PB1 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart6m0_ctsn_pins: uart6m0-ctsn-pins {
+ rockchip,pins =
+ <2 RK_PB3 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart6m0_rtsn_pins: uart6m0-rtsn-pins {
+ rockchip,pins =
+ <2 RK_PB2 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart6m1_xfer_pins: uart6m1-xfer-pins {
+ rockchip,pins =
+ <4 RK_PB1 9 &pcfg_pull_up>,
+ <4 RK_PB0 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart6m1_ctsn_pins: uart6m1-ctsn-pins {
+ rockchip,pins =
+ <4 RK_PB3 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart6m1_rtsn_pins: uart6m1-rtsn-pins {
+ rockchip,pins =
+ <4 RK_PB2 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart6m2_xfer_pins: uart6m2-xfer-pins {
+ rockchip,pins =
+ <1 RK_PB3 9 &pcfg_pull_up>,
+ <1 RK_PB0 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart6m2_ctsn_pins: uart6m2-ctsn-pins {
+ rockchip,pins =
+ <1 RK_PA5 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart6m2_rtsn_pins: uart6m2-rtsn-pins {
+ rockchip,pins =
+ <1 RK_PA4 9 &pcfg_pull_none>;
+ };
+ };
+
+ uart7 {
+ /omit-if-no-ref/
+ uart7m0_xfer_pins: uart7m0-xfer-pins {
+ rockchip,pins =
+ <1 RK_PD1 9 &pcfg_pull_up>,
+ <1 RK_PD0 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart7m0_ctsn_pins: uart7m0-ctsn-pins {
+ rockchip,pins =
+ <1 RK_PD5 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart7m0_rtsn_pins: uart7m0-rtsn-pins {
+ rockchip,pins =
+ <1 RK_PD4 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart7m1_xfer_pins: uart7m1-xfer-pins {
+ rockchip,pins =
+ <1 RK_PA3 9 &pcfg_pull_up>,
+ <1 RK_PA2 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart7m1_ctsn_pins: uart7m1-ctsn-pins {
+ rockchip,pins =
+ <1 RK_PA1 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart7m1_rtsn_pins: uart7m1-rtsn-pins {
+ rockchip,pins =
+ <1 RK_PA0 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart7m2_xfer_pins: uart7m2-xfer-pins {
+ rockchip,pins =
+ <2 RK_PA0 14 &pcfg_pull_up>,
+ <2 RK_PA1 14 &pcfg_pull_up>;
+ };
+ };
+
+ uart8 {
+ /omit-if-no-ref/
+ uart8m0_xfer_pins: uart8m0-xfer-pins {
+ rockchip,pins =
+ <3 RK_PC5 9 &pcfg_pull_up>,
+ <3 RK_PC6 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart8m0_ctsn_pins: uart8m0-ctsn-pins {
+ rockchip,pins =
+ <3 RK_PD0 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart8m0_rtsn_pins: uart8m0-rtsn-pins {
+ rockchip,pins =
+ <3 RK_PC7 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart8m1_xfer_pins: uart8m1-xfer-pins {
+ rockchip,pins =
+ <0 RK_PC2 9 &pcfg_pull_up>,
+ <0 RK_PC1 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart8m1_ctsn_pins: uart8m1-ctsn-pins {
+ rockchip,pins =
+ <0 RK_PC7 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart8m1_rtsn_pins: uart8m1-rtsn-pins {
+ rockchip,pins =
+ <0 RK_PC6 9 &pcfg_pull_none>;
+ };
+ };
+
+ uart9 {
+ /omit-if-no-ref/
+ uart9m0_xfer_pins: uart9m0-xfer-pins {
+ rockchip,pins =
+ <4 RK_PB5 9 &pcfg_pull_up>,
+ <4 RK_PB4 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart9m0_ctsn_pins: uart9m0-ctsn-pins {
+ rockchip,pins =
+ <4 RK_PB6 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart9m0_rtsn_pins: uart9m0-rtsn-pins {
+ rockchip,pins =
+ <4 RK_PB7 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart9m1_xfer_pins: uart9m1-xfer-pins {
+ rockchip,pins =
+ <4 RK_PA1 9 &pcfg_pull_up>,
+ <4 RK_PA0 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart9m1_ctsn_pins: uart9m1-ctsn-pins {
+ rockchip,pins =
+ <3 RK_PB7 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart9m1_rtsn_pins: uart9m1-rtsn-pins {
+ rockchip,pins =
+ <3 RK_PC0 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart9m2_xfer_pins: uart9m2-xfer-pins {
+ rockchip,pins =
+ <2 RK_PB3 9 &pcfg_pull_up>,
+ <2 RK_PB2 9 &pcfg_pull_up>;
+ };
+ };
+
+ uart10 {
+ /omit-if-no-ref/
+ uart10m0_xfer_pins: uart10m0-xfer-pins {
+ rockchip,pins =
+ <3 RK_PB0 9 &pcfg_pull_up>,
+ <3 RK_PB1 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart10m0_ctsn_pins: uart10m0-ctsn-pins {
+ rockchip,pins =
+ <3 RK_PA6 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart10m0_rtsn_pins: uart10m0-rtsn-pins {
+ rockchip,pins =
+ <3 RK_PA7 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart10m1_xfer_pins: uart10m1-xfer-pins {
+ rockchip,pins =
+ <2 RK_PC5 9 &pcfg_pull_up>,
+ <2 RK_PC4 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart10m1_ctsn_pins: uart10m1-ctsn-pins {
+ rockchip,pins =
+ <2 RK_PC6 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart10m1_rtsn_pins: uart10m1-rtsn-pins {
+ rockchip,pins =
+ <2 RK_PC7 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart10m2_xfer_pins: uart10m2-xfer-pins {
+ rockchip,pins =
+ <0 RK_PC5 9 &pcfg_pull_up>,
+ <0 RK_PC4 9 &pcfg_pull_up>;
+ };
+ };
+
+ uart11 {
+ /omit-if-no-ref/
+ uart11m0_xfer_pins: uart11m0-xfer-pins {
+ rockchip,pins =
+ <0 RK_PD1 9 &pcfg_pull_up>,
+ <0 RK_PD0 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart11m1_xfer_pins: uart11m1-xfer-pins {
+ rockchip,pins =
+ <2 RK_PB7 9 &pcfg_pull_up>,
+ <2 RK_PB6 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart11m2_xfer_pins: uart11m2-xfer-pins {
+ rockchip,pins =
+ <2 RK_PC7 12 &pcfg_pull_up>,
+ <2 RK_PC6 12 &pcfg_pull_up>;
+ };
+ };
+
+ ufs {
+ /omit-if-no-ref/
+ ufs_refclk_pins: ufs-refclk-pins {
+ rockchip,pins =
+ <4 RK_PC1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ ufs_rst_pins: ufs-rst-pins {
+ rockchip,pins =
+ <4 RK_PC0 1 &pcfg_pull_none>;
+ };
+ };
+
+ vi_cif {
+ /omit-if-no-ref/
+ vi_cif_pins: vi-cif-pins {
+ rockchip,pins =
+ <2 RK_PD7 6 &pcfg_pull_none>,
+ <2 RK_PD6 6 &pcfg_pull_none>,
+ <2 RK_PD3 6 &pcfg_pull_none>,
+ <2 RK_PD2 6 &pcfg_pull_none>,
+ <2 RK_PD1 6 &pcfg_pull_none>,
+ <2 RK_PD0 6 &pcfg_pull_none>,
+ <2 RK_PC7 6 &pcfg_pull_none>,
+ <2 RK_PC6 6 &pcfg_pull_none>,
+ <2 RK_PC5 6 &pcfg_pull_none>,
+ <2 RK_PC4 6 &pcfg_pull_none>,
+ <2 RK_PC1 2 &pcfg_pull_none>,
+ <2 RK_PC0 2 &pcfg_pull_none>,
+ <2 RK_PB7 2 &pcfg_pull_none>,
+ <2 RK_PB6 2 &pcfg_pull_none>,
+ <2 RK_PB5 2 &pcfg_pull_none>,
+ <2 RK_PB4 2 &pcfg_pull_none>,
+ <2 RK_PB3 2 &pcfg_pull_none>,
+ <2 RK_PB2 2 &pcfg_pull_none>,
+ <2 RK_PD4 6 &pcfg_pull_none>,
+ <2 RK_PD5 6 &pcfg_pull_none>;
+ };
+ };
+
+ vo_ebc {
+ /omit-if-no-ref/
+ vo_ebc_pins: vo-ebc-pins {
+ rockchip,pins =
+ <4 RK_PA0 4 &pcfg_pull_none>,
+ <4 RK_PA1 4 &pcfg_pull_none>,
+ <3 RK_PD5 4 &pcfg_pull_none>,
+ <3 RK_PA6 4 &pcfg_pull_none>,
+ <3 RK_PA5 4 &pcfg_pull_none>,
+ <3 RK_PB3 4 &pcfg_pull_none>,
+ <3 RK_PB2 4 &pcfg_pull_none>,
+ <3 RK_PB1 4 &pcfg_pull_none>,
+ <3 RK_PB0 4 &pcfg_pull_none>,
+ <3 RK_PD6 4 &pcfg_pull_none>,
+ <3 RK_PD3 4 &pcfg_pull_none>,
+ <3 RK_PD2 4 &pcfg_pull_none>,
+ <3 RK_PD1 4 &pcfg_pull_none>,
+ <3 RK_PD0 4 &pcfg_pull_none>,
+ <3 RK_PC7 4 &pcfg_pull_none>,
+ <3 RK_PC6 4 &pcfg_pull_none>,
+ <3 RK_PC5 4 &pcfg_pull_none>,
+ <3 RK_PC4 4 &pcfg_pull_none>,
+ <3 RK_PC3 4 &pcfg_pull_none>,
+ <3 RK_PC2 4 &pcfg_pull_none>,
+ <3 RK_PC1 4 &pcfg_pull_none>,
+ <3 RK_PC0 4 &pcfg_pull_none>,
+ <3 RK_PB7 4 &pcfg_pull_none>,
+ <3 RK_PB6 4 &pcfg_pull_none>,
+ <3 RK_PB5 4 &pcfg_pull_none>,
+ <3 RK_PB4 4 &pcfg_pull_none>,
+ <4 RK_PB0 5 &pcfg_pull_none>,
+ <4 RK_PB1 5 &pcfg_pull_none>,
+ <4 RK_PB2 5 &pcfg_pull_none>,
+ <4 RK_PB3 5 &pcfg_pull_none>,
+ <4 RK_PB4 5 &pcfg_pull_none>,
+ <4 RK_PB5 5 &pcfg_pull_none>,
+ <4 RK_PB6 5 &pcfg_pull_none>,
+ <4 RK_PB7 5 &pcfg_pull_none>,
+ <3 RK_PD4 4 &pcfg_pull_none>,
+ <3 RK_PD7 4 &pcfg_pull_none>,
+ <3 RK_PA4 4 &pcfg_pull_none>,
+ <3 RK_PA7 4 &pcfg_pull_none>;
+ };
+ };
+
+ vo_lcdc {
+ /omit-if-no-ref/
+ vo_lcdc_pins: vo-lcdc-pins {
+ rockchip,pins =
+ <3 RK_PD7 3 &pcfg_pull_none>,
+ <3 RK_PD3 3 &pcfg_pull_none>,
+ <3 RK_PD2 3 &pcfg_pull_none>,
+ <3 RK_PD1 3 &pcfg_pull_none>,
+ <3 RK_PD0 3 &pcfg_pull_none>,
+ <3 RK_PC7 3 &pcfg_pull_none>,
+ <3 RK_PC6 3 &pcfg_pull_none>,
+ <3 RK_PC5 3 &pcfg_pull_none>,
+ <3 RK_PC4 3 &pcfg_pull_none>,
+ <3 RK_PC3 3 &pcfg_pull_none>,
+ <3 RK_PC2 3 &pcfg_pull_none>,
+ <3 RK_PC1 3 &pcfg_pull_none>,
+ <3 RK_PC0 3 &pcfg_pull_none>,
+ <3 RK_PB7 3 &pcfg_pull_none>,
+ <3 RK_PB6 3 &pcfg_pull_none>,
+ <3 RK_PB5 3 &pcfg_pull_none>,
+ <3 RK_PB4 3 &pcfg_pull_none>,
+ <3 RK_PB3 3 &pcfg_pull_none>,
+ <3 RK_PB2 3 &pcfg_pull_none>,
+ <3 RK_PB1 3 &pcfg_pull_none>,
+ <3 RK_PB0 3 &pcfg_pull_none>,
+ <3 RK_PA7 3 &pcfg_pull_none>,
+ <3 RK_PA6 3 &pcfg_pull_none>,
+ <3 RK_PA5 3 &pcfg_pull_none>,
+ <3 RK_PA4 3 &pcfg_pull_none>,
+ <3 RK_PD4 3 &pcfg_pull_none>,
+ <3 RK_PD5 3 &pcfg_pull_none>,
+ <3 RK_PD6 3 &pcfg_pull_none>;
+ };
+ };
+
+ vo_post {
+ /omit-if-no-ref/
+ vo_post_pins: vo-post-pins {
+ rockchip,pins =
+ <4 RK_PA1 3 &pcfg_pull_none>;
+ };
+ };
+
+ vp0_sync {
+ /omit-if-no-ref/
+ vp0_sync_pins: vp0-sync-pins {
+ rockchip,pins =
+ <4 RK_PB5 3 &pcfg_pull_none>;
+ };
+ };
+
+ vp1_sync {
+ /omit-if-no-ref/
+ vp1_sync_pins: vp1-sync-pins {
+ rockchip,pins =
+ <4 RK_PB6 3 &pcfg_pull_none>;
+ };
+ };
+};
+
+&pinctrl {
+ ebc {
+ /omit-if-no-ref/
+ ebc_24bit_pins: ebc-24bit-pins {
+ rockchip,pins =
+ <3 RK_PD5 4 &pcfg_pull_none>,
+ <3 RK_PA6 4 &pcfg_pull_none>,
+ <3 RK_PA5 4 &pcfg_pull_none>,
+ <3 RK_PB3 4 &pcfg_pull_none>,
+ <3 RK_PD6 4 &pcfg_pull_none>,
+ <3 RK_PD3 4 &pcfg_pull_none>,
+ <3 RK_PD2 4 &pcfg_pull_none>,
+ <3 RK_PD1 4 &pcfg_pull_none>,
+ <3 RK_PD0 4 &pcfg_pull_none>,
+ <3 RK_PC7 4 &pcfg_pull_none>,
+ <3 RK_PC6 4 &pcfg_pull_none>,
+ <3 RK_PC5 4 &pcfg_pull_none>,
+ <3 RK_PC4 4 &pcfg_pull_none>,
+ <3 RK_PC3 4 &pcfg_pull_none>,
+ <3 RK_PC2 4 &pcfg_pull_none>,
+ <3 RK_PC1 4 &pcfg_pull_none>,
+ <3 RK_PC0 4 &pcfg_pull_none>,
+ <3 RK_PB7 4 &pcfg_pull_none>,
+ <3 RK_PB6 4 &pcfg_pull_none>,
+ <3 RK_PB5 4 &pcfg_pull_none>,
+ <3 RK_PB4 4 &pcfg_pull_none>,
+ <4 RK_PB0 5 &pcfg_pull_none>,
+ <4 RK_PB1 5 &pcfg_pull_none>,
+ <4 RK_PB2 5 &pcfg_pull_none>,
+ <4 RK_PB3 5 &pcfg_pull_none>,
+ <4 RK_PB4 5 &pcfg_pull_none>,
+ <4 RK_PB5 5 &pcfg_pull_none>,
+ <4 RK_PB6 5 &pcfg_pull_none>,
+ <4 RK_PB7 5 &pcfg_pull_none>,
+ <3 RK_PD4 4 &pcfg_pull_none>,
+ <3 RK_PD7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ ebc_16bit_pins: ebc-16bit-pins {
+ rockchip,pins =
+ <3 RK_PD5 4 &pcfg_pull_none>,
+ <3 RK_PA6 4 &pcfg_pull_none>,
+ <3 RK_PA5 4 &pcfg_pull_none>,
+ <3 RK_PB3 4 &pcfg_pull_none>,
+ <3 RK_PD6 4 &pcfg_pull_none>,
+ <3 RK_PD3 4 &pcfg_pull_none>,
+ <3 RK_PD2 4 &pcfg_pull_none>,
+ <3 RK_PD1 4 &pcfg_pull_none>,
+ <3 RK_PD0 4 &pcfg_pull_none>,
+ <3 RK_PC7 4 &pcfg_pull_none>,
+ <3 RK_PC6 4 &pcfg_pull_none>,
+ <3 RK_PC5 4 &pcfg_pull_none>,
+ <3 RK_PC4 4 &pcfg_pull_none>,
+ <3 RK_PC3 4 &pcfg_pull_none>,
+ <3 RK_PC2 4 &pcfg_pull_none>,
+ <3 RK_PC1 4 &pcfg_pull_none>,
+ <3 RK_PC0 4 &pcfg_pull_none>,
+ <3 RK_PB7 4 &pcfg_pull_none>,
+ <3 RK_PB6 4 &pcfg_pull_none>,
+ <3 RK_PB5 4 &pcfg_pull_none>,
+ <3 RK_PB4 4 &pcfg_pull_none>,
+ <3 RK_PD4 4 &pcfg_pull_none>,
+ <3 RK_PD7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ ebc_8bit_pins: ebc-8bit-pins {
+ rockchip,pins =
+ <3 RK_PD5 4 &pcfg_pull_none>,
+ <3 RK_PA6 4 &pcfg_pull_none>,
+ <3 RK_PA5 4 &pcfg_pull_none>,
+ <3 RK_PB3 4 &pcfg_pull_none>,
+ <3 RK_PD6 4 &pcfg_pull_none>,
+ <3 RK_PD3 4 &pcfg_pull_none>,
+ <3 RK_PD2 4 &pcfg_pull_none>,
+ <3 RK_PD1 4 &pcfg_pull_none>,
+ <3 RK_PD0 4 &pcfg_pull_none>,
+ <3 RK_PC7 4 &pcfg_pull_none>,
+ <3 RK_PC6 4 &pcfg_pull_none>,
+ <3 RK_PC5 4 &pcfg_pull_none>,
+ <3 RK_PC4 4 &pcfg_pull_none>,
+ <3 RK_PD4 4 &pcfg_pull_none>,
+ <3 RK_PD7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ ebc_extern: ebc-extern {
+ rockchip,pins =
+ <3 RK_PB2 4 &pcfg_pull_none>,
+ <3 RK_PB1 4 &pcfg_pull_none>,
+ <3 RK_PB0 4 &pcfg_pull_none>,
+ <3 RK_PA4 4 &pcfg_pull_none>,
+ <3 RK_PA7 4 &pcfg_pull_none>;
+ };
+ };
+
+ pdm {
+ /omit-if-no-ref/
+ pdmm0_clk0_idle: pdmm0-clk0-idle {
+ rockchip,pins =
+ <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_clk1_idle: pdmm0-clk1-idle {
+ rockchip,pins =
+ <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_clk0_idle: pdmm1-clk0-idle {
+ rockchip,pins =
+ <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_clk1_idle: pdmm1-clk1-idle {
+ rockchip,pins =
+ <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm2_clk0_idle: pdmm1-clk0-idle {
+ rockchip,pins =
+ <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm2_clk1_idle: pdmm1-clk1-idle {
+ rockchip,pins =
+ <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm3_clk0_idle: pdmm1-clk0-idle {
+ rockchip,pins =
+ <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm3_clk1_idle: pdmm1-clk1-idle {
+ rockchip,pins =
+ <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm4_clk0_idle: pdmm1-clk0-idle {
+ rockchip,pins =
+ <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm4_clk1_idle: pdmm1-clk1-idle {
+ rockchip,pins =
+ <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ ufs {
+ /omit-if-no-ref/
+ ufs_rstgpio: ufs-rstgpio {
+ rockchip,pins =
+ <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ vo {
+ /omit-if-no-ref/
+ bt1120_pins: bt1120-pins {
+ rockchip,pins =
+ <3 RK_PD7 3 &pcfg_pull_none>,
+ <3 RK_PD0 3 &pcfg_pull_none>,
+ <3 RK_PC7 3 &pcfg_pull_none>,
+ <3 RK_PC6 3 &pcfg_pull_none>,
+ <3 RK_PC5 3 &pcfg_pull_none>,
+ <3 RK_PC4 3 &pcfg_pull_none>,
+ <3 RK_PC1 3 &pcfg_pull_none>,
+ <3 RK_PC0 3 &pcfg_pull_none>,
+ <3 RK_PB7 3 &pcfg_pull_none>,
+ <3 RK_PB6 3 &pcfg_pull_none>,
+ <3 RK_PB5 3 &pcfg_pull_none>,
+ <3 RK_PB4 3 &pcfg_pull_none>,
+ <3 RK_PB0 3 &pcfg_pull_none>,
+ <3 RK_PA7 3 &pcfg_pull_none>,
+ <3 RK_PA6 3 &pcfg_pull_none>,
+ <3 RK_PA5 3 &pcfg_pull_none>,
+ <3 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ bt656_pins: bt656-pins {
+ rockchip,pins =
+ <3 RK_PD7 3 &pcfg_pull_none>,
+ <3 RK_PD0 3 &pcfg_pull_none>,
+ <3 RK_PC7 3 &pcfg_pull_none>,
+ <3 RK_PC6 3 &pcfg_pull_none>,
+ <3 RK_PC5 3 &pcfg_pull_none>,
+ <3 RK_PC4 3 &pcfg_pull_none>,
+ <3 RK_PC1 3 &pcfg_pull_none>,
+ <3 RK_PC0 3 &pcfg_pull_none>,
+ <3 RK_PB7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgb3x8_pins_m0: rgb3x8-pins-m0 {
+ rockchip,pins =
+ <3 RK_PD7 3 &pcfg_pull_none>,
+ <3 RK_PD0 3 &pcfg_pull_none>,
+ <3 RK_PC7 3 &pcfg_pull_none>,
+ <3 RK_PC6 3 &pcfg_pull_none>,
+ <3 RK_PC5 3 &pcfg_pull_none>,
+ <3 RK_PC4 3 &pcfg_pull_none>,
+ <3 RK_PC1 3 &pcfg_pull_none>,
+ <3 RK_PC0 3 &pcfg_pull_none>,
+ <3 RK_PB7 3 &pcfg_pull_none>,
+ <3 RK_PD4 3 &pcfg_pull_none>,
+ <3 RK_PD5 3 &pcfg_pull_none>,
+ <3 RK_PD6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgb3x8_pins_m1: rgb3x8-pins-m1 {
+ rockchip,pins =
+ <3 RK_PB6 3 &pcfg_pull_none>,
+ <3 RK_PB5 3 &pcfg_pull_none>,
+ <3 RK_PB4 3 &pcfg_pull_none>,
+ <3 RK_PB0 3 &pcfg_pull_none>,
+ <3 RK_PA7 3 &pcfg_pull_none>,
+ <3 RK_PA6 3 &pcfg_pull_none>,
+ <3 RK_PA5 3 &pcfg_pull_none>,
+ <3 RK_PA4 3 &pcfg_pull_none>,
+ <3 RK_PD4 3 &pcfg_pull_none>,
+ <3 RK_PD5 3 &pcfg_pull_none>,
+ <3 RK_PD6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgb565_pins: rgb565-pins {
+ rockchip,pins =
+ <3 RK_PD7 3 &pcfg_pull_none>,
+ <3 RK_PD0 3 &pcfg_pull_none>,
+ <3 RK_PC7 3 &pcfg_pull_none>,
+ <3 RK_PC6 3 &pcfg_pull_none>,
+ <3 RK_PC5 3 &pcfg_pull_none>,
+ <3 RK_PC4 3 &pcfg_pull_none>,
+ <3 RK_PC1 3 &pcfg_pull_none>,
+ <3 RK_PC0 3 &pcfg_pull_none>,
+ <3 RK_PB7 3 &pcfg_pull_none>,
+ <3 RK_PB6 3 &pcfg_pull_none>,
+ <3 RK_PB5 3 &pcfg_pull_none>,
+ <3 RK_PB4 3 &pcfg_pull_none>,
+ <3 RK_PB0 3 &pcfg_pull_none>,
+ <3 RK_PA7 3 &pcfg_pull_none>,
+ <3 RK_PA6 3 &pcfg_pull_none>,
+ <3 RK_PA5 3 &pcfg_pull_none>,
+ <3 RK_PA4 3 &pcfg_pull_none>,
+ <3 RK_PD4 3 &pcfg_pull_none>,
+ <3 RK_PD5 3 &pcfg_pull_none>,
+ <3 RK_PD6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgb666_pins: rgb666-pins {
+ rockchip,pins =
+ <3 RK_PD7 3 &pcfg_pull_none>,
+ <3 RK_PD1 3 &pcfg_pull_none>,
+ <3 RK_PD0 3 &pcfg_pull_none>,
+ <3 RK_PC7 3 &pcfg_pull_none>,
+ <3 RK_PC6 3 &pcfg_pull_none>,
+ <3 RK_PC5 3 &pcfg_pull_none>,
+ <3 RK_PC4 3 &pcfg_pull_none>,
+ <3 RK_PC1 3 &pcfg_pull_none>,
+ <3 RK_PC0 3 &pcfg_pull_none>,
+ <3 RK_PB7 3 &pcfg_pull_none>,
+ <3 RK_PB6 3 &pcfg_pull_none>,
+ <3 RK_PB5 3 &pcfg_pull_none>,
+ <3 RK_PB4 3 &pcfg_pull_none>,
+ <3 RK_PB1 3 &pcfg_pull_none>,
+ <3 RK_PB0 3 &pcfg_pull_none>,
+ <3 RK_PA7 3 &pcfg_pull_none>,
+ <3 RK_PA6 3 &pcfg_pull_none>,
+ <3 RK_PA5 3 &pcfg_pull_none>,
+ <3 RK_PA4 3 &pcfg_pull_none>,
+ <3 RK_PD4 3 &pcfg_pull_none>,
+ <3 RK_PD5 3 &pcfg_pull_none>,
+ <3 RK_PD6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgb888_pins: rgb888-pins {
+ rockchip,pins =
+ <3 RK_PD7 3 &pcfg_pull_none>,
+ <3 RK_PD3 3 &pcfg_pull_none>,
+ <3 RK_PD2 3 &pcfg_pull_none>,
+ <3 RK_PD1 3 &pcfg_pull_none>,
+ <3 RK_PD0 3 &pcfg_pull_none>,
+ <3 RK_PC7 3 &pcfg_pull_none>,
+ <3 RK_PC6 3 &pcfg_pull_none>,
+ <3 RK_PC5 3 &pcfg_pull_none>,
+ <3 RK_PC4 3 &pcfg_pull_none>,
+ <3 RK_PC3 3 &pcfg_pull_none>,
+ <3 RK_PC2 3 &pcfg_pull_none>,
+ <3 RK_PC1 3 &pcfg_pull_none>,
+ <3 RK_PC0 3 &pcfg_pull_none>,
+ <3 RK_PB7 3 &pcfg_pull_none>,
+ <3 RK_PB6 3 &pcfg_pull_none>,
+ <3 RK_PB5 3 &pcfg_pull_none>,
+ <3 RK_PB4 3 &pcfg_pull_none>,
+ <3 RK_PB3 3 &pcfg_pull_none>,
+ <3 RK_PB2 3 &pcfg_pull_none>,
+ <3 RK_PB1 3 &pcfg_pull_none>,
+ <3 RK_PB0 3 &pcfg_pull_none>,
+ <3 RK_PA7 3 &pcfg_pull_none>,
+ <3 RK_PA6 3 &pcfg_pull_none>,
+ <3 RK_PA5 3 &pcfg_pull_none>,
+ <3 RK_PA4 3 &pcfg_pull_none>,
+ <3 RK_PD4 3 &pcfg_pull_none>,
+ <3 RK_PD5 3 &pcfg_pull_none>,
+ <3 RK_PD6 3 &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3572.dtsi b/arch/arm64/boot/dts/rockchip/rk3572.dtsi
new file mode 100644
index 000000000000..db415b6da843
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3572.dtsi
@@ -0,0 +1,1325 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/clock/rockchip,rk3572-cru.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rockchip,rk3572-power-controller.h>
+#include <dt-bindings/reset/rockchip,rk3572-cru.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "rockchip,rk3572";
+ #address-cells = <2>;
+ interrupt-parent = <&gic>;
+ #size-cells = <2>;
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ serial8 = &uart8;
+ serial9 = &uart9;
+ serial10 = &uart10;
+ serial11 = &uart11;
+ };
+
+ spll: clock-spll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <702000000>;
+ clock-output-names = "spll";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu_l0>;
+ };
+
+ core1 {
+ cpu = <&cpu_l1>;
+ };
+
+ core2 {
+ cpu = <&cpu_l2>;
+ };
+
+ core3 {
+ cpu = <&cpu_l3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu_l4>;
+ };
+
+ core1 {
+ cpu = <&cpu_l5>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&cpu_b0>;
+ };
+
+ core1 {
+ cpu = <&cpu_b1>;
+ };
+ };
+ };
+
+ cpu_l0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ capacity-dmips-mhz = <669>;
+ clocks = <&scmi_clk ARMCLK_L0>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <0x8000>;
+ enable-method = "psci";
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x8000>;
+ next-level-cache = <&l2_cache_l0>;
+ };
+
+ cpu_l1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ capacity-dmips-mhz = <669>;
+ clocks = <&scmi_clk ARMCLK_L0>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <0x8000>;
+ enable-method = "psci";
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x8000>;
+ next-level-cache = <&l2_cache_l0>;
+ };
+
+ cpu_l2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ capacity-dmips-mhz = <669>;
+ clocks = <&scmi_clk ARMCLK_L0>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <0x8000>;
+ enable-method = "psci";
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x8000>;
+ next-level-cache = <&l2_cache_l0>;
+ };
+
+ cpu_l3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ capacity-dmips-mhz = <669>;
+ clocks = <&scmi_clk ARMCLK_L0>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <0x8000>;
+ enable-method = "psci";
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x8000>;
+ next-level-cache = <&l2_cache_l0>;
+ };
+
+ cpu_l4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x100>;
+ capacity-dmips-mhz = <563>;
+ clocks = <&scmi_clk ARMCLK_L1>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <0x8000>;
+ enable-method = "psci";
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x8000>;
+ next-level-cache = <&l2_cache_l1>;
+ };
+
+ cpu_l5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x101>;
+ capacity-dmips-mhz = <563>;
+ clocks = <&scmi_clk ARMCLK_L1>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <0x8000>;
+ enable-method = "psci";
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x8000>;
+ next-level-cache = <&l2_cache_l1>;
+ };
+
+ cpu_b0: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x200>;
+ capacity-dmips-mhz = <1024>;
+ clocks = <&scmi_clk ARMCLK_B>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <0x8000>;
+ enable-method = "psci";
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+ next-level-cache = <&l2_cache_b>;
+ };
+
+ cpu_b1: cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x201>;
+ capacity-dmips-mhz = <1024>;
+ clocks = <&scmi_clk ARMCLK_B>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ d-cache-size = <0x8000>;
+ enable-method = "psci";
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ i-cache-size = <0x10000>;
+ next-level-cache = <&l2_cache_b>;
+ };
+
+ l2_cache_l0: l2-cache-cluster0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-size = <0x80000>;
+ cache-unified;
+ };
+
+ l2_cache_l1: l2-cache-cluster1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <256>;
+ cache-size = <0x40000>;
+ cache-unified;
+ };
+
+ l2_cache_b: l2-cache-cluster2 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ cache-size = <0x80000>;
+ cache-unified;
+ };
+ };
+
+ firmware {
+ scmi: scmi {
+ compatible = "arm,scmi-smc";
+ #address-cells = <1>;
+ shmem = <&scmi_shmem>;
+ #size-cells = <0>;
+ arm,smc-id = <0x82000010>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3572-pinctrl";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ rockchip,grf = <&ioc_grf>;
+
+ gpio0: gpio@26300000 {
+ compatible = "rockchip,rk3572-gpio-bank";
+ reg = <0x0 0x26300000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpio1: gpio@2b200000 {
+ compatible = "rockchip,rk3572-gpio-bank";
+ reg = <0x0 0x2b200000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpio2: gpio@2b300000 {
+ compatible = "rockchip,rk3572-gpio-bank";
+ reg = <0x0 0x2b300000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpio3: gpio@2b400000 {
+ compatible = "rockchip,rk3572-gpio-bank";
+ reg = <0x0 0x2b400000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpio4: gpio@2b500000 {
+ compatible = "rockchip,rk3572-gpio-bank";
+ reg = <0x0 0x2b500000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ usb_drd0_dwc3: usb@24000000 {
+ compatible = "rockchip,rk3572-dwc3";
+ reg = <0x0 0x24000000 0x0 0x400000>;
+ clocks = <&cru CLK_REF_USB3OTG0>,
+ <&cru CLK_SUSPEND_USB3OTG0>,
+ <&cru ACLK_USB3OTG0>;
+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
+ dma-coherent;
+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
+ phy_type = "utmi_wide";
+ phys = <&u2phy0_otg>, <&combphy0_psu PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ power-domains = <&power RK3572_PD_PHP>;
+ resets = <&cru SRST_ARESETN_USB3OTG0>;
+ rockchip,grf = <&php_grf 0x14>;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis_enblslpm_quirk;
+ snps,parkmode-disable-hs-quirk;
+ snps,parkmode-disable-ss-quirk;
+
+ status = "disabled";
+ };
+
+ usb_drd1_dwc3: usb@24400000 {
+ compatible = "rockchip,rk3572-dwc3";
+ reg = <0x0 0x24400000 0x0 0x400000>;
+ clocks = <&cru CLK_REF_USB3OTG1>,
+ <&cru CLK_SUSPEND_USB3OTG1>,
+ <&cru ACLK_USB3OTG1>;
+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
+ dma-coherent;
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
+ phy_type = "utmi_wide";
+ phys = <&u2phy1_otg>, <&combphy1_psu PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ power-domains = <&power RK3572_PD_PHP>;
+ resets = <&cru SRST_ARESETN_USB3OTG1>;
+ rockchip,grf = <&php_grf 0x34>;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis_enblslpm_quirk;
+ snps,parkmode-disable-hs-quirk;
+ snps,parkmode-disable-ss-quirk;
+
+ status = "disabled";
+ };
+
+ sys_grf: syscon@26010000 {
+ compatible = "rockchip,rk3572-sys-grf", "syscon";
+ reg = <0x0 0x26010000 0x0 0x2000>;
+ };
+
+ php_grf: syscon@26026000 {
+ compatible = "rockchip,rk3572-php-grf", "syscon";
+ reg = <0x0 0x26026000 0x0 0x1000>;
+ clocks = <&cru PCLK_PHPSUBSYS_ROOT>;
+ };
+
+ nvm0_grf: syscon@2602a000 {
+ compatible = "rockchip,rk3572-nvm0-grf", "syscon";
+ reg = <0x0 0x2602a000 0x0 0x1000>;
+ clocks = <&cru PCLK_NVM0_ROOT>;
+ };
+
+ pmu0_grf: syscon@26040000 {
+ compatible = "rockchip,rk3572-pmu0-grf", "syscon";
+ reg = <0x0 0x26040000 0x0 0x1000>;
+ };
+
+ pipe_phy0_grf: syscon@2604e000 {
+ compatible = "rockchip,rk3572-pipe-phy-grf", "syscon";
+ reg = <0x0 0x2604e000 0x0 0x2000>;
+ clocks = <&cru PCLK_PHPSUBSYS_ROOT>;
+ };
+
+ pipe_phy1_grf: syscon@26050000 {
+ compatible = "rockchip,rk3572-pipe-phy-grf", "syscon";
+ reg = <0x0 0x26050000 0x0 0x2000>;
+ clocks = <&cru PCLK_PHPSUBSYS_ROOT>;
+ };
+
+ usb2phy_grf: syscon@26054000 {
+ compatible = "rockchip,rk3572-usb2phy-grf",
+ "syscon",
+ "simple-mfd";
+ reg = <0x0 0x26054000 0x0 0x4000>;
+ #address-cells = <1>;
+ clocks = <&cru PCLK_PHPSUBSYS_ROOT>;
+ #size-cells = <1>;
+
+ u2phy0: usb2phy@0 {
+ compatible = "rockchip,rk3572-usb2phy";
+ reg = <0x0 0x10>;
+ #clock-cells = <0>;
+ clock-output-names = "usb480m_phy0";
+ clocks = <&xin24m>, <&cru PCLK_PHPSUBSYS_ROOT>;
+ clock-names = "phyclk", "pclk";
+ resets = <&cru SRST_RESETN_OTGPHY_0>,
+ <&cru SRST_PRESETN_USBPHY_GRF_0>;
+ reset-names = "phy", "apb";
+
+ status = "disabled";
+
+ u2phy0_otg: otg-port {
+ interrupts = <GIC_SPI 288
+ IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 289
+ IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 290
+ IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid",
+ "otg-id",
+ "linestate";
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
+ u2phy1: usb2phy@2000 {
+ compatible = "rockchip,rk3572-usb2phy";
+ reg = <0x2000 0x10>;
+ #clock-cells = <0>;
+ clock-output-names = "usb480m_phy1";
+ clocks = <&xin24m>, <&cru PCLK_PHPSUBSYS_ROOT>;
+ clock-names = "phyclk", "pclk";
+ resets = <&cru SRST_RESETN_OTGPHY_1>,
+ <&cru SRST_PRESETN_USBPHY_GRF_1>;
+ reset-names = "phy", "apb";
+
+ status = "disabled";
+
+ u2phy1_otg: otg-port {
+ interrupts = <GIC_SPI 293
+ IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294
+ IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295
+ IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid",
+ "otg-id",
+ "linestate";
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+ };
+
+ ioc_grf: syscon@26072000 {
+ compatible = "rockchip,rk3572-ioc-grf", "syscon";
+ reg = <0x0 0x26072000 0x0 0x16000>;
+ };
+
+ cru: clock-controller@26090000 {
+ compatible = "rockchip,rk3572-cru";
+ reg = <0x0 0x26090000 0x0 0x60000>;
+ assigned-clock-rates = <1000000000>,
+ <18432000>,
+ <96000000>,
+ <128000000>;
+ assigned-clocks = <&cru PLL_CPLL>,
+ <&cru CLK_UART_FRAC_0>,
+ <&cru CLK_UART_FRAC_1>,
+ <&cru CLK_UART_FRAC_2>;
+ #clock-cells = <1>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
+ #reset-cells = <1>;
+ rockchip,grf = <&pmu0_grf>;
+ };
+
+ uart1: serial@26500000 {
+ compatible = "rockchip,rk3572-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x26500000 0x0 0x100>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart1m0_xfer_pins>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ i2c0: i2c@26520000 {
+ compatible = "rockchip,rk3572-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0x26520000 0x0 0x1000>;
+ #address-cells = <1>;
+ clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c0m0_xfer_pins>;
+ pinctrl-names = "default";
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ pmu: power-management@26550000 {
+ compatible = "rockchip,rk3572-pmu",
+ "syscon",
+ "simple-mfd";
+ reg = <0x0 0x26550000 0x0 0x1000>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3572-power-controller";
+ #address-cells = <1>;
+ #power-domain-cells = <1>;
+ #size-cells = <0>;
+ rockchip,grf = <&sys_grf>;
+
+ power-domain@3 {
+ reg = <RK3572_PD_NVM1>;
+ pm_qos = <&qos_fspi1>, <&qos_sdmmc0>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@5 {
+ reg = <RK3572_PD_PHP>;
+ pm_qos = <&qos_gmac0>,
+ <&qos_pcie0>,
+ <&qos_pcie1>,
+ <&qos_sata0>,
+ <&qos_sata1>,
+ <&qos_ufshc>,
+ <&qos_usb0>,
+ <&qos_usb1>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@c {
+ reg = <RK3572_PD_VOP>;
+ #address-cells = <1>;
+ pm_qos = <&qos_vop_m0>, <&qos_vop_m1ro>;
+ #power-domain-cells = <0>;
+ #size-cells = <0>;
+
+ power-domain@2 {
+ reg = <RK3572_PD_NVM0>;
+ pm_qos = <&qos_emmc>,
+ <&qos_fspi0>,
+ <&qos_gmac1>,
+ <&qos_sdmmc1>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ };
+
+ qos_fspi1: qos@27802000 {
+ compatible = "rockchip,rk3572-qos", "syscon";
+ reg = <0x0 0x27802000 0x0 0x20>;
+ };
+
+ qos_sdmmc0: qos@27802080 {
+ compatible = "rockchip,rk3572-qos", "syscon";
+ reg = <0x0 0x27802080 0x0 0x20>;
+ };
+
+ qos_emmc: qos@27809000 {
+ compatible = "rockchip,rk3572-qos", "syscon";
+ reg = <0x0 0x27809000 0x0 0x20>;
+ };
+
+ qos_fspi0: qos@27809080 {
+ compatible = "rockchip,rk3572-qos", "syscon";
+ reg = <0x0 0x27809080 0x0 0x20>;
+ };
+
+ qos_gmac1: qos@27809100 {
+ compatible = "rockchip,rk3572-qos", "syscon";
+ reg = <0x0 0x27809100 0x0 0x20>;
+ };
+
+ qos_sdmmc1: qos@27809180 {
+ compatible = "rockchip,rk3572-qos", "syscon";
+ reg = <0x0 0x27809180 0x0 0x20>;
+ };
+
+ qos_gmac0: qos@2780a000 {
+ compatible = "rockchip,rk3572-qos", "syscon";
+ reg = <0x0 0x2780a000 0x0 0x20>;
+ };
+
+ qos_pcie0: qos@2780a080 {
+ compatible = "rockchip,rk3572-qos", "syscon";
+ reg = <0x0 0x2780a080 0x0 0x20>;
+ };
+
+ qos_pcie1: qos@2780a100 {
+ compatible = "rockchip,rk3572-qos", "syscon";
+ reg = <0x0 0x2780a100 0x0 0x20>;
+ };
+
+ qos_sata0: qos@2780a180 {
+ compatible = "rockchip,rk3572-qos", "syscon";
+ reg = <0x0 0x2780a180 0x0 0x20>;
+ };
+
+ qos_sata1: qos@2780a200 {
+ compatible = "rockchip,rk3572-qos", "syscon";
+ reg = <0x0 0x2780a200 0x0 0x20>;
+ };
+
+ qos_ufshc: qos@2780a280 {
+ compatible = "rockchip,rk3572-qos", "syscon";
+ reg = <0x0 0x2780a280 0x0 0x20>;
+ };
+
+ qos_usb0: qos@2780a300 {
+ compatible = "rockchip,rk3572-qos", "syscon";
+ reg = <0x0 0x2780a300 0x0 0x20>;
+ };
+
+ qos_usb1: qos@2780a380 {
+ compatible = "rockchip,rk3572-qos", "syscon";
+ reg = <0x0 0x2780a380 0x0 0x20>;
+ };
+
+ qos_vop_m0: qos@27812800 {
+ compatible = "rockchip,rk3572-qos", "syscon";
+ reg = <0x0 0x27812800 0x0 0x20>;
+ };
+
+ qos_vop_m1ro: qos@27812880 {
+ compatible = "rockchip,rk3572-qos", "syscon";
+ reg = <0x0 0x27812880 0x0 0x20>;
+ };
+
+ gmac0: ethernet@29d20000 {
+ compatible = "rockchip,rk3572-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0x29d20000 0x0 0x10000>;
+ clocks = <&cru CLK_GMAC0_125M_SRC>,
+ <&cru CLK_GMAC0_RMII_CRU>,
+ <&cru PCLK_GMAC0>,
+ <&cru ACLK_GMAC0>,
+ <&cru CLK_GMAC0_PTP_REF_SRC>;
+ clock-names = "stmmaceth", "clk_mac_ref",
+ "pclk_mac", "aclk_mac",
+ "ptp_ref";
+ dma-coherent;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ power-domains = <&power RK3572_PD_PHP>;
+ resets = <&cru SRST_ARESETN_GMAC0>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&php_grf>;
+ rockchip,php-grf = <&ioc_grf>;
+ snps,axi-config = <&gmac0_stmmac_axi_setup>;
+ snps,mixed-burst;
+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
+ snps,tso;
+
+ status = "disabled";
+
+ mdio0: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ gmac0_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+
+ queue0 {
+ };
+ };
+
+ gmac0_stmmac_axi_setup: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <8>;
+ snps,wr_osr_lmt = <4>;
+ };
+
+ gmac0_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+
+ queue0 {
+ };
+ };
+ };
+
+ sdhci: mmc@2a010000 {
+ compatible = "rockchip,rk3572-dwcmshc",
+ "rockchip,rk3576-dwcmshc";
+ reg = <0x0 0x2a010000 0x0 0x10000>;
+ assigned-clock-rates = <200000000>,
+ <24000000>,
+ <200000000>;
+ assigned-clocks = <&cru BCLK_EMMC>,
+ <&cru TCLK_EMMC>,
+ <&cru CCLK_SRC_EMMC>;
+ clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
+ <&cru TCLK_EMMC>;
+ clock-names = "core", "bus", "axi", "block", "timer";
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <200000000>;
+ power-domains = <&power RK3572_PD_NVM0>;
+ resets = <&cru SRST_CRESETN_EMMC>,
+ <&cru SRST_HRESETN_EMMC>,
+ <&cru SRST_ARESETN_EMMC>,
+ <&cru SRST_BRESETN_EMMC>,
+ <&cru SRST_TRESETN_EMMC>;
+ reset-names = "core", "bus", "axi", "block", "timer";
+ supports-cqe;
+
+ status = "disabled";
+ };
+
+ gmac1: ethernet@2a040000 {
+ compatible = "rockchip,rk3572-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0x2a040000 0x0 0x10000>;
+ clocks = <&cru CLK_GMAC1_125M_SRC>,
+ <&cru CLK_GMAC1_RMII_CRU>,
+ <&cru PCLK_GMAC1>,
+ <&cru ACLK_GMAC1>,
+ <&cru CLK_GMAC1_PTP_REF>;
+ clock-names = "stmmaceth", "clk_mac_ref",
+ "pclk_mac", "aclk_mac",
+ "ptp_ref";
+ dma-coherent;
+ interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ power-domains = <&power RK3572_PD_NVM0>;
+ resets = <&cru SRST_ARESETN_GMAC1>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&nvm0_grf>;
+ rockchip,php-grf = <&ioc_grf>;
+ snps,axi-config = <&gmac1_stmmac_axi_setup>;
+ snps,mixed-burst;
+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
+ snps,tso;
+
+ status = "disabled";
+
+ mdio1: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ gmac1_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+
+ queue0 {
+ };
+ };
+
+ gmac1_stmmac_axi_setup: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <8>;
+ snps,wr_osr_lmt = <4>;
+ };
+
+ gmac1_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+
+ queue0 {
+ };
+ };
+ };
+
+ sdmmc0: mmc@2a090000 {
+ compatible = "rockchip,rk3572-dw-mshc",
+ "rockchip,rk3576-dw-mshc";
+ reg = <0x0 0x2a090000 0x0 0x4000>;
+ clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <200000000>;
+ pinctrl-0 = <&sdmmc0m0_bus4_pins &sdmmc0m0_clk_pins
+ &sdmmc0m0_cmd_pins &sdmmc0m0_det_pins>;
+ pinctrl-names = "default";
+ power-domains = <&power RK3572_PD_NVM1>;
+ resets = <&cru SRST_HRESETN_SDMMC0>;
+ reset-names = "reset";
+
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@2a601000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0x2a601000 0 0x1000>,
+ <0x0 0x2a602000 0 0x2000>,
+ <0x0 0x2a604000 0 0x2000>,
+ <0x0 0x2a606000 0 0x2000>;
+ #address-cells = <0>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ i2c1: i2c@2c030000 {
+ compatible = "rockchip,rk3572-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0x2c030000 0x0 0x1000>;
+ #address-cells = <1>;
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c1m0_xfer_pins>;
+ pinctrl-names = "default";
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c2: i2c@2c040000 {
+ compatible = "rockchip,rk3572-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0x2c040000 0x0 0x1000>;
+ #address-cells = <1>;
+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c2m0_xfer_pins>;
+ pinctrl-names = "default";
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c3: i2c@2c050000 {
+ compatible = "rockchip,rk3572-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0x2c050000 0x0 0x1000>;
+ #address-cells = <1>;
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c3m0_xfer_pins>;
+ pinctrl-names = "default";
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c4: i2c@2c060000 {
+ compatible = "rockchip,rk3572-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0x2c060000 0x0 0x1000>;
+ #address-cells = <1>;
+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c4m0_xfer_pins>;
+ pinctrl-names = "default";
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c5: i2c@2c070000 {
+ compatible = "rockchip,rk3572-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0x2c070000 0x0 0x1000>;
+ #address-cells = <1>;
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c5m0_xfer_pins>;
+ pinctrl-names = "default";
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c6: i2c@2c080000 {
+ compatible = "rockchip,rk3572-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0x2c080000 0x0 0x1000>;
+ #address-cells = <1>;
+ clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c6m0_xfer_pins>;
+ pinctrl-names = "default";
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c7: i2c@2c090000 {
+ compatible = "rockchip,rk3572-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0x2c090000 0x0 0x1000>;
+ #address-cells = <1>;
+ clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c7m0_xfer_pins>;
+ pinctrl-names = "default";
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c8: i2c@2c0a0000 {
+ compatible = "rockchip,rk3572-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0x2c0a0000 0x0 0x1000>;
+ #address-cells = <1>;
+ clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c8m0_xfer_pins>;
+ pinctrl-names = "default";
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c9: i2c@2c0b0000 {
+ compatible = "rockchip,rk3572-i2c",
+ "rockchip,rk3399-i2c";
+ reg = <0x0 0x2c0b0000 0x0 0x1000>;
+ #address-cells = <1>;
+ clocks = <&cru CLK_I2C9>, <&cru PCLK_I2C9>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&i2c9m0_xfer_pins>;
+ pinctrl-names = "default";
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ wdt: watchdog@2c0c0000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x2c0c0000 0x0 0x100>;
+ clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
+ clock-names = "tclk", "pclk";
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+ };
+
+ uart0: serial@2c130000 {
+ compatible = "rockchip,rk3572-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2c130000 0x0 0x100>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart0m0_xfer_pins>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@2c140000 {
+ compatible = "rockchip,rk3572-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2c140000 0x0 0x100>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart2m0_xfer_pins>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart3: serial@2c150000 {
+ compatible = "rockchip,rk3572-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2c150000 0x0 0x100>;
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart3m0_xfer_pins>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart4: serial@2c160000 {
+ compatible = "rockchip,rk3572-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2c160000 0x0 0x100>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart4m0_xfer_pins>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart5: serial@2c170000 {
+ compatible = "rockchip,rk3572-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2c170000 0x0 0x100>;
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart5m0_xfer_pins>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart6: serial@2c180000 {
+ compatible = "rockchip,rk3572-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2c180000 0x0 0x100>;
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart6m0_xfer_pins>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart7: serial@2c190000 {
+ compatible = "rockchip,rk3572-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2c190000 0x0 0x100>;
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart7m0_xfer_pins>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart8: serial@2c1a0000 {
+ compatible = "rockchip,rk3572-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2c1a0000 0x0 0x100>;
+ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart8m0_xfer_pins>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart9: serial@2c1b0000 {
+ compatible = "rockchip,rk3572-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2c1b0000 0x0 0x100>;
+ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart9m0_xfer_pins>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart10: serial@2c1c0000 {
+ compatible = "rockchip,rk3572-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2c1c0000 0x0 0x100>;
+ clocks = <&cru SCLK_UART10>, <&cru PCLK_UART10>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart10m0_xfer_pins>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart11: serial@2c1d0000 {
+ compatible = "rockchip,rk3572-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2c1d0000 0x0 0x100>;
+ clocks = <&cru SCLK_UART11>, <&cru PCLK_UART11>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart11m0_xfer_pins>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ tsadc: tsadc@2c1f0000 {
+ compatible = "rockchip,rk3572-tsadc";
+ reg = <0x0 0x2c1f0000 0x0 0x1000>;
+ assigned-clock-rates = <2000000>;
+ assigned-clocks = <&cru CLK_TSADC>;
+ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
+ clock-names = "tsadc", "apb_pclk";
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cru SRST_PRESETN_TSADC>,
+ <&cru SRST_RESETN_TSADC>;
+ reset-names = "tsadc-apb", "tsadc";
+ #thermal-sensor-cells = <1>;
+ rockchip,hw-tshut-mode = <0>; /* 0: CRU, 1: GPIO */
+ rockchip,hw-tshut-polarity = <0>; /* 0: LOW, 1: HIGH */
+ rockchip,hw-tshut-temp = <120000>;
+
+ status = "disabled";
+ };
+
+ combphy0_psu: phy@2c410000 {
+ compatible = "rockchip,rk3572-naneng-combphy";
+ reg = <0x0 0x2c410000 0x0 0x100>;
+ assigned-clock-rates = <24000000>;
+ assigned-clocks = <&cru CLK_REF_PCIE0_INNER_PHY>;
+ clocks = <&cru CLK_REF_PCIE0_INNER_PHY>,
+ <&cru PCLK_PCIE2_COMBOPHY0>;
+ clock-names = "ref", "apb";
+ #phy-cells = <1>;
+ resets = <&cru SRST_RESETN_PCIE0_PIPE_PHY>;
+ reset-names = "phy";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
+
+ status = "disabled";
+ };
+
+ combphy1_psu: phy@2c420000 {
+ compatible = "rockchip,rk3572-naneng-combphy";
+ reg = <0x0 0x2c420000 0x0 0x100>;
+ assigned-clock-rates = <24000000>;
+ assigned-clocks = <&cru CLK_REF_PCIE1_INNER_PHY>;
+ clocks = <&cru CLK_REF_PCIE1_INNER_PHY>,
+ <&cru PCLK_PCIE2_COMBOPHY1>;
+ clock-names = "ref", "apb";
+ #phy-cells = <1>;
+ resets = <&cru SRST_RESETN_PCIE1_PIPE_PHY>;
+ reset-names = "phy";
+ rockchip,pipe-grf = <&php_grf>;
+ rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
+
+ status = "disabled";
+ };
+
+ sram: sram@4010f000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x4010f000 0x0 0x100>;
+ ranges = <0x0 0x0 0x4010f000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ scmi_shmem: scmi-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x100>;
+ };
+ };
+ };
+
+ thermal-zones {
+ big_core_thermal: big-core-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ thermal-sensors = <&tsadc 4>;
+
+ trips {
+ big-core-crit {
+ hysteresis = <2000>;
+ temperature = <115000>;
+ type = "critical";
+ };
+ };
+ };
+
+ center-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ thermal-sensors = <&tsadc 0>;
+
+ trips {
+ center-crit {
+ hysteresis = <2000>;
+ temperature = <115000>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddr-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ thermal-sensors = <&tsadc 2>;
+
+ trips {
+ ddr-crit {
+ hysteresis = <2000>;
+ temperature = <115000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu-npu-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ thermal-sensors = <&tsadc 1>;
+
+ trips {
+ gpu-npu-crit {
+ hysteresis = <2000>;
+ temperature = <115000>;
+ type = "critical";
+ };
+ };
+ };
+
+ little_core_thermal: little-core-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ thermal-sensors = <&tsadc 3>;
+
+ trips {
+ little-core-crit {
+ hysteresis = <2000>;
+ temperature = <115000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ xin24m: xin24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ };
+};
+
+#include "rk3572-pinctrl.dtsi"
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 27/27] arm64: dts: rockchip: Add initial support for Forlinx OK3572-C
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (25 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 26/27] arm64: dts: rockchip: Add RK3572 SoC Cunhao Lu via B4 Relay
@ 2026-10-21 16:11 ` Cunhao Lu via B4 Relay
2026-10-21 23:00 ` [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Shawn Lin
27 siblings, 0 replies; 32+ messages in thread
From: Cunhao Lu via B4 Relay @ 2026-10-21 16:11 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
From: Cunhao Lu <1579567540@qq.com>
Describe the OK3572-C carrier board and FET3572-C system-on-module.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../dts/rockchip/rk3572-forlinx-fet3572-c.dtsi | 369 +++++++++++++++++++++
.../boot/dts/rockchip/rk3572-forlinx-ok3572-c.dts | 286 ++++++++++++++++
3 files changed, 656 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index e7936a21c118..d028e9cccceb 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -168,6 +168,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3b.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-display-vz.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3572-forlinx-ok3572-c.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-100ask-dshanpi-a1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-anbernic-rg-vita-pro.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-cm5-io.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3572-forlinx-fet3572-c.dtsi b/arch/arm64/boot/dts/rockchip/rk3572-forlinx-fet3572-c.dtsi
new file mode 100644
index 000000000000..d9a662aef6ad
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3572-forlinx-fet3572-c.dtsi
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2025 Forlinx Embedded Tech. Co., Ltd
+ * Copyright (c) 2026 Cunhao Lu <1579567540@qq.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3572.dtsi"
+#include "rk3572-opp.dtsi"
+
+/ {
+ compatible = "forlinx,fet3572-c", "rockchip,rk3572";
+
+ vcc5v0_sys_s5: regulator-vcc5v0-sys-s5 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "vcc5v0_sys_s5";
+ };
+
+ vcc_ldo_s3: regulator-vcc-ldo-s3 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <2100000>;
+ regulator-min-microvolt = <2100000>;
+ regulator-name = "vcc_ldo_s3";
+ };
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big_s0>;
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l4 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ rk806: pmic@23 {
+ compatible = "rockchip,rk806";
+ reg = <0x23>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA6 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pmic_int>;
+ pinctrl-names = "default";
+ system-power-controller;
+ vcc1-supply = <&vcc5v0_sys_s5>;
+ vcc2-supply = <&vcc5v0_sys_s5>;
+ vcc3-supply = <&vcc5v0_sys_s5>;
+ vcc4-supply = <&vcc5v0_sys_s5>;
+ vcc5-supply = <&vcc5v0_sys_s5>;
+ vcc6-supply = <&vcc5v0_sys_s5>;
+ vcc7-supply = <&vcc5v0_sys_s5>;
+ vcc8-supply = <&vcc5v0_sys_s5>;
+ vcc9-supply = <&vcc5v0_sys_s5>;
+ vcc10-supply = <&vcc5v0_sys_s5>;
+ vcc11-supply = <&vcc_ldo_s3>;
+ vcc12-supply = <&vcc5v0_sys_s5>;
+ vcc13-supply = <&vcc_ldo_s3>;
+ vcc14-supply = <&vcc_ldo_s3>;
+ vcca-supply = <&vcc5v0_sys_s5>;
+
+ regulators {
+ vdd_cpu_lit_s0: dcdc-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-enable-ramp-delay = <400>;
+ regulator-max-microvolt = <950000>;
+ regulator-min-microvolt = <550000>;
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_npu_s0: dcdc-reg2 {
+ regulator-boot-on;
+ regulator-enable-ramp-delay = <400>;
+ regulator-max-microvolt = <950000>;
+ regulator-min-microvolt = <550000>;
+ regulator-name = "vdd_npu_s0";
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_big_s0: dcdc-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <950000>;
+ regulator-min-microvolt = <550000>;
+ regulator-name = "vdd_cpu_big_s0";
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "vcc_3v3_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vdd_gpu_s0: dcdc-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-enable-ramp-delay = <400>;
+ regulator-max-microvolt = <900000>;
+ regulator-min-microvolt = <550000>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-ramp-delay = <12500>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vddq_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_logic_s0: dcdc-reg7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <800000>;
+ regulator-min-microvolt = <550000>;
+ regulator-name = "vdd_logic_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: dcdc-reg8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vdd2_ddr_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <850000>;
+ regulator-min-microvolt = <750000>;
+ regulator-name = "vdd_ddr_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <750000>;
+ regulator-min-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdda_0v85_s0: nldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <850000>;
+ regulator-min-microvolt = <850000>;
+ regulator-name = "vdd_0v85_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_hdmi_s0: nldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <837500>;
+ regulator-min-microvolt = <837500>;
+ regulator-name = "vdda_hdmi_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_ddr_pll_s0: nldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <850000>;
+ regulator-min-microvolt = <850000>;
+ regulator-name = "vdda_ddr_pll_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v75_s0: nldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <750000>;
+ regulator-min-microvolt = <750000>;
+ regulator-name = "vdda_0v75_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: pldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vccio_1v8_s0: pldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vccio_1v8_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_1v2_s0: pldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microvolt = <1200000>;
+ regulator-name = "vdda_1v2_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd_s0: pldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "vcc3v3_sd_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vccio_sd_s0";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pldo6_s3: pldo-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "vcca1v8_pldo6_s3";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+ };
+ };
+};
+
+&pinctrl {
+ pmic {
+ pmic_int: pmic-int {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ no-sd;
+ no-sdio;
+ non-removable;
+ pinctrl-0 = <&emmc_rstnout_pins &emmc_bus8_pins &emmc_clk_pins
+ &emmc_cmd_pins &emmc_strb_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <&vcc_3v3_s3>;
+ vqmmc-supply = <&vcc_1v8_s3>;
+
+ status = "okay";
+};
+
+&tsadc {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3572-forlinx-ok3572-c.dts b/arch/arm64/boot/dts/rockchip/rk3572-forlinx-ok3572-c.dts
new file mode 100644
index 000000000000..754fbce00162
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3572-forlinx-ok3572-c.dts
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2025 Forlinx Embedded Tech. Co., Ltd
+ * Copyright (c) 2026 Cunhao Lu <1579567540@qq.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3572-forlinx-fet3572-c.dtsi"
+
+/ {
+ compatible = "forlinx,ok3572-c", "forlinx,fet3572-c", "rockchip,rk3572";
+ model = "Forlinx OK3572-C";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
+ };
+
+ chosen {
+ stdout-path = "serial0:1500000n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&work_led_gpio>;
+ pinctrl-names = "default";
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ vcc_usb_hub_1v2: regulator-usb-hub-1v2 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microvolt = <1200000>;
+ regulator-name = "vcc_usb_hub_1v2";
+ vin-supply = <&vcc5v0_sys_s5>;
+ };
+
+ vcc_usb_hub_3v3: regulator-usb-hub-3v3 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "vcc_usb_hub_3v3";
+ vin-supply = <&vcc5v0_sys_s5>;
+ };
+
+ vbus5v0_typec: regulator-vbus5v0-typec {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&usb_drd0_pwren>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "vbus5v0_typec";
+ vin-supply = <&vcc5v0_sys_s5>;
+ };
+
+ vcc5v0_usb3_host: regulator-vcc5v0-usb3-host {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ regulator-name = "vcc5v0_usb3_host";
+ vin-supply = <&vcc5v0_sys_s5>;
+ };
+};
+
+&combphy1_psu {
+ status = "okay";
+};
+
+&gmac0 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii0_phy>;
+ phy-mode = "rgmii-rxid"; /* Schematic adds a 2ns delay to RX_CLK */
+ phy-supply = <&vcc_3v3_s3>;
+ pinctrl-0 = <ð0_miim_pins ð0_tx_bus2_pins ð0_rx_bus2_pins
+ ð0_rgmii_clk_pins ð0_rgmii_bus_pins>;
+ pinctrl-names = "default";
+ tx_delay = <0x21>;
+
+ status = "okay";
+};
+
+&gmac1 {
+ clock_in_out = "output";
+ phy-handle = <&rgmii1_phy>;
+ phy-mode = "rgmii-rxid"; /* Schematic adds a 2ns delay to RX_CLK */
+ phy-supply = <&vcc_3v3_s3>;
+ pinctrl-0 = <ð1m0_miim_pins ð1m0_tx_bus2_pins ð1m0_rx_bus2_pins
+ ð1m0_rgmii_clk_pins ð1m0_rgmii_bus_pins>;
+ pinctrl-names = "default";
+ tx_delay = <0x20>;
+
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+
+ usb-typec@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&usbc0_int>;
+ pinctrl-names = "default";
+ vbus-supply = <&vbus5v0_typec>;
+
+ connector {
+ compatible = "usb-c-connector";
+ data-role = "dual";
+ label = "USB-C";
+ op-sink-microwatt = <1000000>;
+ power-role = "dual";
+ sink-pdos = <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
+ source-pdos =
+ <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ try-power-role = "sink";
+
+ port {
+ usbc0_role_sw: endpoint {
+ remote-endpoint =
+ <&usb_drd0_role_switch>;
+ };
+ };
+ };
+ };
+
+ gpio@23 {
+ compatible = "nxp,pcal6524";
+ reg = <0x23>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-0 = <&extio_int_gpio>;
+ pinctrl-names = "default";
+ vcc-supply = <&vcc_3v3_s3>;
+ };
+};
+
+&mdio0 {
+ rgmii0_phy: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&mdio1 {
+ rgmii1_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ extio {
+ extio_int_gpio: extio-int {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ work_led_gpio: work-led {
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ usb_drd0_pwren: usb-drd0-pwren {
+ rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usbc0_int: usbc0-int {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ max-frequency = <200000000>;
+ no-mmc;
+ no-sdio;
+ pinctrl-0 = <&sdmmc0m0_bus4_pins &sdmmc0m0_clk_pins &sdmmc0m0_cmd_pins
+ &sdmmc0m0_det_pins &sdmmc0_pwren_pins>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd_s0>;
+ vqmmc-supply = <&vccio_sd_s0>;
+
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+};
+
+&u2phy0_otg {
+ status = "okay";
+};
+
+&u2phy1 {
+ status = "okay";
+};
+
+&u2phy1_otg {
+ phy-supply = <&vcc5v0_usb3_host>;
+
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb_drd0_dwc3 {
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+ phys = <&u2phy0_otg>;
+ phy-names = "usb2-phy";
+ usb-role-switch;
+ snps,dis_u2_susphy_quirk;
+ snps,usb2-lpm-disable;
+
+ status = "okay";
+
+ port {
+ usb_drd0_role_switch: endpoint {
+ remote-endpoint = <&usbc0_role_sw>;
+ };
+ };
+};
+
+&usb_drd1_dwc3 {
+ #address-cells = <1>;
+ dr_mode = "host";
+ #size-cells = <0>;
+
+ status = "okay";
+
+ hub_2_0: hub@1 {
+ compatible = "usb4b4,6502", "usb4b4,6506";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;
+ vdd2-supply = <&vcc_usb_hub_3v3>;
+ vdd-supply = <&vcc_usb_hub_1v2>;
+ };
+
+ hub_3_0: hub@2 {
+ compatible = "usb4b4,6500", "usb4b4,6504";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;
+ vdd2-supply = <&vcc_usb_hub_3v3>;
+ vdd-supply = <&vcc_usb_hub_1v2>;
+ };
+};
+
+&wdt {
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 16/27] net: stmmac: dwmac-rk: Add RK3572 support
2026-10-21 16:11 ` [PATCH 16/27] net: stmmac: dwmac-rk: Add RK3572 support Cunhao Lu via B4 Relay
@ 2026-10-21 17:09 ` Andrew Lunn
0 siblings, 0 replies; 32+ messages in thread
From: Andrew Lunn @ 2026-10-21 17:09 UTC (permalink / raw)
To: 1579567540
Cc: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, mfd, linux-gpio,
netdev, linux-pm, linux-i2c, linux-serial, linux-mmc,
linux-stm32, linux-phy, linux-usb
On Thu, Oct 22, 2026 at 12:11:13AM +0800, Cunhao Lu via B4 Relay wrote:
> From: Cunhao Lu <1579567540@qq.com>
>
> Configure RGMII delays and clocks for both RK3572 GMAC controllers,
> using GMAC-specific GRF registers.
You need to split this patches per subsystem. Please send all
networking patches to netdev, once the merge window closes.
https://www.kernel.org/doc/html/latest/process/maintainer-netdev.html
Andrew
---
pw-bot: cr
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 14/27] dt-bindings: net: rockchip-dwmac: Add RK3572
2026-10-21 16:11 ` [PATCH 14/27] dt-bindings: net: rockchip-dwmac: Add RK3572 Cunhao Lu via B4 Relay
@ 2026-10-21 17:14 ` Andrew Lunn
0 siblings, 0 replies; 32+ messages in thread
From: Andrew Lunn @ 2026-10-21 17:14 UTC (permalink / raw)
To: 1579567540
Cc: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Lee Jones, Linus Walleij, Bartosz Golaszewski,
Richard Cochran, Ulf Hansson, Andi Shyti, Greg Kroah-Hartman,
Jiri Slaby, Jisheng Zhang, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, David Wu,
Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Maxime Chevallier, Maxime Coquelin, Alexandre Torgue, Vinod Koul,
Neil Armstrong, Manivannan Sadhasivam, Thinh Nguyen,
Jaehoon Chung, Shawn Lin, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, mfd, linux-gpio,
netdev, linux-pm, linux-i2c, linux-serial, linux-mmc,
linux-stm32, linux-phy, linux-usb
On Thu, Oct 22, 2026 at 12:11:11AM +0800, Cunhao Lu via B4 Relay wrote:
> From: Cunhao Lu <1579567540@qq.com>
>
> Add the RK3572 GMAC compatible using the snps,dwmac-4.20a fallback.
Since this is a new device, please don't allow tx_delay and rx_delay,
which should be considered deprecated, replaced by
rx-internal-delay-ps and tx-internal-delay-ps.
We have to keep tx_delay and rx_delay for older devices because of
backwards compatibility, but there is no reason new devices should use
them.
Andrew
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 07/27] clk: rockchip: Add RK3572 clock and reset support
2026-10-21 16:11 ` [PATCH 07/27] clk: rockchip: Add RK3572 clock and reset support Cunhao Lu via B4 Relay
@ 2026-10-21 22:26 ` Heiko Stübner
0 siblings, 0 replies; 32+ messages in thread
From: Heiko Stübner @ 2026-10-21 22:26 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Elaine Zhang,
Lee Jones, Linus Walleij, Bartosz Golaszewski, Richard Cochran,
Ulf Hansson, Andi Shyti, Greg Kroah-Hartman, Jiri Slaby,
Jisheng Zhang, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, David Wu, Rafael J. Wysocki,
Daniel Lezcano, Zhang Rui, Lukasz Luba, Maxime Chevallier,
Maxime Coquelin, Alexandre Torgue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Thinh Nguyen, Jaehoon Chung, Shawn Lin,
1579567540
Cc: Cunhao Lu, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
Hi,
Am Mittwoch, 21. Oktober 2026, 18:11:04 Mitteleuropäische Sommerzeit schrieb Cunhao Lu via B4 Relay:
> From: Cunhao Lu <1579567540@qq.com>
>
> CPU clocks are managed by SCMI. Keep BPLL and LPLL enabled for firmware
> consumers.
>
> Signed-off-by: Cunhao Lu <1579567540@qq.com>
[...]
> diff --git a/drivers/clk/rockchip/clk-rk3572.c b/drivers/clk/rockchip/clk-rk3572.c
> new file mode 100644
> index 000000000000..78fd35f5f27d
> --- /dev/null
> +++ b/drivers/clk/rockchip/clk-rk3572.c
> @@ -0,0 +1,1972 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
> + * Author: Elaine Zhang <zhangqing@rock-chips.com>
> + */
As you didn't write this driver on your own and even kept the original
author, please also credit the original author in the commit itself.
This can be done for example with something like
git commit --amend --author="Elaine Zhang <zhangqing@rock-chips.com>"
and in the commit also have both signed-offs-by, aka Elaine first
then yours below as the submitter, i.e. like
+++++++++++
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[document what changes you did inside the brackets]
Signed-off-by: Cunhao Lu <1579567540@qq.com>
+++++++++++
The same applies to all commits coming from the Rockchip vendor kernel.
Thanks
Heiko
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
` (26 preceding siblings ...)
2026-10-21 16:11 ` [PATCH 27/27] arm64: dts: rockchip: Add initial support for Forlinx OK3572-C Cunhao Lu via B4 Relay
@ 2026-10-21 23:00 ` Shawn Lin
27 siblings, 0 replies; 32+ messages in thread
From: Shawn Lin @ 2026-10-21 23:00 UTC (permalink / raw)
To: 1579567540, Stephen Boyd, Brian Masney, Jerome Brunet,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
Philipp Zabel, Elaine Zhang, Lee Jones, Linus Walleij,
Bartosz Golaszewski, Richard Cochran, Ulf Hansson, Andi Shyti,
Greg Kroah-Hartman, Jiri Slaby, Jisheng Zhang, Andrew Lunn,
David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
David Wu, Rafael J. Wysocki, Daniel Lezcano, Zhang Rui,
Lukasz Luba, Maxime Chevallier, Maxime Coquelin,
Alexandre Torgue, Vinod Koul, Neil Armstrong,
Manivannan Sadhasivam, Thinh Nguyen, Jaehoon Chung
Cc: shawn.lin, linux-clk, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, mfd, linux-gpio, netdev, linux-pm,
linux-i2c, linux-serial, linux-mmc, linux-stm32, linux-phy,
linux-usb
Hi Cunhao,
在 2026/10/22 星期四 0:10, Cunhao Lu via B4 Relay 写道:
> This series adds initial support for the RK3572 SoC and the Forlinx
> OK3572-C board. It includes the bindings, drivers, and device trees
> needed to bring up a minimal system.
>
Thanks for your patches. Typically, a series of this size covering SoC
support should be split by subsystem，for instance, separate DT binding
and driver patches for each subsystem，and only CC the relevant
maintainers and mailing lists. The DTS patch can follow afterwards.
> The RK3572 SoC has eight CPU cores: two Cortex-A73 cores and six
> Cortex-A53 cores. It also integrates an Arm Mali-G310V2 MC1 GPU.
> The OK3572-C board provides two Gigabit Ethernet ports, three USB3 Type-A
> ports, a Type-C dual-role port, eMMC, microSD, and UART.
>
> Testing was performed with Debian 13 minimal and Linux 7.3 on the
> OK3572-C with the FET3572-C module. Shared peripheral tests were run with
> the system booted from SD, while eMMC validation covered the complete
> boot chain.
>
> Passed functionality:unhao
>
> - SD and eMMC complete the firmware, kernel, and root filesystem
> boot chain.
> - UART console works at 1500000 baud.
> - SD read/write and data persistence checks pass.
> - All eight CPUs start; CPU frequency scaling and hotplug checks pass.
> - Both Ethernet ports obtain IPv4 addresses and pass bidirectional file
> transfers.
> - All three Type-A ports pass USB2 and USB3 enumeration, data transfers,
> and reconnect persistence checks.
> - Type-C host and device modes pass in both plug orientations. Physical
> reconnects correctly select the expected device, host, and device roles
> in sequence.
>
> Stability:
>
> - Repeated cold and software reboots complete on SD and eMMC without data
> integrity failures.
> - A combined CPU, memory, network, SD, and USB3 stress test completes
> without a crash, lockup, CPU offline event, or thermal shutdown.
> - Ethernet error and drop counters do not increase during bidirectional
> network tests.
>
> Build and checks:
>
> - The kernel, modules, and board DTB build successfully.
> - The series passes checkpatch with --strict; only generic reminders about
> new MAINTAINERS entries remain.
>
> Untested hardware and paths:
>
> - NPU
> - PCIe
> - GPU, video output, and audio
> - CPU rates above 1.2 GHz and voltage scaling
> - Other low-speed external interfaces
>
> Some files in this series are derived from the Forlinx OK3572-C BSP
> Alpha1. Thanks to Forlinx for their support.
>
> AI assistance:
>
> - Codex / DeepSeek V4.1 Flash were used for:
> - Collecting data
> - Automating tests
> - Reviewing and adjusting code to follow community conventions
>
> Signed-off-by: Cunhao Lu <1579567540@qq.com>
> ---
> Raw dmesg from the OK3572-C boot:
>
> [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
> [ 0.000000] Linux version 7.3.0-bleedingedge-rk3572 (build@armbian) (aarch64-linux-gnu-gcc (Ubuntu 11.4.0-1ubuntu1~22.04.3) 11.4.0, GNU ld (GNU Binutils for Ubuntu) 2.38) #1 SMP PREEMPT Wed Oct 21 14:04:07 CST 2026
> [ 0.000000] Machine model: Forlinx OK3572-C
> [ 0.000000] efi: UEFI not found.
> [ 0.000000] OF: reserved mem: Reserved memory: No reserved-memory node in the DT
> [ 0.000000] psci: probing for conduit method from DT.
> [ 0.000000] psci: PSCIv1.1 detected in firmware.
> [ 0.000000] psci: Using standard PSCI v0.2 function IDs
> [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
> [ 0.000000] psci: SMC Calling Convention v1.5
> [ 0.000000] Zone ranges:
> [ 0.000000] DMA [mem 0x0000000040200000-0x00000000ffffffff]
> [ 0.000000] DMA32 empty
> [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
> [ 0.000000] Movable zone start for each node
> [ 0.000000] Early memory node ranges
> [ 0.000000] node 0: [mem 0x0000000040200000-0x000000013fffffff]
> [ 0.000000] Initmem setup node 0 [mem 0x0000000040200000-0x000000013fffffff]
> [ 0.000000] On node 0, zone DMA: 512 pages in unavailable ranges
> [ 0.000000] percpu: Embedded 30 pages/cpu s82136 r8192 d32552 u122880
> [ 0.000000] pcpu-alloc: s82136 r8192 d32552 u122880 alloc=30*4096
> [ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5 [0] 6 [0] 7
> [ 0.000000] CPU features: detected: ARM erratum 845719
> [ 0.000000] alternatives: applying boot alternatives
> [ 0.000000] Kernel command line: root=UUID=2520cc50-b3ea-430f-ba9b-552afa4b6f82 rootwait rootfstype=ext4 splash=verbose console=ttyS0,1500000 console=tty1 consoleblank=0 loglevel=1 ubootpart=48cd0da4-4dfb-4b7c-b03f-e4a0c57ddacd usb-storage.quirks=0x2537:0x1066:u,0x2537:0x1068:u cgroup_enable=cpuset cgroup_memory=1 cgroup_enable=memory
> [ 0.000000] Unknown kernel command line parameters "splash=verbose ubootpart=48cd0da4-4dfb-4b7c-b03f-e4a0c57ddacd cgroup_enable=memory cgroup_memory=1", will be passed to user space.
> [ 0.000000] printk: log buffer data + meta data: 131072 + 458752 = 589824 bytes
> [ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
> [ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
> [ 0.000000] software IO TLB: area num 8.
> [ 0.000000] software IO TLB: mapped [mem 0x00000000f7f47000-0x00000000fbf47000] (64MB)
> [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1048064
> [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
> [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
> [ 0.000000] ftrace: allocating 40216 entries in 158 pages
> [ 0.000000] ftrace: allocated 158 pages with 5 groups
> [ 0.000000] rcu: Hierarchical RCU implementation.
> [ 0.000000] rcu: RCU event tracing is enabled.
> [ 0.000000] Trampoline variant of Tasks RCU enabled.
> [ 0.000000] Rude variant of Tasks RCU enabled.
> [ 0.000000] Tracing variant of Tasks RCU enabled.
> [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
> [ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=8.
> [ 0.000000] RCU Tasks Rude: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=8.
> [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
> [ 0.000000] Root IRQ handler: gic_handle_irq
> [ 0.000000] GIC: Using split EOI/Deactivate mode
> [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
> [ 0.000000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
> [ 0.000000] arch_timer: cp15 timer running at 24.00MHz (phys).
> [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
> [ 0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
> [ 0.000502] Console: colour dummy device 80x25
> [ 0.000516] printk: legacy console [tty1] enabled
> [ 0.000637] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
> [ 0.000652] pid_max: default: 32768 minimum: 301
> [ 0.000874] Yama: becoming mindful.
> [ 0.001075] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
> [ 0.001097] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
> [ 0.001450] VFS: Finished mounting rootfs on nullfs
> [ 0.004025] rcu: Hierarchical SRCU implementation.
> [ 0.004042] rcu: Max phase no-delay instances is 1000.
> [ 0.004294] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
> [ 0.004820] EFI services will not be available.
> [ 0.005261] smp: Bringing up secondary CPUs ...
> [ 0.006096] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
> [ 0.006991] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
> [ 0.007847] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
> [ 0.008787] CPU4: Booted secondary processor 0x0000000100 [0x410fd034]
> [ 0.009715] CPU5: Booted secondary processor 0x0000000101 [0x410fd034]
> [ 0.010446] CPU features: detected: Spectre-BHB
> [ 0.010459] CPU features: detected: ARM erratum 858921
> [ 0.010576] arch_timer: Enabling local workaround for ARM erratum 858921
> [ 0.010590] arch_timer: CPU6: Trapping CNTVCT access
> [ 0.010600] CPU6: Booted secondary processor 0x0000000200 [0x411fd090]
> [ 0.011335] arch_timer: Enabling local workaround for ARM erratum 858921
> [ 0.011346] arch_timer: CPU7: Trapping CNTVCT access
> [ 0.011354] CPU7: Booted secondary processor 0x0000000201 [0x411fd090]
> [ 0.011443] smp: Brought up 1 node, 8 CPUs
> [ 0.011468] SMP: Total of 8 processors activated.
> [ 0.011473] CPU: All CPU(s) started at EL2
> [ 0.011480] CPU features: detected: 32-bit EL0 Support
> [ 0.011487] CPU features: detected: CRC32 instructions
> [ 0.011563] alternatives: applying system-wide alternatives
> [ 0.013503] Memory: 3994400K/4192256K available (12800K kernel code, 1804K rwdata, 8020K rodata, 4800K init, 367K bss, 188600K reserved, 0K cma-reserved)
> [ 0.014586] devtmpfs: initialized
> [ 0.023256] posixtimers hash table entries: 4096 (order: 4, 65536 bytes, linear)
> [ 0.023390] futex hash table entries: 2048 (131072 bytes on 1 NUMA nodes, total 128 KiB, linear).
> [ 0.023497] 25760 pages in range for non-PLT usage
> [ 0.023504] 517280 pages in range for PLT usage
> [ 0.024485] DMI: not present or invalid.
> [ 0.027105] NET: Registered PF_NETLINK/PF_ROUTE protocol family
> [ 0.027775] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
> [ 0.027873] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
> [ 0.027917] audit: initializing netlink subsys (disabled)
> [ 0.028106] audit: type=2000 audit(0.024:1): state=initialized audit_enabled=0 res=1
> [ 0.063844] thermal_sys: Registered thermal governor 'step_wise'
> [ 0.063969] ASID allocator initialised with 65536 entries
> [ 0.066221] /soc/i2c@2c040000/usb-typec@22/connector: Fixed dependency cycle(s) with /soc/usb@24000000
> [ 0.066238] /soc/usb@24000000: Fixed dependency cycle(s) with /soc/i2c@2c040000/usb-typec@22/connector
> [ 0.066401] /soc/interrupt-controller@2a601000: Fixed dependency cycle(s) with /soc/interrupt-controller@2a601000
> [ 0.074302] rockchip-gpio 26300000.gpio: probed /pinctrl/gpio@26300000
> [ 0.074859] rockchip-gpio 2b200000.gpio: probed /pinctrl/gpio@2b200000
> [ 0.075467] rockchip-gpio 2b300000.gpio: probed /pinctrl/gpio@2b300000
> [ 0.076065] rockchip-gpio 2b400000.gpio: probed /pinctrl/gpio@2b400000
> [ 0.076577] rockchip-gpio 2b500000.gpio: probed /pinctrl/gpio@2b500000
> [ 0.079569] iommu: Default domain type: Translated
> [ 0.079581] iommu: DMA domain TLB invalidation policy: strict mode
> [ 0.087665] SCSI subsystem initialized
> [ 0.087800] usbcore: registered new interface driver usbfs
> [ 0.087825] usbcore: registered new interface driver hub
> [ 0.087851] usbcore: registered new device driver usb
> [ 0.087962] pps_core: LinuxPPS API ver. 1 registered
> [ 0.087967] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
> [ 0.087977] PTP clock support registered
> [ 0.088046] scmi_core: SCMI protocol bus registered
> [ 0.088816] vgaarb: loaded
> [ 0.089111] clocksource: Switched to clocksource arch_sys_counter
> [ 0.095252] NET: Registered PF_INET protocol family
> [ 0.095435] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
> [ 0.098401] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
> [ 0.098444] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
> [ 0.098456] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
> [ 0.098599] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
> [ 0.099208] TCP: Hash tables configured (established 32768 bind 32768)
> [ 0.099320] UDP hash table entries: 2048 (order: 5, 131072 bytes, linear)
> [ 0.099566] NET: Registered PF_UNIX/PF_LOCAL protocol family
> [ 0.099609] PCI: CLS 0 bytes, default 64
> [ 0.099809] Unpacking initramfs...
> [ 0.113777] Initialise system trusted keyrings
> [ 0.114004] workingset: timestamp_bits=46 (anon: 41) max_order=20 bucket_order=0 (anon: 0)
> [ 0.114534] fuse: init (API version 7.46)
> [ 0.114817] NET: Registered PF_ALG protocol family
> [ 0.114828] Key type asymmetric registered
> [ 0.114833] Asymmetric key parser 'x509' registered
> [ 0.114866] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249)
> [ 0.115027] io scheduler mq-deadline registered
> [ 0.115033] io scheduler kyber registered
> [ 0.115065] io scheduler bfq registered
> [ 0.603726] Freeing initrd memory: 13024K
> [ 0.641317] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
> [ 0.642938] printk: console [ttyS0] disabled
> [ 0.643204] 2c130000.serial: ttyS0 MMIO32:0x000000002c130000 (irq = 36, base_baud = 1500000) is a 16550A
> [ 0.643447] printk: console [ttyS0] enabled
> [ 0.649403] loop: module loaded
> [ 0.650488] tun: Universal TUN/TAP device driver, 1.6
> [ 0.657994] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
> [ 0.658022] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
> [ 0.658098] xhci-hcd xhci-hcd.0.auto: hcc params 0x0220fe64 hci version 0x110 quirks 0x0000808002000010
> [ 0.658139] xhci-hcd xhci-hcd.0.auto: irq 38, io mem 0x24400000
> [ 0.658251] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
> [ 0.658261] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
> [ 0.658273] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
> [ 0.658925] hub 1-0:1.0: USB hub found
> [ 0.658955] hub 1-0:1.0: 1 port detected
> [ 0.659569] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
> [ 0.659953] hub 2-0:1.0: USB hub found
> [ 0.659977] hub 2-0:1.0: 1 port detected
> [ 0.660444] usbcore: registered new interface driver uas
> [ 0.660501] usbcore: registered new interface driver usb-storage
> [ 0.660521] usbcore: registered new device driver onboard-usb-dev
> [ 0.677538] vdda_hdmi_s0: Bringing 750000uV into 837500-837500uV
> [ 0.691929] pca953x 2-0023: using auto increment
> [ 0.704405] dwmmc_rockchip 2a090000.mmc: IDMAC supports 32-bit address mode.
> [ 0.704405] arm-scmi arm-scmi.4.auto: Using scmi_smc_transport
> [ 0.704420] arm-scmi arm-scmi.4.auto: SCMI max-rx-timeout: 30ms / max-msg-size: 104bytes / max-msg: 20
> [ 0.704437] dwmmc_rockchip 2a090000.mmc: Using internal DMA controller.
> [ 0.704446] dwmmc_rockchip 2a090000.mmc: Version ID is 270a
> [ 0.704482] dwmmc_rockchip 2a090000.mmc: DW MMC controller at irq 62,32 bit host data width,256 deep fifo
> [ 0.704546] scmi_protocol scmi_dev.1: Enabled polling mode TX channel - prot_id:16
> [ 0.704919] arm-scmi arm-scmi.4.auto: SCMI Notifications - Core Enabled.
> [ 0.704981] arm-scmi arm-scmi.4.auto: SCMI Protocol v2.0 'rockchip:' Firmware version 0x0
> [ 0.705018] arm-scmi arm-scmi.4.auto: Enabling SCMI Quirk [quirk_clock_rates_triplet_out_of_spec]
> [ 0.705787] mmc0: CQHCI version 5.10
> [ 0.708680] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
> [ 0.708975] usbcore: registered new interface driver usbhid
> [ 0.708982] usbhid: USB HID core driver
> [ 0.709386] NET: Registered PF_INET6 protocol family
> [ 0.710254] Segment Routing with IPv6
> [ 0.710294] In-situ OAM (IOAM) with IPv6
> [ 0.710341] NET: Registered PF_PACKET protocol family
> [ 0.710370] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
> [ 0.715466] Loading compiled-in X.509 certificates
> [ 0.717882] mmc_host mmc1: Bus speed = 400000Hz (req 400000Hz, actual 400000HZ div = 0)
> [ 0.721073] Key type encrypted registered
> [ 0.732592] mmc0: SDHCI controller on 2a010000.mmc [2a010000.mmc] using ADMA 64-bit
> [ 0.737594] dwc3-generic-plat 24400000.usb: Failed to create device link (0x180) with supplier regulator-usb-hub-1v2 for /soc/usb@24400000/hub@2
> [ 0.737903] rk_gmac-dwmac 29d20000.ethernet: IRQ sfty not found
> [ 0.738262] rk_gmac-dwmac 29d20000.ethernet: clock input or output? (output).
> [ 0.738271] rk_gmac-dwmac 29d20000.ethernet: TX delay(0x21).
> [ 0.738279] rk_gmac-dwmac 29d20000.ethernet: Can not read property: rx_delay.
> [ 0.738284] rk_gmac-dwmac 29d20000.ethernet: set rx_delay to 0x10
> [ 0.738298] rk_gmac-dwmac 29d20000.ethernet: integrated PHY? (no).
> [ 0.743326] rk_gmac-dwmac 29d20000.ethernet: init for RGMII_RXID
> [ 0.743496] rk_gmac-dwmac 29d20000.ethernet: User ID: 0x50, Synopsys ID: 0x51
> [ 0.743506] rk_gmac-dwmac 29d20000.ethernet: DWMAC4/5
> [ 0.743513] rk_gmac-dwmac 29d20000.ethernet: DMA HW capability register supported
> [ 0.743519] rk_gmac-dwmac 29d20000.ethernet: Active PHY interface: RGMII (1)
> [ 0.743525] rk_gmac-dwmac 29d20000.ethernet: RX Checksum Offload Engine supported
> [ 0.743530] rk_gmac-dwmac 29d20000.ethernet: TX Checksum insertion supported
> [ 0.743535] rk_gmac-dwmac 29d20000.ethernet: Wake-Up On Lan supported
> [ 0.743580] rk_gmac-dwmac 29d20000.ethernet: Enable RX Mitigation via HW Watchdog Timer
> [ 0.743587] rk_gmac-dwmac 29d20000.ethernet: Enabled L3L4 Flow TC (entries=2)
> [ 0.743594] rk_gmac-dwmac 29d20000.ethernet: Enabled RFS Flow TC (entries=10)
> [ 0.743599] rk_gmac-dwmac 29d20000.ethernet: TSO supported
> [ 0.743604] rk_gmac-dwmac 29d20000.ethernet: TSO feature enabled
> [ 0.743609] rk_gmac-dwmac 29d20000.ethernet: SPH feature enabled
> [ 0.743614] rk_gmac-dwmac 29d20000.ethernet: Using 40/40 bits DMA host/device width
> [ 0.801924] sdhci-dwcmshc 2a010000.mmc: Can't reduce the clock below 52MHz in HS200/HS400 mode
> [ 0.802190] mmc0: Command Queue Engine enabled
> [ 0.802216] mmc0: new HS400 Enhanced strobe MMC card at address 0001
> [ 0.802867] mmcblk0: mmc0:0001 C9A611 58.3 GiB
> [ 0.806837] mmcblk0: p1
> [ 0.807374] mmcblk0boot0: mmc0:0001 C9A611 4.00 MiB
> [ 0.809014] mmcblk0boot1: mmc0:0001 C9A611 4.00 MiB
> [ 0.810526] mmcblk0rpmb: mmc0:0001 C9A611 16.0 MiB, chardev (248:0)
> [ 0.884811] rk_gmac-dwmac 2a040000.ethernet: IRQ sfty not found
> [ 0.885249] rk_gmac-dwmac 2a040000.ethernet: clock input or output? (output).
> [ 0.885262] rk_gmac-dwmac 2a040000.ethernet: TX delay(0x20).
> [ 0.885269] rk_gmac-dwmac 2a040000.ethernet: Can not read property: rx_delay.
> [ 0.885275] rk_gmac-dwmac 2a040000.ethernet: set rx_delay to 0x10
> [ 0.885362] rk_gmac-dwmac 2a040000.ethernet: integrated PHY? (no).
> [ 0.890392] rk_gmac-dwmac 2a040000.ethernet: init for RGMII_RXID
> [ 0.890584] rk_gmac-dwmac 2a040000.ethernet: User ID: 0x50, Synopsys ID: 0x51
> [ 0.890595] rk_gmac-dwmac 2a040000.ethernet: DWMAC4/5
> [ 0.890603] rk_gmac-dwmac 2a040000.ethernet: DMA HW capability register supported
> [ 0.890608] rk_gmac-dwmac 2a040000.ethernet: Active PHY interface: RGMII (1)
> [ 0.890615] rk_gmac-dwmac 2a040000.ethernet: RX Checksum Offload Engine supported
> [ 0.890620] rk_gmac-dwmac 2a040000.ethernet: TX Checksum insertion supported
> [ 0.890625] rk_gmac-dwmac 2a040000.ethernet: Wake-Up On Lan supported
> [ 0.890675] rk_gmac-dwmac 2a040000.ethernet: Enable RX Mitigation via HW Watchdog Timer
> [ 0.890682] rk_gmac-dwmac 2a040000.ethernet: Enabled L3L4 Flow TC (entries=2)
> [ 0.890693] rk_gmac-dwmac 2a040000.ethernet: Enabled RFS Flow TC (entries=10)
> [ 0.890699] rk_gmac-dwmac 2a040000.ethernet: TSO supported
> [ 0.890704] rk_gmac-dwmac 2a040000.ethernet: TSO feature enabled
> [ 0.890709] rk_gmac-dwmac 2a040000.ethernet: SPH feature enabled
> [ 0.890714] rk_gmac-dwmac 2a040000.ethernet: Using 40/40 bits DMA host/device width
> [ 0.913126] usb 1-1: new high-speed USB device number 2 using xhci-hcd
> [ 1.048394] clk: Disabling unused clocks
> [ 1.048873] PM: genpd: Disabling unused power domains
> [ 1.051000] Freeing unused kernel memory: 4800K
> [ 1.051125] Run /init as init process
> [ 1.051130] with arguments:
> [ 1.051134] /init
> [ 1.051137] with environment:
> [ 1.051139] HOME=/
> [ 1.051141] TERM=linux
> [ 1.051144] splash=verbose
> [ 1.051146] ubootpart=48cd0da4-4dfb-4b7c-b03f-e4a0c57ddacd
> [ 1.051149] cgroup_enable=memory
> [ 1.051151] cgroup_memory=1
> [ 1.106465] hub 1-1:1.0: USB hub found
> [ 1.106513] hub 1-1:1.0: 4 ports detected
> [ 1.177969] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
> [ 1.218522] hub 2-1:1.0: USB hub found
> [ 1.218968] hub 2-1:1.0: 4 ports detected
> [ 1.505447] usb 2-1.2: new SuperSpeed USB device number 3 using xhci-hcd
> [ 1.528547] usb-storage 2-1.2:1.0: USB Mass Storage device detected
> [ 1.529653] scsi host0: usb-storage 2-1.2:1.0
> [ 1.536346] rk_gmac-dwmac 29d20000.ethernet end0: renamed from eth0
> [ 1.537766] rk_gmac-dwmac 2a040000.ethernet end1: renamed from eth1
> [ 1.686075] raid6: using neon recovery algorithm
> [ 1.717069] raid6: int64x1 gen() 847 MB/s
> [ 1.737837] raid6: int64x2 gen() 1264 MB/s
> [ 1.752864] raid6: int64x4 gen() 1747 MB/s
> [ 1.763929] raid6: int64x8 gen() 2371 MB/s
> [ 1.773319] raid6: neonx1 gen() 2796 MB/s
> [ 1.781011] raid6: neonx2 gen() 3409 MB/s
> [ 1.786289] raid6: neonx4 gen() 4970 MB/s
> [ 1.791806] raid6: neonx8 gen() 4753 MB/s
> [ 1.791809] raid6: using algorithm neonx4 gen() 4970 MB/s
> [ 1.794906] raid6: .... xor() 4236 MB/s, rmw enabled
> [ 1.796085] xor: measuring software checksum speed
> [ 1.797076] neon : 13380 MB/sec
> [ 1.798330] 32regs : 10491 MB/sec
> [ 1.799540] 8regs : 10874 MB/sec
> [ 1.799542] xor: using function: neon (13380 MB/sec)
> [ 1.849991] Btrfs loaded, zoned=no, fsverity=no
> [ 1.937396] EXT4-fs (mmcblk0p1): mounted filesystem 2520cc50-b3ea-430f-ba9b-552afa4b6f82 ro with writeback data mode. Quota mode: disabled.
> [ 2.097144] usb 1-1.3: new high-speed USB device number 3 using xhci-hcd
> [ 2.124255] systemd[1]: System time advanced to timestamp on /var/lib/systemd/timesync/clock: Wed 2026-10-21 09:39:33 UTC
> [ 2.159722] systemd[1]: systemd 257.13-1~deb13u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +IPE +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBCRYPTSETUP_PLUGINS +LIBFDISK +PCRE2 +PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD +BPF_FRAMEWORK +BTF -XKBCOMMON -UTMP +SYSVINIT +LIBARCHIVE)
> [ 2.159752] systemd[1]: Detected architecture arm64.
> [ 2.187497] usb-storage 1-1.3:1.0: USB Mass Storage device detected
> [ 2.187840] scsi host1: usb-storage 1-1.3:1.0
> [ 2.304474] systemd[1]: bpf-restrict-fs: BPF LSM hook not enabled in the kernel, BPF LSM not supported.
> [ 2.333489] dw-apb-uart 2c130000.serial: forbid DMA for kernel console
> [ 2.561278] scsi 0:0:0:0: Direct-Access Generic MassStorageClass 2962 PQ: 0 ANSI: 6
> [ 2.562581] sd 0:0:0:0: [sda] Media removed, stopped polling
> [ 2.563353] systemd[1]: Queued start job for default target graphical.target.
> [ 2.564595] scsi 0:0:0:1: Direct-Access Generic MassStorageClass 2962 PQ: 0 ANSI: 6
> [ 2.568510] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
> [ 2.570149] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
> [ 2.571561] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
> [ 2.572692] systemd[1]: Created slice user.slice - User and Session Slice.
> [ 2.573163] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
> [ 2.573510] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
> [ 2.573797] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point skipped, unmet condition check ConditionPathExists=/proc/sys/fs/binfmt_misc
> [ 2.573881] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
> [ 2.574097] systemd[1]: Reached target paths.target - Path Units.
> [ 2.574254] systemd[1]: Reached target remote-fs.target - Remote File Systems.
> [ 2.574386] systemd[1]: Reached target slices.target - Slice Units.
> [ 2.574522] systemd[1]: Reached target swap.target - Swaps.
> [ 2.575001] systemd[1]: Listening on syslog.socket - Syslog Socket.
> [ 2.577411] systemd[1]: Listening on systemd-creds.socket - Credential Encryption/Decryption.
> [ 2.577941] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
> [ 2.578412] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
> [ 2.578959] systemd[1]: Listening on systemd-journald.socket - Journal Sockets.
> [ 2.579632] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
> [ 2.579893] systemd[1]: systemd-pcrextend.socket - TPM PCR Measurements skipped, unmet condition check ConditionSecurity=measured-uki
> [ 2.579945] systemd[1]: systemd-pcrlock.socket - Make TPM PCR Policy skipped, unmet condition check ConditionSecurity=measured-uki
> [ 2.580276] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
> [ 2.580707] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
> [ 2.581241] systemd[1]: dev-hugepages.mount - Huge Pages File System skipped, unmet condition check ConditionPathExists=/sys/kernel/mm/hugepages
> [ 2.584057] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
> [ 2.586938] systemd[1]: Mounting run-lock.mount - Legacy Locks Directory /run/lock...
> [ 2.589826] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
> [ 2.592783] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
> [ 2.593548] sd 0:0:0:0: [sda] Attached SCSI removable disk
> [ 2.596003] systemd[1]: Starting fake-hwclock-load.service - Restore the current clock...
> [ 2.600570] systemd[1]: Starting keyboard-setup.service - Set the console keyboard layout...
> [ 2.604814] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
> [ 2.613686] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
> [ 2.617598] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
> [ 2.626158] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
> [ 2.633752] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
> [ 2.634121] systemd[1]: netplan-ovs-cleanup.service - OpenVSwitch configuration for cleanup skipped, unmet condition check ConditionFileIsExecutable=/usr/bin/ovs-vsctl
> [ 2.634358] systemd[1]: systemd-hibernate-clear.service - Clear Stale Hibernate Storage Info skipped, unmet condition check ConditionPathExists=/sys/firmware/efi/efivars/HibernateLocation-8cf2644b-4b0b-428f-9387-6d876050dc67
> [ 2.639834] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
> [ 2.643700] systemd[1]: Starting systemd-network-generator.service - Generate Network Units from Kernel Command Line...
> [ 2.644139] systemd[1]: systemd-pcrmachine.service - TPM PCR Machine ID Measurement skipped, unmet condition check ConditionSecurity=measured-uki
> [ 2.644383] systemd[1]: systemd-tpm2-setup-early.service - Early TPM SRK Setup skipped, unmet condition check ConditionSecurity=measured-uki
> [ 2.648310] systemd[1]: Starting systemd-udev-load-credentials.service - Load udev Rules from Credentials...
> [ 2.652281] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
> [ 2.661621] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
> [ 2.663368] systemd[1]: Mounted run-lock.mount - Legacy Locks Directory /run/lock.
> [ 2.664501] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
> [ 2.665462] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
> [ 2.666583] systemd[1]: fake-hwclock-load.service: Deactivated successfully.
> [ 2.667169] systemd[1]: Finished fake-hwclock-load.service - Restore the current clock.
> [ 2.668734] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
> [ 2.669954] systemd[1]: modprobe@configfs.service: Deactivated successfully.
> [ 2.670577] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
> [ 2.671875] systemd[1]: modprobe@drm.service: Deactivated successfully.
> [ 2.672499] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
> [ 2.673859] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
> [ 2.674460] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
> [ 2.675669] systemd[1]: modprobe@fuse.service: Deactivated successfully.
> [ 2.676291] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
> [ 2.683474] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
> [ 2.686792] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
> [ 2.687022] systemd[1]: systemd-fsck-root.service - File System Check on Root Device skipped, unmet condition check ConditionPathExists=!/run/initramfs/fsck-root
> [ 2.697694] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
> [ 2.705654] systemd[1]: Starting systemd-tmpfiles-setup-dev-early.service - Create Static Device Nodes in /dev gracefully...
> [ 2.708619] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
> [ 2.714637] systemd[1]: Finished systemd-network-generator.service - Generate Network Units from Kernel Command Line.
> [ 2.719008] systemd[1]: Finished systemd-udev-load-credentials.service - Load udev Rules from Credentials.
> [ 2.721423] systemd[1]: Mounted sys-fs-fuse-connections.mount - FUSE Control File System.
> [ 2.722109] systemd[1]: Reached target network-pre.target - Preparation for Network.
> [ 2.725804] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
> [ 2.727801] systemd[1]: Mounted sys-kernel-config.mount - Kernel Configuration File System.
> [ 2.772223] systemd[1]: Finished systemd-tmpfiles-setup-dev-early.service - Create Static Device Nodes in /dev gracefully.
> [ 2.773872] EXT4-fs (mmcblk0p1): re-mounted 2520cc50-b3ea-430f-ba9b-552afa4b6f82 r/w.
> [ 2.777912] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
> [ 2.779673] systemd[1]: systemd-hwdb-update.service - Rebuild Hardware Database skipped, unmet condition check ConditionNeedsUpdate=/etc
> [ 2.779919] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival skipped, unmet condition check ConditionDirectoryNotEmpty=/sys/fs/pstore
> [ 2.783365] systemd[1]: Starting systemd-random-seed.service - Load/Save OS Random Seed...
> [ 2.783733] systemd[1]: systemd-sysusers.service - Create System Users skipped, no trigger condition checks were met.
> [ 2.790652] systemd[1]: Starting systemd-timesyncd.service - Network Time Synchronization...
> [ 2.793619] systemd[1]: Starting systemd-tmpfiles-setup-dev.service - Create Static Device Nodes in /dev...
> [ 2.793932] systemd[1]: systemd-tpm2-setup.service - TPM SRK Setup skipped, unmet condition check ConditionSecurity=measured-uki
> [ 2.795274] systemd[1]: Finished keyboard-setup.service - Set the console keyboard layout.
> [ 2.796841] systemd[1]: Finished systemd-sysctl.service - Apply Kernel Variables.
> [ 2.803118] systemd[1]: Starting systemd-resolved.service - Network Name Resolution...
> [ 2.852608] systemd[1]: Finished systemd-tmpfiles-setup-dev.service - Create Static Device Nodes in /dev.
> [ 2.853310] systemd[1]: Reached target local-fs-pre.target - Preparation for Local File Systems.
> [ 2.857305] systemd[1]: Starting systemd-udevd.service - Rule-based Manager for Device Events and Files...
> [ 2.956019] systemd[1]: Started systemd-timesyncd.service - Network Time Synchronization.
> [ 2.957257] systemd[1]: Reached target time-set.target - System Time Set.
> [ 3.028829] systemd[1]: Started systemd-udevd.service - Rule-based Manager for Device Events and Files.
> [ 3.037801] systemd[1]: Starting systemd-networkd.service - Network Configuration...
> [ 3.108456] sd 0:0:0:1: [sdb] Spinning up disk...
> [ 3.157455] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
> [ 3.185174] random: crng init done
> [ 3.193688] systemd[1]: Finished systemd-random-seed.service - Load/Save OS Random Seed.
> [ 3.194566] systemd[1]: first-boot-complete.target - First Boot Complete skipped, unmet condition check ConditionFirstBoot=yes
> [ 3.204351] scsi 1:0:0:0: Direct-Access HIKSEMI PSSD 0100 PQ: 0 ANSI: 6
> [ 3.210912] sd 1:0:0:0: [sdc] 2000409264 512-byte logical blocks: (1.02 TB/954 GiB)
> [ 3.212772] sd 1:0:0:0: [sdc] Write Protect is off
> [ 3.212811] sd 1:0:0:0: [sdc] Mode Sense: 43 00 00 00
> [ 3.213208] sd 1:0:0:0: [sdc] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
> [ 3.234251] cfg80211: Loading compiled-in X.509 certificates for regulatory database
> [ 3.239605] systemd[1]: Found device dev-ttyS0.device - /dev/ttyS0.
> [ 3.270004] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
> [ 3.271763] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
> [ 3.277656] systemd[1]: Started systemd-resolved.service - Network Name Resolution.
> [ 3.288182] sdc: sdc1 sdc2
> [ 3.288736] sd 1:0:0:0: [sdc] Attached SCSI disk
> [ 3.857154] systemd[1]: Reached target nss-lookup.target - Host and Network Name Lookups.
> [ 3.857424] systemd[1]: Reached target usb-gadget.target - Hardware activated USB gadget.
> [ 3.862630] systemd[1]: Mounting tmp.mount - /tmp...
> [ 3.891645] systemd[1]: Mounted tmp.mount - /tmp.
> [ 3.892193] systemd[1]: Reached target local-fs.target - Local File Systems.
> [ 3.894856] systemd[1]: Listening on systemd-sysext.socket - System Extension Image Management.
> [ 3.897761] systemd[1]: Starting armbian-zram-config.service - Armbian ZRAM config...
> [ 3.900711] systemd[1]: Starting console-setup.service - Set console font and keymap...
> [ 3.901703] systemd[1]: systemd-binfmt.service - Set Up Additional Binary Formats skipped, unmet condition check ConditionPathIsMountPoint=/proc/sys/fs/binfmt_misc
> [ 3.901895] systemd[1]: systemd-machine-id-commit.service - Save Transient machine-id to Disk skipped, unmet condition check ConditionPathIsMountPoint=/etc/machine-id
> [ 3.935051] systemd[1]: Finished console-setup.service - Set console font and keymap.
> [ 4.125129] .ready
> [ 4.496526] sd 0:0:0:1: [sdb] 122167296 512-byte logical blocks: (62.5 GB/58.3 GiB)
> [ 4.497199] sd 0:0:0:1: [sdb] Write Protect is off
> [ 4.497208] sd 0:0:0:1: [sdb] Mode Sense: 21 00 00 00
> [ 4.497863] sd 0:0:0:1: [sdb] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
> [ 4.526869] sdb: sdb1
> [ 4.527177] sd 0:0:0:1: [sdb] Attached SCSI removable disk
> [ 4.536274] zram: Added device: zram0
> [ 4.536958] zram: Added device: zram1
> [ 4.537502] zram: Added device: zram2
> [ 4.560724] zswap: loaded using pool lzo
> [ 4.583622] zram0: detected capacity change from 0 to 4021480
> [ 4.602878] Adding 2010736k swap on /dev/zram0. Priority:5 extents:1 across:2010736k SS
> [ 4.618289] systemd[1]: Started systemd-networkd.service - Network Configuration.
> [ 4.620664] rk_gmac-dwmac 2a040000.ethernet end1: Register MEM_TYPE_PAGE_POOL RxQ-0
> [ 4.623308] systemd[1]: Starting systemd-networkd-persistent-storage.service - Enable Persistent Storage in systemd-networkd...
> [ 4.635307] zram1: detected capacity change from 0 to 102400
> [ 4.649148] rk_gmac-dwmac 2a040000.ethernet end1: PHY [stmmac-1:01] driver [RTL8211F Gigabit Ethernet] (irq=POLL)
> [ 4.651091] dwmac4: Master AXI performs any burst length
> [ 4.651105] rk_gmac-dwmac 2a040000.ethernet end1: No Safety Features support found
> [ 4.651449] rk_gmac-dwmac 2a040000.ethernet end1: IEEE 1588-2008 Advanced Timestamp supported
> [ 4.651645] rk_gmac-dwmac 2a040000.ethernet end1: registered PTP clock
> [ 4.651652] rk_gmac-dwmac 2a040000.ethernet end1: configuring for phy/rgmii-rxid link mode
> [ 4.672612] systemd[1]: Finished armbian-zram-config.service - Armbian ZRAM config.
> [ 4.675764] systemd[1]: Starting armbian-ramlog.service - Armbian memory supported logging...
> [ 4.679240] rk_gmac-dwmac 29d20000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
> [ 4.705167] rk_gmac-dwmac 29d20000.ethernet end0: PHY [stmmac-0:02] driver [RTL8211F Gigabit Ethernet] (irq=POLL)
> [ 4.717129] dwmac4: Master AXI performs any burst length
> [ 4.717166] rk_gmac-dwmac 29d20000.ethernet end0: No Safety Features support found
> [ 4.717690] rk_gmac-dwmac 29d20000.ethernet end0: IEEE 1588-2008 Advanced Timestamp supported
> [ 4.718006] rk_gmac-dwmac 29d20000.ethernet end0: registered PTP clock
> [ 4.718031] rk_gmac-dwmac 29d20000.ethernet end0: configuring for phy/rgmii-rxid link mode
> [ 4.747457] systemd[1]: Finished systemd-networkd-persistent-storage.service - Enable Persistent Storage in systemd-networkd.
> [ 4.748565] EXT4-fs (zram1): mounted filesystem 839fe5ef-a8e2-4adc-b9a0-0c76a7cc60b4 r/w without journal. Quota mode: disabled.
> [ 5.000713] systemd[1]: Finished armbian-ramlog.service - Armbian memory supported logging.
> [ 5.007005] systemd[1]: Starting systemd-journald.service - Journal Service...
> [ 5.093778] systemd-journald[438]: Collecting audit messages is disabled.
> [ 5.173135] systemd[1]: Started systemd-journald.service - Journal Service.
> [ 5.231994] systemd-journald[438]: Received client request to flush runtime journal.
> [ 5.588283] systemd-journald[438]: Received client request to relinquish /var/log/journal/958cd540f0e041c6b855006cbba7667a access.
> [ 6.241260] NOTICE: Automounting of tracing to debugfs is deprecated and will be removed in 2030
> [ 7.806604] rk_gmac-dwmac 29d20000.ethernet end0: Link is Up - 1Gbps/Full - flow control rx/tx
> [ 8.766543] rk_gmac-dwmac 2a040000.ethernet end1: Link is Up - 1Gbps/Full - flow control rx/tx
> [ 31.709317] vdd_npu_s0: disabling
>
> To: Stephen Boyd <sboyd@kernel.org>
> To: Brian Masney <bmasney+clk@redhat.com>
> To: Jerome Brunet <jbrunet+clk@baylibre.com>
> To: Rob Herring <robh@kernel.org>
> To: Krzysztof Kozlowski <krzk+dt@kernel.org>
> To: Conor Dooley <conor+dt@kernel.org>
> To: Heiko Stuebner <heiko@sntech.de>
> To: Philipp Zabel <p.zabel@pengutronix.de>
> To: Elaine Zhang <zhangqing@rock-chips.com>
> To: Lee Jones <lee@kernel.org>
> To: Linus Walleij <linusw@kernel.org>
> To: Bartosz Golaszewski <brgl@kernel.org>
> To: Richard Cochran <richardcochran@gmail.com>
> To: Ulf Hansson <ulfh@kernel.org>
> To: Andi Shyti <andi.shyti@kernel.org>
> To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> To: Jiri Slaby <jirislaby@kernel.org>
> To: Jisheng Zhang <jszhang@kernel.org>
> To: Andrew Lunn <andrew+netdev@lunn.ch>
> To: "David S. Miller" <davem@davemloft.net>
> To: Eric Dumazet <edumazet@kernel.org>
> To: Jakub Kicinski <kuba@kernel.org>
> To: Paolo Abeni <pabeni@redhat.com>
> To: David Wu <david.wu@rock-chips.com>
> To: "Rafael J. Wysocki" <rafael@kernel.org>
> To: Daniel Lezcano <daniel.lezcano@kernel.org>
> To: Zhang Rui <rui.zhang@intel.com>
> To: Lukasz Luba <lukasz.luba@arm.com>
> To: Maxime Chevallier <maxime.chevallier@bootlin.com>
> To: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> To: Alexandre Torgue <alexandre.torgue@foss.st.com>
> To: Vinod Koul <vkoul@kernel.org>
> To: Neil Armstrong <neil.armstrong@linaro.org>
> To: Manivannan Sadhasivam <mani@kernel.org>
> To: Cunhao Lu <1579567540@qq.com>
> To: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
> To: Jaehoon Chung <jh80.chung@samsung.com>
> To: Shawn Lin <shawn.lin@rock-chips.com>
> Cc: linux-clk@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-rockchip@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Cc: mfd@lists.linux.dev
> Cc: linux-gpio@vger.kernel.org
> Cc: netdev@vger.kernel.org
> Cc: linux-pm@vger.kernel.org
> Cc: linux-i2c@vger.kernel.org
> Cc: linux-serial@vger.kernel.org
> Cc: linux-mmc@vger.kernel.org
> Cc: linux-stm32@st-md-mailman.stormreply.com
> Cc: linux-phy@lists.infradead.org
> Cc: linux-usb@vger.kernel.org
>
> ---
> Cunhao Lu (27):
> dt-bindings: clock: rockchip: Add RK3572 CRU
> dt-bindings: power: rockchip: Add RK3572 power domains
> dt-bindings: soc: rockchip: Add RK3572 PMU and GRF
> dt-bindings: mfd: syscon: Add RK3572 QoS register compatible
> dt-bindings: pinctrl: rockchip: Add RK3572
> dt-bindings: gpio: rockchip: Add RK3572 GPIO banks
> clk: rockchip: Add RK3572 clock and reset support
> pinctrl: rockchip: Add RK3572 support
> gpio: rockchip: Add RK3572 GPIO support
> pmdomain: rockchip: Add RK3572 boot peripheral domains
> dt-bindings: i2c: rk3x: Add RK3572
> dt-bindings: serial: snps-dw-apb-uart: Add RK3572
> dt-bindings: mmc: rockchip: Add RK3572 controllers
> dt-bindings: net: rockchip-dwmac: Add RK3572
> dt-bindings: thermal: rockchip: Add RK3572
> net: stmmac: dwmac-rk: Add RK3572 support
> thermal: rockchip: Add RK3572 support
> dt-bindings: phy: rockchip-inno-usb2: Add RK3572
> dt-bindings: phy: rockchip-naneng-combphy: Add RK3572
> dt-bindings: usb: rockchip: Add RK3572 DWC3 controller
> phy: rockchip-inno-usb2: Add RK3572 support
> phy: rockchip-naneng-combphy: Add RK3572 support
> usb: dwc3: Configure RK3572 PIPE port before discovery
> mmc: dw_mmc-rockchip: Keep RK3572 NVM domain powered
> dt-bindings: arm: rockchip: Add Forlinx OK3572-C
> arm64: dts: rockchip: Add RK3572 SoC
> arm64: dts: rockchip: Add initial support for Forlinx OK3572-C
>
> .../devicetree/bindings/arm/rockchip.yaml | 6 +
> .../devicetree/bindings/arm/rockchip/pmu.yaml | 2 +
> .../bindings/clock/rockchip,rk3572-cru.yaml | 57 +
> .../bindings/gpio/rockchip,gpio-bank.yaml | 24 +-
> .../devicetree/bindings/i2c/i2c-rk3x.yaml | 1 +
> Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
> .../devicetree/bindings/mmc/rockchip-dw-mshc.yaml | 1 +
> .../bindings/mmc/snps,dwcmshc-sdhci.yaml | 3 +
> .../devicetree/bindings/net/rockchip-dwmac.yaml | 3 +
> .../bindings/phy/phy-rockchip-naneng-combphy.yaml | 23 +
> .../bindings/phy/rockchip,inno-usb2phy.yaml | 14 +
> .../bindings/pinctrl/rockchip,pinctrl.yaml | 1 +
> .../bindings/power/rockchip,power-controller.yaml | 17 +
> .../bindings/serial/snps-dw-apb-uart.yaml | 1 +
> .../devicetree/bindings/soc/rockchip/grf.yaml | 12 +
> .../bindings/thermal/rockchip-thermal.yaml | 2 +
> .../bindings/usb/rockchip,rk3572-dwc3.yaml | 100 +
> arch/arm64/boot/dts/rockchip/Makefile | 1 +
> .../dts/rockchip/rk3572-forlinx-fet3572-c.dtsi | 369 ++
> .../boot/dts/rockchip/rk3572-forlinx-ok3572-c.dts | 286 ++
> arch/arm64/boot/dts/rockchip/rk3572-opp.dtsi | 165 +
> arch/arm64/boot/dts/rockchip/rk3572-pinctrl.dtsi | 3935 ++++++++++++++++++++
> arch/arm64/boot/dts/rockchip/rk3572.dtsi | 1325 +++++++
> drivers/clk/rockchip/Kconfig | 7 +
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk-rk3572.c | 1972 ++++++++++
> drivers/clk/rockchip/clk.h | 36 +
> drivers/clk/rockchip/rst-rk3572.c | 739 ++++
> drivers/gpio/gpio-rockchip.c | 91 +-
> drivers/mmc/host/dw_mmc-rockchip.c | 24 +
> drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 53 +
> drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 136 +
> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 201 +
> drivers/pinctrl/pinctrl-rockchip.c | 230 +-
> drivers/pinctrl/pinctrl-rockchip.h | 9 +-
> drivers/pmdomain/rockchip/pm-domains.c | 141 +-
> drivers/thermal/rockchip_thermal.c | 28 +
> drivers/usb/dwc3/dwc3-generic-plat.c | 31 +
> include/dt-bindings/clock/rockchip,rk3572-cru.h | 560 +++
> .../power/rockchip,rk3572-power-controller.h | 30 +
> include/dt-bindings/reset/rockchip,rk3572-cru.h | 713 ++++
> include/soc/rockchip/rockchip_sip.h | 5 +
> 42 files changed, 11332 insertions(+), 24 deletions(-)
> ---
> base-commit: a804c5742bff224d4cb4d25dd383554d598be32b
> change-id: 20261021-add-board-ok3572-c-8ed18b9065da
>
> Best regards,
> --
> Cunhao Lu <1579567540@qq.com>
>
>
>
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2026-10-21 23:00 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-10-21 16:10 [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Cunhao Lu via B4 Relay
2026-10-21 16:10 ` [PATCH 01/27] dt-bindings: clock: rockchip: Add RK3572 CRU Cunhao Lu via B4 Relay
2026-10-21 16:10 ` [PATCH 02/27] dt-bindings: power: rockchip: Add RK3572 power domains Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 03/27] dt-bindings: soc: rockchip: Add RK3572 PMU and GRF Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 04/27] dt-bindings: mfd: syscon: Add RK3572 QoS register compatible Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 05/27] dt-bindings: pinctrl: rockchip: Add RK3572 Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 06/27] dt-bindings: gpio: rockchip: Add RK3572 GPIO banks Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 07/27] clk: rockchip: Add RK3572 clock and reset support Cunhao Lu via B4 Relay
2026-10-21 22:26 ` Heiko Stübner
2026-10-21 16:11 ` [PATCH 08/27] pinctrl: rockchip: Add RK3572 support Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 09/27] gpio: rockchip: Add RK3572 GPIO support Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 10/27] pmdomain: rockchip: Add RK3572 boot peripheral domains Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 11/27] dt-bindings: i2c: rk3x: Add RK3572 Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 12/27] dt-bindings: serial: snps-dw-apb-uart: " Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 13/27] dt-bindings: mmc: rockchip: Add RK3572 controllers Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 14/27] dt-bindings: net: rockchip-dwmac: Add RK3572 Cunhao Lu via B4 Relay
2026-10-21 17:14 ` Andrew Lunn
2026-10-21 16:11 ` [PATCH 15/27] dt-bindings: thermal: rockchip: " Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 16/27] net: stmmac: dwmac-rk: Add RK3572 support Cunhao Lu via B4 Relay
2026-10-21 17:09 ` Andrew Lunn
2026-10-21 16:11 ` [PATCH 17/27] thermal: rockchip: " Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 18/27] dt-bindings: phy: rockchip-inno-usb2: Add RK3572 Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 19/27] dt-bindings: phy: rockchip-naneng-combphy: " Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 20/27] dt-bindings: usb: rockchip: Add RK3572 DWC3 controller Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 21/27] phy: rockchip-inno-usb2: Add RK3572 support Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 22/27] phy: rockchip-naneng-combphy: " Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 23/27] usb: dwc3: Configure RK3572 PIPE port before discovery Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 24/27] mmc: dw_mmc-rockchip: Keep RK3572 NVM domain powered Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 25/27] dt-bindings: arm: rockchip: Add Forlinx OK3572-C Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 26/27] arm64: dts: rockchip: Add RK3572 SoC Cunhao Lu via B4 Relay
2026-10-21 16:11 ` [PATCH 27/27] arm64: dts: rockchip: Add initial support for Forlinx OK3572-C Cunhao Lu via B4 Relay
2026-10-21 23:00 ` [PATCH 00/27] rockchip: Add RK3572 and Forlinx OK3572-C support Shawn Lin
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