[PATCH 1/2] dt-bindings: display: bridge: waveshare,dsi2dpi: Document 1..4 DSI lane support

[PATCH 1/2] dt-bindings: display: bridge: waveshare,dsi2dpi: Document 1..4 DSI lane support

[Marek Vasut]

Describe 1..4 DSI lanes as supported. Internally, this bridge is
an ChipOne ICN6211 which loads its register configuration from a
dedicated storage and its I2C does not seem to be accessible. The
ICN6211 supports up to 4 DSI lanes, so this is a hard limit for
this bridge. The lane configuration is preconfigured in the bridge
for each of the WaveShare panels.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: David Airlie <airlied@gmail.com>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Joseph Guo <qijian.guo@nxp.com>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Robert Foss <rfoss@kernel.org>
Cc: Simona Vetter <simona@ffwll.ch>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: devicetree@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
 .../devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml  | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml b/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml
index 5e8498c8303dd..3820dd7e11af1 100644
--- a/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml
@@ -40,9 +40,12 @@ properties:
             properties:
               data-lanes:
                 description: array of physical DSI data lane indexes.
+                minItems: 1
                 items:
                   - const: 1
                   - const: 2
+                  - const: 3
+                  - const: 4
 
             required:
               - data-lanes
-- 
2.51.0

[PATCH 2/2] drm/bridge: waveshare-dsi: Add support for 1..4 DSI data lanes

[Marek Vasut]

Parse the data lane count out of DT. Limit the supported data lanes
to 1..4 which is the maximum available DSI pairs on the connector of
any known panels which may use this bridge. Internally, this bridge
is an ChipOne ICN6211 which loads its register configuration from a
dedicated storage and its I2C does not seem to be accessible. The
ICN6211 also supports up to 4 DSI lanes, so this is a hard limit.

To avoid any breakage on old DTs where the parsing of data lanes from
DT may fail, fall back to the original hard-coded value of 2 lanes and
warn user.

The lane configuration is preconfigured in the bridge for each of the
WaveShare panels. The 13.3" DSI panel works with 4-lane configuration,
others seem to use 2-lane configuration. This is a hardware property,
so the actual count should come from DT.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: David Airlie <airlied@gmail.com>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Joseph Guo <qijian.guo@nxp.com>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Robert Foss <rfoss@kernel.org>
Cc: Simona Vetter <simona@ffwll.ch>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: devicetree@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
 drivers/gpu/drm/bridge/waveshare-dsi.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/waveshare-dsi.c b/drivers/gpu/drm/bridge/waveshare-dsi.c
index 9254446f54958..7fcb878f37e2b 100644
--- a/drivers/gpu/drm/bridge/waveshare-dsi.c
+++ b/drivers/gpu/drm/bridge/waveshare-dsi.c
@@ -66,7 +66,11 @@ static int ws_bridge_attach_dsi(struct ws_bridge *ws)
 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
 			  MIPI_DSI_CLOCK_NON_CONTINUOUS;
 	dsi->format = MIPI_DSI_FMT_RGB888;
-	dsi->lanes = 2;
+	dsi->lanes = drm_of_get_data_lanes_count_ep(dev->of_node, 0, 0, 1, 4);
+	if (dsi->lanes < 0) {
+		dev_warn(dev, "Invalid DSI lane count %d, falling back to 2 lanes\n", dsi->lanes);
+		dsi->lanes = 2;	/* Old DT backward compatibility */
+	}
 
 	ret = devm_mipi_dsi_attach(dev, dsi);
 	if (ret < 0)
-- 
2.51.0

Re: [EXT] [PATCH 2/2] drm/bridge: waveshare-dsi: Add support for 1..4 DSI data lanes

[Joseph Guo]

On 1/13/2026 7:47 AM, Marek Vasut wrote:
> [You don't often get email from marek.vasut+renesas@mailbox.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> 
> Caution: This is an external email. Please take care when clicking links or opening attachments. When in doubt, report the message using the 'Report this email' button
> 
> 
> Parse the data lane count out of DT. Limit the supported data lanes
> to 1..4 which is the maximum available DSI pairs on the connector of
> any known panels which may use this bridge. Internally, this bridge
> is an ChipOne ICN6211 which loads its register configuration from a
> dedicated storage and its I2C does not seem to be accessible. The
> ICN6211 also supports up to 4 DSI lanes, so this is a hard limit.
> 
> To avoid any breakage on old DTs where the parsing of data lanes from
> DT may fail, fall back to the original hard-coded value of 2 lanes and
> warn user.
> 
> The lane configuration is preconfigured in the bridge for each of the
> WaveShare panels. The 13.3" DSI panel works with 4-lane configuration,
> others seem to use 2-lane configuration. This is a hardware property,
> so the actual count should come from DT.
> 
>
Hi Marek,

I don't have 4 lanes waveshare panel on my hands. Have you tested with the 4-lane panel already?

Regards,
Joseph

Re: [EXT] [PATCH 2/2] drm/bridge: waveshare-dsi: Add support for 1..4 DSI data lanes

[Marek Vasut]

On 1/13/26 7:41 AM, Joseph Guo wrote:
> On 1/13/2026 7:47 AM, Marek Vasut wrote:
>> [You don't often get email from marek.vasut+renesas@mailbox.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>
>> Caution: This is an external email. Please take care when clicking links or opening attachments. When in doubt, report the message using the 'Report this email' button
>>
>>
>> Parse the data lane count out of DT. Limit the supported data lanes
>> to 1..4 which is the maximum available DSI pairs on the connector of
>> any known panels which may use this bridge. Internally, this bridge
>> is an ChipOne ICN6211 which loads its register configuration from a
>> dedicated storage and its I2C does not seem to be accessible. The
>> ICN6211 also supports up to 4 DSI lanes, so this is a hard limit.
>>
>> To avoid any breakage on old DTs where the parsing of data lanes from
>> DT may fail, fall back to the original hard-coded value of 2 lanes and
>> warn user.
>>
>> The lane configuration is preconfigured in the bridge for each of the
>> WaveShare panels. The 13.3" DSI panel works with 4-lane configuration,
>> others seem to use 2-lane configuration. This is a hardware property,
>> so the actual count should come from DT.
>>
>>
> Hi Marek,
> 
> I don't have 4 lanes waveshare panel on my hands. Have you tested with the 4-lane panel already?
Yes, the 13.3" DSI panel is 4-lane 
https://www.waveshare.com/13.3inch-dsi-lcd.htm , I have it connected to 
Retronix Sparrow Hawk board which has 4-lane port.

See also this patch I submitted, that is the DT binding for it:

[PATCH 2/2] arm64: dts: renesas: sparrow-hawk: Add overlay for WaveShare 
Display 13.3"

Re: [EXT] [PATCH 2/2] drm/bridge: waveshare-dsi: Add support for 1..4 DSI data lanes

[Joseph Guo]

On 1/13/2026 4:04 PM, Marek Vasut wrote:
> [You don't often get email from marek.vasut@mailbox.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> 
> Caution: This is an external email. Please take care when clicking links or opening attachments. When in doubt, report the message using the 'Report this email' button
> 
> 
> On 1/13/26 7:41 AM, Joseph Guo wrote:
>> On 1/13/2026 7:47 AM, Marek Vasut wrote:
>>> [You don't often get email from marek.vasut+renesas@mailbox.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>
>>> Caution: This is an external email. Please take care when clicking links or opening attachments. When in doubt, report the message using the 'Report this email' button
>>>
>>>
>>> Parse the data lane count out of DT. Limit the supported data lanes
>>> to 1..4 which is the maximum available DSI pairs on the connector of
>>> any known panels which may use this bridge. Internally, this bridge
>>> is an ChipOne ICN6211 which loads its register configuration from a
>>> dedicated storage and its I2C does not seem to be accessible. The
>>> ICN6211 also supports up to 4 DSI lanes, so this is a hard limit.
>>>
>>> To avoid any breakage on old DTs where the parsing of data lanes from
>>> DT may fail, fall back to the original hard-coded value of 2 lanes and
>>> warn user.
>>>
>>> The lane configuration is preconfigured in the bridge for each of the
>>> WaveShare panels. The 13.3" DSI panel works with 4-lane configuration,
>>> others seem to use 2-lane configuration. This is a hardware property,
>>> so the actual count should come from DT.
>>>
>>>
>> Hi Marek,
>>
>> I don't have 4 lanes waveshare panel on my hands. Have you tested with the 4-lane panel already?
> Yes, the 13.3" DSI panel is 4-lane
> https://www.waveshare.com/13.3inch-dsi-lcd.htm, I have it connected to
> Retronix Sparrow Hawk board which has 4-lane port.
> 
> See also this patch I submitted, that is the DT binding for it:
> 
> [PATCH 2/2] arm64: dts: renesas: sparrow-hawk: Add overlay for WaveShare
> Display 13.3"

OK, thank you.
Reviewed-by: Joseph Guo <qijian.guo@nxp.com>

Regards,
Joseph

Re: [EXT] [PATCH 2/2] drm/bridge: waveshare-dsi: Add support for 1..4 DSI data lanes

[Marek Vasut]

On 1/13/26 9:15 AM, Joseph Guo wrote:
> On 1/13/2026 4:04 PM, Marek Vasut wrote:
>> [You don't often get email from marek.vasut@mailbox.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>
>> Caution: This is an external email. Please take care when clicking links or opening attachments. When in doubt, report the message using the 'Report this email' button
>>
>>
>> On 1/13/26 7:41 AM, Joseph Guo wrote:
>>> On 1/13/2026 7:47 AM, Marek Vasut wrote:
>>>> [You don't often get email from marek.vasut+renesas@mailbox.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>>
>>>> Caution: This is an external email. Please take care when clicking links or opening attachments. When in doubt, report the message using the 'Report this email' button
>>>>
>>>>
>>>> Parse the data lane count out of DT. Limit the supported data lanes
>>>> to 1..4 which is the maximum available DSI pairs on the connector of
>>>> any known panels which may use this bridge. Internally, this bridge
>>>> is an ChipOne ICN6211 which loads its register configuration from a
>>>> dedicated storage and its I2C does not seem to be accessible. The
>>>> ICN6211 also supports up to 4 DSI lanes, so this is a hard limit.
>>>>
>>>> To avoid any breakage on old DTs where the parsing of data lanes from
>>>> DT may fail, fall back to the original hard-coded value of 2 lanes and
>>>> warn user.
>>>>
>>>> The lane configuration is preconfigured in the bridge for each of the
>>>> WaveShare panels. The 13.3" DSI panel works with 4-lane configuration,
>>>> others seem to use 2-lane configuration. This is a hardware property,
>>>> so the actual count should come from DT.
>>>>
>>>>
>>> Hi Marek,
>>>
>>> I don't have 4 lanes waveshare panel on my hands. Have you tested with the 4-lane panel already?
>> Yes, the 13.3" DSI panel is 4-lane
>> https://www.waveshare.com/13.3inch-dsi-lcd.htm, I have it connected to
>> Retronix Sparrow Hawk board which has 4-lane port.
>>
>> See also this patch I submitted, that is the DT binding for it:
>>
>> [PATCH 2/2] arm64: dts: renesas: sparrow-hawk: Add overlay for WaveShare
>> Display 13.3"
> 
> OK, thank you.
> Reviewed-by: Joseph Guo <qijian.guo@nxp.com>
Thank you too.

Re: [PATCH 2/2] drm/bridge: waveshare-dsi: Add support for 1..4 DSI data lanes

[Geert Uytterhoeven]

Hi Marek,

On Tue, 13 Jan 2026 at 00:48, Marek Vasut
<marek.vasut+renesas@mailbox.org> wrote:
> Parse the data lane count out of DT. Limit the supported data lanes
> to 1..4 which is the maximum available DSI pairs on the connector of
> any known panels which may use this bridge. Internally, this bridge
> is an ChipOne ICN6211 which loads its register configuration from a
> dedicated storage and its I2C does not seem to be accessible. The
> ICN6211 also supports up to 4 DSI lanes, so this is a hard limit.
>
> To avoid any breakage on old DTs where the parsing of data lanes from
> DT may fail, fall back to the original hard-coded value of 2 lanes and
> warn user.
>
> The lane configuration is preconfigured in the bridge for each of the
> WaveShare panels. The 13.3" DSI panel works with 4-lane configuration,
> others seem to use 2-lane configuration. This is a hardware property,
> so the actual count should come from DT.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

Thanks for your patch!

> --- a/drivers/gpu/drm/bridge/waveshare-dsi.c
> +++ b/drivers/gpu/drm/bridge/waveshare-dsi.c
> @@ -66,7 +66,11 @@ static int ws_bridge_attach_dsi(struct ws_bridge *ws)
>         dsi->mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
>                           MIPI_DSI_CLOCK_NON_CONTINUOUS;
>         dsi->format = MIPI_DSI_FMT_RGB888;
> -       dsi->lanes = 2;
> +       dsi->lanes = drm_of_get_data_lanes_count_ep(dev->of_node, 0, 0, 1, 4);
> +       if (dsi->lanes < 0) {
> +               dev_warn(dev, "Invalid DSI lane count %d, falling back to 2 lanes\n", dsi->lanes);

"Invalid or missing"?

BTW, I doubt the kerneldoc for drm_of_get_data_lanes_count_ep()
is correct:

 * Return:
 * * min..max - positive integer count of "data-lanes" elements
 * * -EINVAL - the "data-mapping" property is unsupported
 * * -ENODEV - the "data-mapping" property is missing

1. s/data-mapping/data-lanes/,
2. of_property_count_u32_elems() never returns -ENODEV?

> +               dsi->lanes = 2; /* Old DT backward compatibility */
> +       }
>
>         ret = devm_mipi_dsi_attach(dev, dsi);
>         if (ret < 0)

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/2] drm/bridge: waveshare-dsi: Add support for 1..4 DSI data lanes

[Marek Vasut]

On 1/14/26 10:32 AM, Geert Uytterhoeven wrote:

Hello Geert,

>> +++ b/drivers/gpu/drm/bridge/waveshare-dsi.c
>> @@ -66,7 +66,11 @@ static int ws_bridge_attach_dsi(struct ws_bridge *ws)
>>          dsi->mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
>>                            MIPI_DSI_CLOCK_NON_CONTINUOUS;
>>          dsi->format = MIPI_DSI_FMT_RGB888;
>> -       dsi->lanes = 2;
>> +       dsi->lanes = drm_of_get_data_lanes_count_ep(dev->of_node, 0, 0, 1, 4);
>> +       if (dsi->lanes < 0) {
>> +               dev_warn(dev, "Invalid DSI lane count %d, falling back to 2 lanes\n", dsi->lanes);
> 
> "Invalid or missing"?

Fixed in V2

> BTW, I doubt the kerneldoc for drm_of_get_data_lanes_count_ep()
> is correct:
Nice find, fixed in

[PATCH] drm: of: Fix drm_of_get_data_lanes_count_ep() return value 
documentation

Thanks !