From: Dave Jiang <dave.jiang@intel.com>
To: Srirangan Madhavan <smadhavan@nvidia.com>,
Alison Schofield <alison.schofield@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <jic23@kernel.org>,
Vishal Verma <vishal.l.verma@intel.com>,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Alex Williamson <alex.williamson@redhat.com>,
vsethi@nvidia.com, alwilliamson@nvidia.com,
Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
Vishal Aslot <vaslot@nvidia.com>,
Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
Richard Cheng <icheng@nvidia.com>,
linux-tegra@vger.kernel.org
Subject: Re: [PATCH v14 09/16] cxl: Refresh cached PCI HDM decoder settings
Date: Fri, 2 Oct 2026 16:57:51 -0700 [thread overview]
Message-ID: <48d34fdc-d891-4175-81df-2217068176dd@intel.com> (raw)
In-Reply-To: <20261001092227.3004747-10-smadhavan@nvidia.com>
On 10/1/26 2:22 AM, Srirangan Madhavan wrote:
> Early PCI discovery creates the HDM cache, while later CXL enumeration and
> decoder operations provide updated programming state.
>
> Refresh the PCI snapshot when decoders are enumerated, committed, or reset
> so reset recovery need not walk the CXL topology. Ignore updates when no
> cache exists and reject decoder-count mismatches.
>
> Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
> ---
> drivers/cxl/core/hdm.c | 58 ++++++++++++++++++++++++++++++++++++++++++
> include/cxl/cxl.h | 22 ++++++++++++++++
> include/linux/pci.h | 6 +++++
> 3 files changed, 86 insertions(+)
>
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index b6a8fe83d336..d6b3afbffa3e 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -753,6 +753,44 @@ static void cxl_decoder_snapshot(struct cxl_decoder *cxld,
> }
> }
>
> +static void cxl_hdm_refresh_decoder(struct cxl_hdm *cxlhdm,
> + struct cxl_decoder *cxld)
> +{
> + struct cxl_port *port = cxlhdm->port;
> + void __iomem *hdm = cxlhdm->regs.hdm_decoder;
reverse xmas tree pls.
> + struct cxl_decoder_settings *settings;
> + struct cxl_hdm_info *info;
> + struct pci_dev *pdev __free(pci_dev_put) =
> + cxl_port_get_uport_pci_dev(port);
You can move this outside of declaration block. It's one of the exceptions.
Also, is there any reason to reference a PCI device specifically? Can't you just get the 'struct device' and use exclusively that in this function? Prefer to keep the function neutral here rather than hard code it to PCI and I don't see anything specific to PCI that needs the hard coding. core/hdm.c should use 'struct device'. It does not have a PCI dependency before this. Also you may break cxl_test as it uses platform devices instead of PCI devices.
As an aside, can you please do me a favor and run cxl_test for your series? Having it passing all regression tests is one of the requirements for us to accept CXL patches. We will help you fix any issues crop up if you need it. Of course adding new regression tests for reset to test the new core functions would be awesome and much appreciated.
> +
> + if (!pdev || !hdm)
> + return;
Go ahead and do the block like:
struct pci_dev *pdev __free(pci_dev_put) =
cxl_port_get_uport_pci_dev(port);
if (!pdev)
return;
if (!hdm)
return;
> +
> + guard(rwsem_write)(&cxl_rwsem.dpa);
> + info = pdev->hdm;
> + if (!info)
> + return;
Could use a blank line here.
> + if (cxld->config.id < 0 || cxld->config.id >= info->decoder_count) {
Maybe just create a local ptr for cxld->config given all the places you need to access its members.
> + pci_warn(pdev, "CXL HDM decoder %d exceeds cached count %d\n",
> + cxld->config.id, info->decoder_count);
> + return;
> + }
> +
> + info->global_ctrl = readl(hdm + CXL_HDM_DECODER_CTRL_OFFSET);
> + settings = &info->settings[cxld->config.id];
> +
> + /*
> + * A disabled decoder's software object may retain its old range and
> + * target state. Leave only the decoder id in the cached settings so stale
> + * state is not restored as an enabled decode.
> + */
> + *settings = (struct cxl_decoder_settings) {
> + .config.id = cxld->config.id,
> + };
> + if (cxld->config.flags & CXL_DECODER_F_ENABLE)
> + cxl_decoder_snapshot(cxld, settings);
> +}
> +
> static int cxl_decoder_commit(struct cxl_decoder *cxld)
> {
> struct cxl_port *port = to_cxl_port(cxld->dev.parent);
> @@ -804,6 +842,7 @@ static int cxl_decoder_commit(struct cxl_decoder *cxld)
> }
> port->commit_end++;
> cxld->config.flags |= CXL_DECODER_F_ENABLE;
> + cxl_hdm_refresh_decoder(cxlhdm, cxld);
>
> return 0;
> }
> @@ -876,6 +915,7 @@ static void cxl_decoder_reset(struct cxl_decoder *cxld)
> writel(0, hdm + CXL_HDM_DECODER0_BASE_LOW_OFFSET(id));
>
> cxld->config.flags &= ~CXL_DECODER_F_ENABLE;
> + cxl_hdm_refresh_decoder(cxlhdm, cxld);
>
> /* Userspace is now responsible for reconfiguring this decoder */
> if (is_endpoint_decoder(&cxld->dev)) {
> @@ -1086,6 +1126,23 @@ static int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm,
> int i;
> u64 dpa_base = 0;
>
> + if (is_cxl_endpoint(port) && hdm) {
> + struct pci_dev *pdev __free(pci_dev_put) =
> + cxl_port_get_uport_pci_dev(port);
> +
> + if (pdev) {
> + guard(rwsem_read)(&cxl_rwsem.dpa);
> +
> + if (pdev->hdm &&
> + pdev->hdm->decoder_count != cxlhdm->decoder_count) {
> + pci_warn(pdev,
> + "CXL HDM cache decoder count mismatch: cached=%d hdm=%d\n",
> + pdev->hdm->decoder_count, cxlhdm->decoder_count);
> + return -ENXIO;
> + }
> + }
So we can't have a 'struct pci_dev' in core/hdm.c without breaking cxl_test. I think we can move this block into a helper function that's in core/pci.c. Maybe call it something like cxl_check_cached_decoder_settings(). I'm open to ideas. That way cxl_test can create a mock function and override it. See something like cxl_await_media_ready() in tools/testing/cxl/ on how to fixup cxl_test. Until we add support code for decoder saving etc in cxl_test, it can just do nothing now.
DJ
> + }
> +
> cxl_settle_decoders(cxlhdm);
>
> for (i = 0; i < cxlhdm->decoder_count; i++) {
> @@ -1124,6 +1181,7 @@ static int devm_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm,
> put_device(&cxld->dev);
> return rc;
> }
> + cxl_hdm_refresh_decoder(cxlhdm, cxld);
> rc = add_hdm_decoder(port, cxld);
> if (rc) {
> dev_warn(&port->dev,
> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
> index 67c81be47fbb..e200c5c56b92 100644
> --- a/include/cxl/cxl.h
> +++ b/include/cxl/cxl.h
> @@ -82,6 +82,28 @@ struct cxl_decoder_settings {
> u64 target_or_skip_reg_val;
> };
>
> +/**
> + * struct cxl_hdm_info - cached CXL HDM state for a PCI device
> + * @decoder_count: number of entries in @settings
> + * @hdm_bar: PCI BAR containing the HDM decoder capability
> + * @hdm_offset: offset of the HDM decoder capability in @hdm_bar
> + * @hdm_size: size of the HDM decoder register block
> + * @global_ctrl: HDM decoder global control register
> + * @dvsec_ctrl: CXL DVSEC control register
> + * @dvsec_ctrl_valid: whether @dvsec_ctrl contains valid state
> + * @settings: per-decoder programming state
> + */
> +struct cxl_hdm_info {
> + int decoder_count;
> + int hdm_bar;
> + resource_size_t hdm_offset;
> + resource_size_t hdm_size;
> + u32 global_ctrl;
> + u16 dvsec_ctrl;
> + bool dvsec_ctrl_valid;
> + struct cxl_decoder_settings settings[] __counted_by(decoder_count);
> +};
> +
> /*
> * Using struct_group() allows for per register-block-type helper routines,
> * without requiring block-type agnostic code to include the prefix.
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index d31a8d107b1e..7bb37fcb556d 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -339,6 +339,9 @@ struct pcie_link_state;
> struct pci_sriov;
> struct pci_p2pdma;
> struct rcec_ea;
> +#ifdef CONFIG_CXL_RESET
> +struct cxl_hdm_info;
> +#endif
>
> /* struct pci_dev - describes a PCI device
> *
> @@ -566,6 +569,9 @@ struct pci_dev {
> #ifdef CONFIG_PCI_DOE
> struct xarray doe_mbs; /* Data Object Exchange mailboxes */
> #endif
> +#ifdef CONFIG_CXL_RESET
> + struct cxl_hdm_info *hdm; /* CXL HDM decoder state */
> +#endif
> #ifdef CONFIG_PCI_NPEM
> struct npem *npem; /* Native PCIe Enclosure Management */
> #endif
next prev parent reply other threads:[~2026-10-02 23:57 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-01 9:22 [PATCH v14 00/16] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 01/16] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-10-02 9:33 ` Richard Cheng
2026-10-01 9:22 ` [PATCH v14 02/16] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-02 9:48 ` Richard Cheng
2026-10-01 9:22 ` [PATCH v14 03/16] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-02 9:49 ` Richard Cheng
2026-10-01 9:22 ` [PATCH v14 04/16] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-02 10:17 ` Richard Cheng
2026-10-02 19:07 ` Dave Jiang
2026-10-01 9:22 ` [PATCH v14 05/16] cxl: Introduce reusable HDM decoder settings Srirangan Madhavan
2026-10-02 19:59 ` Dave Jiang
2026-10-01 9:22 ` [PATCH v14 06/16] cxl: Move HDM decoder helpers to built-in resource code Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 07/16] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-02 21:46 ` Dave Jiang
2026-10-01 9:22 ` [PATCH v14 08/16] cxl: Reject overflowing HDM decoder ranges Srirangan Madhavan
2026-10-02 21:50 ` Dave Jiang
2026-10-01 9:22 ` [PATCH v14 09/16] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-02 23:57 ` Dave Jiang [this message]
2026-10-01 9:22 ` [PATCH v14 10/16] cxl: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 11/16] cxl: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 12/16] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-02 8:06 ` Richard Cheng
2026-10-01 9:22 ` [PATCH v14 13/16] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 14/16] cxl: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 15/16] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-01 9:22 ` [PATCH v14 16/16] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=48d34fdc-d891-4175-81df-2217068176dd@intel.com \
--to=dave.jiang@intel.com \
--cc=alex.williamson@redhat.com \
--cc=alison.schofield@intel.com \
--cc=alwilliamson@nvidia.com \
--cc=bhelgaas@google.com \
--cc=dave@stgolabs.net \
--cc=icheng@nvidia.com \
--cc=ira.weiny@intel.com \
--cc=jan@nvidia.com \
--cc=jic23@kernel.org \
--cc=linux-cxl@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=mhonap@nvidia.com \
--cc=skancherla@nvidia.com \
--cc=smadhavan@nvidia.com \
--cc=vaslot@nvidia.com \
--cc=vishal.l.verma@intel.com \
--cc=vsethi@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®