Re: [PATCH 8/9] cpufreq: tegra194: Add support for Tegra264

[Zhongqiu Han <zhongqiu.han@oss.qualcomm.com>]

On 11/5/2026 2:15 AM, Sumit Gupta wrote:
> Add cpufreq support for Tegra264. It requests and reads the CPU
> frequency differently from earlier SoCs.
> 
> To request a frequency, the driver writes NDIV to a core_freq_req
> register in the CCPLEX register space. Two clusters share a
> cluster-clock unit and its register, so they always run at the same
> frequency. The driver exposes each pair as one performance domain and
> one cpufreq policy. Each CPU's "performance-domains" property gives the
> domain index, which selects the register. If the CCPLEX node declares
> "#performance-domain-cells", probe fails if any CPU lacks the property.
> 
> To read the frequency, the driver samples the per-CPU 64-bit AMU
> counters through system registers. The AMU constant counter is the
> reference. It ticks at the system counter rate, so the driver takes the
> reference rate from CNTFRQ instead of the fixed 408 MHz clock.
> 
> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
> ---
>   drivers/cpufreq/Kconfig.arm        |   4 +-
>   drivers/cpufreq/tegra194-cpufreq.c | 147 ++++++++++++++++++++++++++++-
>   2 files changed, 144 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> index a441668f9e0c..a5482b12be57 100644
> --- a/drivers/cpufreq/Kconfig.arm
> +++ b/drivers/cpufreq/Kconfig.arm
> @@ -248,9 +248,9 @@ config ARM_TEGRA186_CPUFREQ
>   
>   config ARM_TEGRA194_CPUFREQ
>   	tristate "Tegra194 CPUFreq support"
> -	depends on ARCH_TEGRA_194_SOC || ARCH_TEGRA_234_SOC
> +	depends on ARCH_TEGRA_194_SOC || ARCH_TEGRA_234_SOC || ARCH_TEGRA_264_SOC
>   	depends on TEGRA_BPMP
> -	default ARCH_TEGRA_194_SOC || ARCH_TEGRA_234_SOC
> +	default ARCH_TEGRA_194_SOC || ARCH_TEGRA_234_SOC || ARCH_TEGRA_264_SOC
>   	help
>   	  This adds CPU frequency driver support for Tegra194 SOCs.
>   
> diff --git a/drivers/cpufreq/tegra194-cpufreq.c b/drivers/cpufreq/tegra194-cpufreq.c
> index 1328aa0a1bd1..0767a6fd6bdc 100644
> --- a/drivers/cpufreq/tegra194-cpufreq.c
> +++ b/drivers/cpufreq/tegra194-cpufreq.c
> @@ -14,7 +14,9 @@
>   #include <linux/slab.h>
>   #include <linux/units.h>
>   
> +#include <asm/arch_timer.h>
>   #include <asm/cputype.h>
> +#include <asm/sysreg.h>
>   
>   #include <soc/tegra/bpmp.h>
>   #include <soc/tegra/bpmp-abi.h>
> @@ -36,6 +38,18 @@
>   			(data->regs + (MMCRAB_CLUSTER_BASE(cl) + data->soc->actmon_cntr_base))
>   #define CORE_ACTMON_CNTR_REG(data, cl, cpu)	(CLUSTER_ACTMON_BASE(data, cl) + CORE_OFFSET(cpu))
>   
> +/*
> + * Tegra264 requests a frequency by writing the NDIV to a core_freq_req
> + * register in the CCPLEX register space.
> + *
> + * Two clusters that share a cluster-clock unit form a performance domain.
> + * Each domain has one core_freq_req register. The registers are grouped
> + * in blocks, two domains per block.
> + */
> +#define T264_CORE_FREQ_REQ_BLOCK_SIZE		0x400000
> +#define T264_CORE_FREQ_REQ_BLOCK_DOMAIN0_OFFSET	0x40000
> +#define T264_CORE_FREQ_REQ_BLOCK_DOMAIN1_OFFSET	0x50000
> +
>   /* cpufreq transisition latency */
>   #define TEGRA_CPUFREQ_TRANSITION_LATENCY (300 * 1000) /* unit in nanoseconds */
>   
> @@ -70,6 +84,8 @@ struct tegra_cpufreq_ops {
>   struct tegra_cpufreq_soc {
>   	struct tegra_cpufreq_ops *ops;
>   	u64 cnt_mask;
> +	/* AMU's constant counter ticks at the system counter rate. */
> +	bool ref_clk_from_cntfrq;
>   	int maxcpus_per_cluster;
>   	unsigned int num_clusters;
>   	bool needs_mmio;
> @@ -79,8 +95,10 @@ struct tegra_cpufreq_soc {
>   
>   struct tegra194_cpufreq_data {
>   	void __iomem *regs;
> +	resource_size_t regs_size;
>   	struct cpufreq_frequency_table **bpmp_luts;
>   	const struct tegra_cpufreq_soc *soc;
> +	u32 ref_clk_mhz;
>   	bool icc_dram_bw_scaling;
>   	struct tegra_cpu_data *cpu_data;
>   	enum cpuhp_state cpuhp_state;
> @@ -240,6 +258,78 @@ static const struct tegra_cpufreq_soc tegra238_cpufreq_soc = {
>   	.refclk_delta_min = 16000,
>   };
>   
> +static void __iomem *tegra264_core_freq_req_reg(struct tegra194_cpufreq_data *data,
> +						u32 clkid)
> +{
> +	u64 offset = (u64)(clkid / 2) * T264_CORE_FREQ_REQ_BLOCK_SIZE;
> +
> +	offset += (clkid % 2) ? T264_CORE_FREQ_REQ_BLOCK_DOMAIN1_OFFSET :
> +				T264_CORE_FREQ_REQ_BLOCK_DOMAIN0_OFFSET;
> +
> +	/*
> +	 * clkid comes from the device tree. Reject an index whose 32-bit
> +	 * register does not fit in the mapped region.
> +	 */
> +	if (offset + sizeof(u32) > data->regs_size)
> +		return NULL;
> +
> +	return data->regs + offset;
> +}
> +
> +static int tegra264_get_cpu_ndiv(u32 cpu, u32 cpuid, u32 clusterid, u64 *ndiv)
> +{
> +	struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
> +	u32 clkid = data->cpu_data[cpu].clkid;
> +	void __iomem *reg;
> +
> +	reg = tegra264_core_freq_req_reg(data, clkid);
> +	if (!reg)
> +		return -EINVAL;
> +
> +	*ndiv = readl(reg) & NDIV_MASK;
> +
> +	return 0;
> +}
> +
> +static void tegra264_set_cpu_ndiv(struct cpufreq_policy *policy, u64 ndiv)
> +{
> +	struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
> +	u32 clkid = data->cpu_data[policy->cpu].clkid;
> +	void __iomem *reg;
> +
> +	reg = tegra264_core_freq_req_reg(data, clkid);
> +	if (reg)
> +		writel(ndiv, reg);
> +}
> +
> +/*
> + * The AMU counters are per-CPU system registers, so this must run on the CPU
> + * it samples. tegra194_calculate_speed() queues it there with queue_work_on().
> + */
> +static void tegra264_sample_counters(struct tegra194_cpufreq_data *data,
> +				     struct tegra_cpu_ctr *c)
> +{
> +	c->coreclk_cnt = read_sysreg_s(SYS_AMEVCNTR0_CORE_EL0);
> +	c->refclk_cnt = read_sysreg_s(SYS_AMEVCNTR0_CONST_EL0);


AMU is optional, so arm64 core reads these counters only with
CONFIG_ARM64_AMU_EXTN and a per-CPU check (arch/arm64/kernel/
topology.c). Is AMU always enabled on Tegra264, or should this be gated
the same way?


-- 
Thx and BRs,
Zhongqiu Han