From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
To: Tarang Raval <tarang.raval@siliconsignals.io>,
sakari.ailus@linux.intel.com, mehdi.djait@linux.intel.com
Cc: Himanshu Bhavani <himanshu.bhavani@siliconsignals.io>,
Elgin Perumbilly <elgin.perumbilly@siliconsignals.io>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Hans Verkuil <hverkuil+cisco@kernel.org>,
linux-media@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 04/17] media: i2c: os05b10: split common and mode-specific init registers
Date: Fri, 24 Jul 2026 16:15:25 +0300 [thread overview]
Message-ID: <52c6ea74-5938-465d-ad22-4192eef658a1@linaro.org> (raw)
In-Reply-To: <20260718200912.16001-5-tarang.raval@siliconsignals.io>
On 7/18/26 23:08, Tarang Raval wrote:
> Separate common initialization registers from mode-specific settings.
> Move resolution-dependent registers into a per-mode register list and
> program them during stream enable.
>
> Signed-off-by: Tarang Raval <tarang.raval@siliconsignals.io>
> ---
> drivers/media/i2c/os05b10.c | 96 ++++++++++++++++++++++++-------------
> 1 file changed, 63 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/media/i2c/os05b10.c b/drivers/media/i2c/os05b10.c
> index 96395cd7a2ca..12c4e2610d6f 100644
> --- a/drivers/media/i2c/os05b10.c
> +++ b/drivers/media/i2c/os05b10.c
> @@ -142,16 +142,13 @@ static const struct cci_reg_sequence os05b10_common_regs[] = {
> { OS05B10_REG_EXPOSURE_SHORT, 0x000020 },
> { CCI_REG8(0x3600), 0x4d },
> { CCI_REG8(0x3601), 0x08 },
> - { CCI_REG8(0x3610), 0x87 },
> { CCI_REG8(0x3611), 0x24 },
> { CCI_REG8(0x3614), 0x4c },
> - { CCI_REG8(0x3620), 0x0c },
> { CCI_REG8(0x3632), 0x80 },
> { CCI_REG8(0x3633), 0x00 },
> { CCI_REG8(0x3636), 0xcc },
> { CCI_REG8(0x3637), 0x27 },
> { CCI_REG8(0x3660), 0x00 },
> - { CCI_REG8(0x3662), 0x10 },
> { CCI_REG8(0x3665), 0x00 },
> { CCI_REG8(0x3666), 0x00 },
> { CCI_REG8(0x366a), 0x14 },
> @@ -235,7 +232,6 @@ static const struct cci_reg_sequence os05b10_common_regs[] = {
> { CCI_REG8(0x370f), 0x1c },
> { CCI_REG8(0x3710), 0x00 },
> { CCI_REG8(0x3713), 0x00 },
> - { CCI_REG8(0x3714), 0x24 },
> { CCI_REG8(0x3716), 0x24 },
> { CCI_REG8(0x371a), 0x1e },
> { CCI_REG8(0x3724), 0x09 },
> @@ -244,7 +240,6 @@ static const struct cci_reg_sequence os05b10_common_regs[] = {
> { CCI_REG8(0x3730), 0xe1 },
> { CCI_REG8(0x3735), 0x80 },
> { CCI_REG8(0x3739), 0x10 },
> - { CCI_REG8(0x373f), 0xb0 },
> { CCI_REG8(0x3740), 0x28 },
> { CCI_REG8(0x3741), 0x21 },
> { CCI_REG8(0x3742), 0x21 },
> @@ -290,8 +285,6 @@ static const struct cci_reg_sequence os05b10_common_regs[] = {
> { CCI_REG8(0x37ac), 0xa0 },
> { CCI_REG8(0x37be), 0x0a },
> { CCI_REG8(0x37bb), 0x02 },
> - { CCI_REG8(0x37bf), 0x05 },
> - { CCI_REG8(0x37c2), 0x04 },
> { CCI_REG8(0x37c4), 0x11 },
> { CCI_REG8(0x37c5), 0x80 },
> { CCI_REG8(0x37c6), 0x14 },
> @@ -300,7 +293,6 @@ static const struct cci_reg_sequence os05b10_common_regs[] = {
> { CCI_REG8(0x37cd), 0x17 },
> { CCI_REG8(0x37ce), 0x01 },
> { CCI_REG8(0x37d8), 0x02 },
> - { CCI_REG8(0x37d9), 0x08 },
> { CCI_REG8(0x37dc), 0x01 },
> { CCI_REG8(0x37e0), 0x0c },
> { CCI_REG8(0x37e1), 0x20 },
> @@ -313,25 +305,10 @@ static const struct cci_reg_sequence os05b10_common_regs[] = {
> { CCI_REG8(0x37f5), 0x00 },
> { CCI_REG8(0x37f6), 0x00 },
> { CCI_REG8(0x37f7), 0x00 },
> - { OS05B10_REG_X_ADDR_START, 0x0130 },
> - { OS05B10_REG_Y_ADDR_START, 0x0000 },
> - { OS05B10_REG_X_ADDR_END, 0x0b5f },
> - { OS05B10_REG_Y_ADDR_END, 0x07a7 },
> - { OS05B10_REG_X_OUTPUT_SIZE, 0x0a20 },
> - { OS05B10_REG_Y_OUTPUT_SIZE, 0x0798 },
> - { OS05B10_REG_HTS, 0x06d0 },
> - { OS05B10_REG_ISP_X_WIN, 0x0008 },
> - { OS05B10_REG_ISP_Y_WIN, 0x0008 },
> - { OS05B10_REG_X_INC_ODD, 0x01 },
> - { OS05B10_REG_X_INC_EVEN, 0x01 },
> - { OS05B10_REG_Y_INC_ODD, 0x01 },
> - { OS05B10_REG_Y_INC_EVEN, 0x01 },
> { CCI_REG8(0x3818), 0x00 },
> { CCI_REG8(0x3819), 0x00 },
> { CCI_REG8(0x381a), 0x00 },
> { CCI_REG8(0x381b), 0x01 },
> - { OS05B10_REG_FORMAT1, 0x88 },
> - { OS05B10_REG_FORMAT2, 0x00 },
> { CCI_REG8(0x3822), 0x12 },
> { CCI_REG8(0x3823), 0x08 },
> { CCI_REG8(0x3824), 0x00 },
> @@ -341,7 +318,6 @@ static const struct cci_reg_sequence os05b10_common_regs[] = {
> { CCI_REG8(0x3829), 0x03 },
> { CCI_REG8(0x382a), 0x00 },
> { CCI_REG8(0x382b), 0x00 },
> - { CCI_REG8(0x3832), 0x08 },
> { CCI_REG8(0x3838), 0x00 },
> { CCI_REG8(0x3839), 0x00 },
> { CCI_REG8(0x383a), 0x00 },
> @@ -362,26 +338,19 @@ static const struct cci_reg_sequence os05b10_common_regs[] = {
> { CCI_REG8(0x38a7), 0x04 },
> { CCI_REG8(0x38b8), 0x02 },
> { CCI_REG8(0x3c80), 0x3e },
> - { CCI_REG8(0x3c86), 0x01 },
> { CCI_REG8(0x3c87), 0x02 },
> { CCI_REG8(0x389c), 0x00 },
> { CCI_REG8(0x3ca2), 0x0c },
> { CCI_REG8(0x3d85), 0x1b },
> - { CCI_REG8(0x3d8c), 0x01 },
> { CCI_REG8(0x3d8d), 0xe2 },
> { CCI_REG8(0x3f00), 0xcb },
> - { CCI_REG8(0x3f03), 0x08 },
> { CCI_REG8(0x3f9e), 0x07 },
> { CCI_REG8(0x3f9f), 0x04 },
> { CCI_REG8(0x4000), 0xf3 },
> { CCI_REG8(0x4002), 0x00 },
> { CCI_REG8(0x4003), 0x40 },
> - { CCI_REG8(0x4008), 0x02 },
> - { CCI_REG8(0x4009), 0x0d },
> - { CCI_REG8(0x400a), 0x01 },
> { CCI_REG8(0x400b), 0x00 },
> { CCI_REG8(0x4040), 0x00 },
> - { CCI_REG8(0x4041), 0x07 },
> { CCI_REG8(0x4090), 0x14 },
> { CCI_REG8(0x40b0), 0x01 },
> { CCI_REG8(0x40b1), 0x01 },
> @@ -401,7 +370,6 @@ static const struct cci_reg_sequence os05b10_common_regs[] = {
> { CCI_REG8(0x4305), 0x83 },
> { CCI_REG8(0x4306), 0x21 },
> { CCI_REG8(0x430d), 0x00 },
> - { CCI_REG8(0x4505), 0xc4 },
> { CCI_REG8(0x4506), 0x00 },
> { CCI_REG8(0x4507), 0x60 },
> { CCI_REG8(0x4803), 0x00 },
> @@ -413,7 +381,6 @@ static const struct cci_reg_sequence os05b10_common_regs[] = {
> { CCI_REG8(0x481f), 0x30 },
> { CCI_REG8(0x4825), 0x34 },
> { CCI_REG8(0x4829), 0x64 },
> - { CCI_REG8(0x4837), 0x12 },
> { CCI_REG8(0x484b), 0x07 },
> { CCI_REG8(0x4883), 0x36 },
> { CCI_REG8(0x4885), 0x03 },
> @@ -446,6 +413,42 @@ static const struct cci_reg_sequence os05b10_common_regs[] = {
> { CCI_REG8(0x3222), 0x03 },
> };
>
> +static const struct cci_reg_sequence mode_2592_1944_regs[] = {
> + { OS05B10_REG_X_ADDR_START, 0x0130 },
> + { OS05B10_REG_Y_ADDR_START, 0x0000 },
> + { OS05B10_REG_X_ADDR_END, 0x0b5f },
> + { OS05B10_REG_Y_ADDR_END, 0x07a7 },
> + { OS05B10_REG_X_OUTPUT_SIZE, 0x0a20 },
> + { OS05B10_REG_Y_OUTPUT_SIZE, 0x0798 },
> + { OS05B10_REG_HTS, 0x06d0 },
> + { OS05B10_REG_ISP_X_WIN, 0x0008 },
> + { OS05B10_REG_ISP_Y_WIN, 0x0008 },
> + { OS05B10_REG_X_INC_ODD, 0x01 },
> + { OS05B10_REG_X_INC_EVEN, 0x01 },
> + { OS05B10_REG_Y_INC_ODD, 0x01 },
> + { OS05B10_REG_Y_INC_EVEN, 0x01 },
> + { OS05B10_REG_FORMAT1, 0x88 },
> + { OS05B10_REG_FORMAT2, 0x00 },
> + { CCI_REG8(0x3610), 0x87 },
> + { CCI_REG8(0x3620), 0x0c },
> + { CCI_REG8(0x3662), 0x10 },
> + { CCI_REG8(0x3714), 0x24 },
> + { CCI_REG8(0x373f), 0xb0 },
> + { CCI_REG8(0x37bf), 0x05 },
> + { CCI_REG8(0x37c2), 0x04 },
> + { CCI_REG8(0x37d9), 0x08 },
> + { CCI_REG8(0x3832), 0x08 },
> + { CCI_REG8(0x3c86), 0x01 },
> + { CCI_REG8(0x3d8c), 0x01 },
> + { CCI_REG8(0x3f03), 0x08 },
> + { CCI_REG8(0x4008), 0x02 },
> + { CCI_REG8(0x4009), 0x0d },
> + { CCI_REG8(0x400a), 0x01 },
> + { CCI_REG8(0x4041), 0x07 },
> + { CCI_REG8(0x4505), 0xc4 },
> + { CCI_REG8(0x4837), 0x12 },
> +};
> +
> struct os05b10 {
> struct device *dev;
> struct regmap *cci;
> @@ -468,6 +471,11 @@ struct os05b10 {
> u32 data_lanes;
> };
>
> +struct os05b10_reg_list {
> + u32 num_of_regs;
> + const struct cci_reg_sequence *regs;
> +};
> +
> struct os05b10_mode {
> u32 width;
> u32 height;
> @@ -475,6 +483,7 @@ struct os05b10_mode {
> u32 hts;
> u32 exp;
> u8 bpp;
> + struct os05b10_reg_list reg_list;
> };
>
> static const struct os05b10_mode supported_modes_10bit[] = {
> @@ -485,6 +494,10 @@ static const struct os05b10_mode supported_modes_10bit[] = {
> .hts = 1744,
> .exp = 1944,
> .bpp = 10,
> + .reg_list = {
> + .num_of_regs = ARRAY_SIZE(mode_2592_1944_regs),
> + .regs = mode_2592_1944_regs,
> + },
> },
> };
>
> @@ -654,8 +667,16 @@ static int os05b10_enable_streams(struct v4l2_subdev *sd,
> u32 pad, u64 streams_mask)
> {
> struct os05b10 *os05b10 = to_os05b10(sd);
> + const struct os05b10_reg_list *reg_list;
> + const struct v4l2_mbus_framefmt *fmt;
> + const struct os05b10_mode *mode;
> int ret;
>
> + fmt = v4l2_subdev_state_get_format(state, 0);
> + mode = v4l2_find_nearest_size(supported_modes_10bit,
> + ARRAY_SIZE(supported_modes_10bit), width,
> + height, fmt->width, fmt->height);
> +
> ret = pm_runtime_resume_and_get(os05b10->dev);
> if (ret < 0)
> return ret;
> @@ -668,6 +689,15 @@ static int os05b10_enable_streams(struct v4l2_subdev *sd,
> goto err_rpm_put;
> }
>
> + /* Write sensor mode registers */
> + reg_list = &mode->reg_list;
> + ret = cci_multi_reg_write(os05b10->cci, reg_list->regs,
> + reg_list->num_of_regs, NULL);
> + if (ret) {
> + dev_err(os05b10->dev, "fail to write initial registers\n");
> + goto err_rpm_put;
> + }
> +
> /* Apply customized user controls */
> ret = __v4l2_ctrl_handler_setup(os05b10->sd.ctrl_handler);
> if (ret)
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
--
Best wishes,
Vladimir
next prev parent reply other threads:[~2026-07-24 13:15 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-18 20:08 [PATCH v3 00/17] media: i2c: os05b10: Refactor driver and Add new features Tarang Raval
2026-07-18 20:08 ` [PATCH v3 01/17] media: i2c: os05b10: Use pm_runtime_get_if_active() when applying controls Tarang Raval
2026-07-22 5:58 ` Jai Luthra
2026-07-24 6:47 ` Tarang Raval
2026-07-18 20:08 ` [PATCH v3 02/17] media: i2c: os05b10: drop unused group-hold programming Tarang Raval
2026-07-18 20:08 ` [PATCH v3 03/17] media: i2c: os05b10: add register definitions and use them in init table Tarang Raval
2026-07-21 17:25 ` Mehdi Djait
2026-07-24 13:09 ` Vladimir Zapolskiy
2026-07-18 20:08 ` [PATCH v3 04/17] media: i2c: os05b10: split common and mode-specific init registers Tarang Raval
2026-07-21 17:40 ` Mehdi Djait
2026-07-24 13:15 ` Vladimir Zapolskiy [this message]
2026-07-18 20:08 ` [PATCH v3 05/17] media: i2c: os05b10: add V4L2 digital gain control Tarang Raval
2026-07-24 13:19 ` Vladimir Zapolskiy
2026-07-24 14:15 ` Tarang Raval
2026-07-18 20:08 ` [PATCH v3 06/17] media: i2c: os05b10: Add H/V flip support Tarang Raval
2026-07-21 17:43 ` Mehdi Djait
2026-07-22 5:51 ` Jai Luthra
2026-07-24 7:01 ` Tarang Raval
2026-07-24 13:27 ` Vladimir Zapolskiy
2026-07-18 20:08 ` [PATCH v3 07/17] media: i2c: os05b10: Add test pattern options Tarang Raval
2026-07-21 17:50 ` Mehdi Djait
2026-07-24 13:43 ` Vladimir Zapolskiy
2026-07-18 20:08 ` [PATCH v3 08/17] media: i2c: os05b10: add 12-bit RAW mode support Tarang Raval
2026-07-24 14:08 ` Vladimir Zapolskiy
2026-07-24 14:30 ` Tarang Raval
2026-07-24 15:03 ` Vladimir Zapolskiy
2026-07-18 20:09 ` [PATCH v3 09/17] media: i2c: os05b10: update pixel rate on 10/12-bit mode switch Tarang Raval
2026-07-22 6:17 ` Jai Luthra
2026-07-22 6:19 ` Jai Luthra
2026-07-24 9:08 ` Tarang Raval
2026-07-25 7:26 ` Vladimir Zapolskiy
2026-07-18 20:09 ` [PATCH v3 10/17] media: i2c: os05b10: Add 1080p and 2x2 binning 720p modes Tarang Raval
2026-07-22 6:05 ` Jai Luthra
2026-07-24 6:44 ` Tarang Raval
2026-07-18 20:09 ` [PATCH v3 11/17] media: i2c: os05b10: keep vblank and exposure range in sync on mode switch Tarang Raval
2026-07-25 7:30 ` Vladimir Zapolskiy
2026-07-18 20:09 ` [PATCH v3 12/17] media: i2c: os05b10: Update active format before adjusting framing controls Tarang Raval
2026-07-25 7:32 ` Vladimir Zapolskiy
2026-07-18 20:09 ` [PATCH v3 13/17] media: i2c: os05b10: Rename vmax variable in VBLANK control Tarang Raval
2026-07-25 7:33 ` Vladimir Zapolskiy
2026-07-18 20:09 ` [PATCH v3 14/17] media: i2c: os05b10: add 2-lane support Tarang Raval
2026-07-25 7:38 ` Vladimir Zapolskiy
2026-07-18 20:09 ` [PATCH v3 15/17] media: i2c: os05b10: fix negative hblank calculation Tarang Raval
2026-07-22 6:14 ` Jai Luthra
2026-07-24 8:14 ` Tarang Raval
2026-07-18 20:09 ` [PATCH v3 16/17] media: i2c: os05b10: Enable runtime PM autosuspend Tarang Raval
2026-07-22 6:08 ` Jai Luthra
2026-07-24 7:02 ` Tarang Raval
2026-07-24 9:58 ` Jai Luthra
2026-07-18 20:09 ` [PATCH v3 17/17] media: i2c: os05b10: remove unused control fields, simplify error handling Tarang Raval
2026-07-25 11:33 ` Vladimir Zapolskiy
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