* [PATCH 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document Glymur QMP UFS PHY
2026-09-11 16:47 [PATCH 0/5] Add UFS support for Glymur Qualcomm SoC Pradeep P V K
@ 2026-09-11 16:47 ` Pradeep P V K
2026-09-11 16:47 ` [PATCH 2/5] scsi: ufs: qcom: dt-bindings: Document Glymur UFS controller Pradeep P V K
` (3 subsequent siblings)
4 siblings, 0 replies; 15+ messages in thread
From: Pradeep P V K @ 2026-09-11 16:47 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Alim Akhtar, Avri Altman,
Bart Van Assche, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, gopikrishna.garmidi, jagadeesh.kona
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, sibi.sankar, Taniya Das, Pradeep P V K
Document the QMP UFS PHY on Glymur SoC.
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
---
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
index 4efe40c0dc97..e1b19ed42542 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
@@ -38,6 +38,7 @@ properties:
- qcom,kaanapali-qmp-ufs-phy
- const: qcom,sm8750-qmp-ufs-phy
- enum:
+ - qcom,glymur-qmp-ufs-phy
- qcom,hawi-qmp-ufs-phy
- qcom,milos-qmp-ufs-phy
- qcom,msm8996-qmp-ufs-phy
@@ -109,6 +110,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,glymur-qmp-ufs-phy
- qcom,hawi-qmp-ufs-phy
- qcom,milos-qmp-ufs-phy
- qcom,msm8998-qmp-ufs-phy
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 2/5] scsi: ufs: qcom: dt-bindings: Document Glymur UFS controller
2026-09-11 16:47 [PATCH 0/5] Add UFS support for Glymur Qualcomm SoC Pradeep P V K
2026-09-11 16:47 ` [PATCH 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document Glymur QMP UFS PHY Pradeep P V K
@ 2026-09-11 16:47 ` Pradeep P V K
2026-09-11 16:47 ` [PATCH 3/5] arm64: dts: qcom: glymur: Add UFS nodes Pradeep P V K
` (2 subsequent siblings)
4 siblings, 0 replies; 15+ messages in thread
From: Pradeep P V K @ 2026-09-11 16:47 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Alim Akhtar, Avri Altman,
Bart Van Assche, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, gopikrishna.garmidi, jagadeesh.kona
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, sibi.sankar, Taniya Das, Pradeep P V K
Document UFS Host Controller on Glymur SoC. Glymur UFSHC has a
multi-queue command (MCQ) register range in addition to the standard
one. So, both reg entries are required.
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
---
Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml
index d03295806657..f132b1a9ebc2 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml
@@ -16,6 +16,7 @@ select:
contains:
enum:
- qcom,eliza-ufshc
+ - qcom,glymur-ufshc
- qcom,hawi-ufshc
- qcom,kaanapali-ufshc
- qcom,maili-ufshc
@@ -30,6 +31,7 @@ properties:
items:
- enum:
- qcom,eliza-ufshc
+ - qcom,glymur-ufshc
- qcom,hawi-ufshc
- qcom,kaanapali-ufshc
- qcom,maili-ufshc
@@ -80,6 +82,7 @@ allOf:
contains:
enum:
- qcom,eliza-ufshc
+ - qcom,glymur-ufshc
- qcom,maili-ufshc
- qcom,nord-ufshc
then:
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 3/5] arm64: dts: qcom: glymur: Add UFS nodes
2026-09-11 16:47 [PATCH 0/5] Add UFS support for Glymur Qualcomm SoC Pradeep P V K
2026-09-11 16:47 ` [PATCH 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document Glymur QMP UFS PHY Pradeep P V K
2026-09-11 16:47 ` [PATCH 2/5] scsi: ufs: qcom: dt-bindings: Document Glymur UFS controller Pradeep P V K
@ 2026-09-11 16:47 ` Pradeep P V K
2026-09-14 9:14 ` Konrad Dybcio
2026-09-14 14:06 ` Abel Vesa
2026-09-11 16:47 ` [PATCH 4/5] arm64: dts: qcom: glymur-qcb: Enable UFS Pradeep P V K
2026-09-11 16:47 ` [PATCH 5/5] phy: qcom-qmp-ufs: Add Glymur support Pradeep P V K
4 siblings, 2 replies; 15+ messages in thread
From: Pradeep P V K @ 2026-09-11 16:47 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Alim Akhtar, Avri Altman,
Bart Van Assche, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, gopikrishna.garmidi, jagadeesh.kona
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, sibi.sankar, Taniya Das, Pradeep P V K
Add UFS PHY and UFS host controller nodes for Glymur SoC.
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 114 ++++++++++++++++++++++++++++++++++-
1 file changed, 111 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 624a9edd602c..7bbc804ed340 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -812,9 +812,9 @@ gcc: clock-controller@100000 {
<0>, /* QUSB4 1 PHY RX 1 */
<0>, /* QUSB4 2 PHY RX 0 */
<0>, /* QUSB4 2 PHY RX 1 */
- <0>, /* UFS PHY RX Symbol 0 */
- <0>, /* UFS PHY RX Symbol 1 */
- <0>, /* UFS PHY TX Symbol 0 */
+ <&ufs_mem_phy 0>, /* UFS PHY RX Symbol 0 */
+ <&ufs_mem_phy 1>, /* UFS PHY RX Symbol 1 */
+ <&ufs_mem_phy 2>, /* UFS PHY TX Symbol 0 */
<&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
<&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
<&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
@@ -4103,6 +4103,114 @@ rng: rng@10c3000 {
reg = <0x0 0x010c3000 0x0 0x1000>;
};
+ ufs_mem_phy: phy@1d80000 {
+ compatible = "qcom,glymur-qmp-ufs-phy";
+ reg = <0x0 0x01d80000 0x0 0x2000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ /* UFS and PCIE4 shares the same clkref on glymur */
+ <&tcsr TCSR_PCIE_4_CLKREF_EN>;
+
+ clock-names = "ref",
+ "ref_aux",
+ "qref";
+
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ ufs_mem_hc: ufshc@1d84000 {
+ compatible = "qcom,glymur-ufshc",
+ "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0x0 0x01d84000 0x0 0x3000>,
+ <0x0 0x01da0000 0x0 0x15000>;
+
+ reg-names = "std",
+ "mcq";
+
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_LN_BB_CLK3>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ clock-names = "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+
+ operating-points-v2 = <&ufs_opp_table>;
+
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ interconnects = <&aggre2_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "ufs-ddr",
+ "cpu-ufs";
+
+ power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ iommus = <&apps_smmu 0x460 0>;
+ dma-coherent;
+
+ msi-parent = <&gic_its 0x460>;
+ lanes-per-direction = <2>;
+
+ phys = <&ufs_mem_phy>;
+ phy-names = "ufsphy";
+
+ #reset-cells = <1>;
+
+ status = "disabled";
+
+ ufs_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <100000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-403000000 {
+ opp-hz = /bits/ 64 <403000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <403000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x0 0x01dc4000 0x0 0x28000>;
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 3/5] arm64: dts: qcom: glymur: Add UFS nodes
2026-09-11 16:47 ` [PATCH 3/5] arm64: dts: qcom: glymur: Add UFS nodes Pradeep P V K
@ 2026-09-14 9:14 ` Konrad Dybcio
2026-09-16 14:47 ` Pradeep Pragallapati
2026-09-14 14:06 ` Abel Vesa
1 sibling, 1 reply; 15+ messages in thread
From: Konrad Dybcio @ 2026-09-14 9:14 UTC (permalink / raw)
To: Pradeep P V K, Vinod Koul, Neil Armstrong, Manivannan Sadhasivam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alim Akhtar,
Avri Altman, Bart Van Assche, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, gopikrishna.garmidi, jagadeesh.kona
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, sibi.sankar, Taniya Das
On 9/11/26 6:47 PM, Pradeep P V K wrote:
> Add UFS PHY and UFS host controller nodes for Glymur SoC.
>
> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 114 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 111 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index 624a9edd602c..7bbc804ed340 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -812,9 +812,9 @@ gcc: clock-controller@100000 {
> <0>, /* QUSB4 1 PHY RX 1 */
> <0>, /* QUSB4 2 PHY RX 0 */
> <0>, /* QUSB4 2 PHY RX 1 */
> - <0>, /* UFS PHY RX Symbol 0 */
> - <0>, /* UFS PHY RX Symbol 1 */
> - <0>, /* UFS PHY TX Symbol 0 */
> + <&ufs_mem_phy 0>, /* UFS PHY RX Symbol 0 */
> + <&ufs_mem_phy 1>, /* UFS PHY RX Symbol 1 */
> + <&ufs_mem_phy 2>, /* UFS PHY TX Symbol 0 */
The comment is no useful, please drop it
> <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
> <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
> <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
> @@ -4103,6 +4103,114 @@ rng: rng@10c3000 {
> reg = <0x0 0x010c3000 0x0 0x1000>;
> };
>
> + ufs_mem_phy: phy@1d80000 {
> + compatible = "qcom,glymur-qmp-ufs-phy";
> + reg = <0x0 0x01d80000 0x0 0x2000>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> + /* UFS and PCIE4 shares the same clkref on glymur */
s/shares/share
> + <&tcsr TCSR_PCIE_4_CLKREF_EN>;
> +
> + clock-names = "ref",
> + "ref_aux",
> + "qref";
> +
> + resets = <&ufs_mem_hc 0>;
> + reset-names = "ufsphy";
> +
> + #clock-cells = <1>;
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + ufs_mem_hc: ufshc@1d84000 {
> + compatible = "qcom,glymur-ufshc",
> + "qcom,ufshc",
> + "jedec,ufs-2.0";
> + reg = <0x0 0x01d84000 0x0 0x3000>,
> + <0x0 0x01da0000 0x0 0x15000>;
> +
> + reg-names = "std",
Stray \n above
[...]
> + ufs_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-100000000 {
> + opp-hz = /bits/ 64 <100000000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <100000000>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>,
> + /bits/ 64 <0>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-403000000 {
There's another (201.5 MHz) OPP at SVS
Konrad
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 3/5] arm64: dts: qcom: glymur: Add UFS nodes
2026-09-14 9:14 ` Konrad Dybcio
@ 2026-09-16 14:47 ` Pradeep Pragallapati
0 siblings, 0 replies; 15+ messages in thread
From: Pradeep Pragallapati @ 2026-09-16 14:47 UTC (permalink / raw)
To: Konrad Dybcio, Vinod Koul, Neil Armstrong, Manivannan Sadhasivam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alim Akhtar,
Avri Altman, Bart Van Assche, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, gopikrishna.garmidi, jagadeesh.kona
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, sibi.sankar, Taniya Das
On 9/14/2026 2:44 PM, Konrad Dybcio wrote:
> On 9/11/26 6:47 PM, Pradeep P V K wrote:
>> Add UFS PHY and UFS host controller nodes for Glymur SoC.
>>
>> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/glymur.dtsi | 114 ++++++++++++++++++++++++++++++++++-
>> 1 file changed, 111 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
>> index 624a9edd602c..7bbc804ed340 100644
>> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
>> @@ -812,9 +812,9 @@ gcc: clock-controller@100000 {
>> <0>, /* QUSB4 1 PHY RX 1 */
>> <0>, /* QUSB4 2 PHY RX 0 */
>> <0>, /* QUSB4 2 PHY RX 1 */
>> - <0>, /* UFS PHY RX Symbol 0 */
>> - <0>, /* UFS PHY RX Symbol 1 */
>> - <0>, /* UFS PHY TX Symbol 0 */
>> + <&ufs_mem_phy 0>, /* UFS PHY RX Symbol 0 */
>> + <&ufs_mem_phy 1>, /* UFS PHY RX Symbol 1 */
>> + <&ufs_mem_phy 2>, /* UFS PHY TX Symbol 0 */
>
> The comment is no useful, please drop it
sure, i will remove it in my next patchset.>
>
>> <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
>> <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
>> <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
>> @@ -4103,6 +4103,114 @@ rng: rng@10c3000 {
>> reg = <0x0 0x010c3000 0x0 0x1000>;
>> };
>>
>> + ufs_mem_phy: phy@1d80000 {
>> + compatible = "qcom,glymur-qmp-ufs-phy";
>> + reg = <0x0 0x01d80000 0x0 0x2000>;
>> +
>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>> + /* UFS and PCIE4 shares the same clkref on glymur */
>
> s/shares/share
ok, i will change this in my next patchset.>
>> + <&tcsr TCSR_PCIE_4_CLKREF_EN>;
>> +
>> + clock-names = "ref",
>> + "ref_aux",
>> + "qref";
>> +
>> + resets = <&ufs_mem_hc 0>;
>> + reset-names = "ufsphy";
>> +
>> + #clock-cells = <1>;
>> + #phy-cells = <0>;
>> +
>> + status = "disabled";
>> + };
>> +
>> + ufs_mem_hc: ufshc@1d84000 {
>> + compatible = "qcom,glymur-ufshc",
>> + "qcom,ufshc",
>> + "jedec,ufs-2.0";
>> + reg = <0x0 0x01d84000 0x0 0x3000>,
>> + <0x0 0x01da0000 0x0 0x15000>;
>> +
>> + reg-names = "std",
>
> Stray \n above
>
sure, will remove it in my next patchset version.
> [...]
>
>> + ufs_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-100000000 {
>> + opp-hz = /bits/ 64 <100000000>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <100000000>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>,
>> + /bits/ 64 <0>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + };
>> +
>> + opp-403000000 {
>
> There's another (201.5 MHz) OPP at SVS
>
acknowledged, i will add it in my next patchset.
> Konrad
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/5] arm64: dts: qcom: glymur: Add UFS nodes
2026-09-11 16:47 ` [PATCH 3/5] arm64: dts: qcom: glymur: Add UFS nodes Pradeep P V K
2026-09-14 9:14 ` Konrad Dybcio
@ 2026-09-14 14:06 ` Abel Vesa
2026-09-16 14:48 ` Pradeep Pragallapati
1 sibling, 1 reply; 15+ messages in thread
From: Abel Vesa @ 2026-09-14 14:06 UTC (permalink / raw)
To: Pradeep P V K
Cc: Vinod Koul, Neil Armstrong, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Alim Akhtar, Avri Altman,
Bart Van Assche, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, gopikrishna.garmidi, jagadeesh.kona,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, sibi.sankar, Taniya Das
On 26-09-11 22:17:07, Pradeep P V K wrote:
> Add UFS PHY and UFS host controller nodes for Glymur SoC.
>
> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
One nit below.
With Konrad's comments addressed, I think it looks good, so:
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 114 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 111 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index 624a9edd602c..7bbc804ed340 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -812,9 +812,9 @@ gcc: clock-controller@100000 {
> <0>, /* QUSB4 1 PHY RX 1 */
> <0>, /* QUSB4 2 PHY RX 0 */
> <0>, /* QUSB4 2 PHY RX 1 */
> - <0>, /* UFS PHY RX Symbol 0 */
> - <0>, /* UFS PHY RX Symbol 1 */
> - <0>, /* UFS PHY TX Symbol 0 */
> + <&ufs_mem_phy 0>, /* UFS PHY RX Symbol 0 */
> + <&ufs_mem_phy 1>, /* UFS PHY RX Symbol 1 */
> + <&ufs_mem_phy 2>, /* UFS PHY TX Symbol 0 */
> <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
> <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
> <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
> @@ -4103,6 +4103,114 @@ rng: rng@10c3000 {
> reg = <0x0 0x010c3000 0x0 0x1000>;
> };
>
> + ufs_mem_phy: phy@1d80000 {
> + compatible = "qcom,glymur-qmp-ufs-phy";
> + reg = <0x0 0x01d80000 0x0 0x2000>;
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> + /* UFS and PCIE4 shares the same clkref on glymur */
On top of Konrad's comment, I'd drop the "on glymur" part entirely here.
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 3/5] arm64: dts: qcom: glymur: Add UFS nodes
2026-09-14 14:06 ` Abel Vesa
@ 2026-09-16 14:48 ` Pradeep Pragallapati
0 siblings, 0 replies; 15+ messages in thread
From: Pradeep Pragallapati @ 2026-09-16 14:48 UTC (permalink / raw)
To: Abel Vesa
Cc: Vinod Koul, Neil Armstrong, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Alim Akhtar, Avri Altman,
Bart Van Assche, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, gopikrishna.garmidi, jagadeesh.kona,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, sibi.sankar, Taniya Das
On 9/14/2026 7:36 PM, Abel Vesa wrote:
> On 26-09-11 22:17:07, Pradeep P V K wrote:
>> Add UFS PHY and UFS host controller nodes for Glymur SoC.
>>
>> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
>
> One nit below.
>
> With Konrad's comments addressed, I think it looks good, so:
>
> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>
>> ---
>> arch/arm64/boot/dts/qcom/glymur.dtsi | 114 ++++++++++++++++++++++++++++++++++-
>> 1 file changed, 111 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
>> index 624a9edd602c..7bbc804ed340 100644
>> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
>> @@ -812,9 +812,9 @@ gcc: clock-controller@100000 {
>> <0>, /* QUSB4 1 PHY RX 1 */
>> <0>, /* QUSB4 2 PHY RX 0 */
>> <0>, /* QUSB4 2 PHY RX 1 */
>> - <0>, /* UFS PHY RX Symbol 0 */
>> - <0>, /* UFS PHY RX Symbol 1 */
>> - <0>, /* UFS PHY TX Symbol 0 */
>> + <&ufs_mem_phy 0>, /* UFS PHY RX Symbol 0 */
>> + <&ufs_mem_phy 1>, /* UFS PHY RX Symbol 1 */
>> + <&ufs_mem_phy 2>, /* UFS PHY TX Symbol 0 */
>> <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
>> <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
>> <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
>> @@ -4103,6 +4103,114 @@ rng: rng@10c3000 {
>> reg = <0x0 0x010c3000 0x0 0x1000>;
>> };
>>
>> + ufs_mem_phy: phy@1d80000 {
>> + compatible = "qcom,glymur-qmp-ufs-phy";
>> + reg = <0x0 0x01d80000 0x0 0x2000>;
>> +
>> + clocks = <&rpmhcc RPMH_CXO_CLK>,
>> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>> + /* UFS and PCIE4 shares the same clkref on glymur */
>
> On top of Konrad's comment, I'd drop the "on glymur" part entirely here.
sure, i will remove it in my next patchset.
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 4/5] arm64: dts: qcom: glymur-qcb: Enable UFS
2026-09-11 16:47 [PATCH 0/5] Add UFS support for Glymur Qualcomm SoC Pradeep P V K
` (2 preceding siblings ...)
2026-09-11 16:47 ` [PATCH 3/5] arm64: dts: qcom: glymur: Add UFS nodes Pradeep P V K
@ 2026-09-11 16:47 ` Pradeep P V K
2026-09-14 9:14 ` Konrad Dybcio
2026-09-14 14:04 ` Abel Vesa
2026-09-11 16:47 ` [PATCH 5/5] phy: qcom-qmp-ufs: Add Glymur support Pradeep P V K
4 siblings, 2 replies; 15+ messages in thread
From: Pradeep P V K @ 2026-09-11 16:47 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Alim Akhtar, Avri Altman,
Bart Van Assche, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, gopikrishna.garmidi, jagadeesh.kona
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, sibi.sankar, Taniya Das, Pradeep P V K
Enable UFS for glymur-qcb board.
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-qcb.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur-qcb.dts b/arch/arm64/boot/dts/qcom/glymur-qcb.dts
index 17d8ff3aed23..b6e384024dff 100644
--- a/arch/arm64/boot/dts/qcom/glymur-qcb.dts
+++ b/arch/arm64/boot/dts/qcom/glymur-qcb.dts
@@ -697,3 +697,21 @@ bluetooth {
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
};
};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l1c_e1_0p82>;
+ vdda-pll-supply = <&vreg_l4f_e1_1p08>;
+
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 250 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l17b_e0_2p4>;
+ vcc-max-microamp = <1200000>;
+ vccq-supply = <&vreg_l12b_e0_1p14>;
+ vccq-max-microamp = <1200000>;
+
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 4/5] arm64: dts: qcom: glymur-qcb: Enable UFS
2026-09-11 16:47 ` [PATCH 4/5] arm64: dts: qcom: glymur-qcb: Enable UFS Pradeep P V K
@ 2026-09-14 9:14 ` Konrad Dybcio
2026-09-16 14:49 ` Pradeep Pragallapati
2026-09-14 14:04 ` Abel Vesa
1 sibling, 1 reply; 15+ messages in thread
From: Konrad Dybcio @ 2026-09-14 9:14 UTC (permalink / raw)
To: Pradeep P V K, Vinod Koul, Neil Armstrong, Manivannan Sadhasivam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alim Akhtar,
Avri Altman, Bart Van Assche, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, gopikrishna.garmidi, jagadeesh.kona
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, sibi.sankar, Taniya Das
On 9/11/26 6:47 PM, Pradeep P V K wrote:
> Enable UFS for glymur-qcb board.
>
> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur-qcb.dts | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur-qcb.dts b/arch/arm64/boot/dts/qcom/glymur-qcb.dts
> index 17d8ff3aed23..b6e384024dff 100644
> --- a/arch/arm64/boot/dts/qcom/glymur-qcb.dts
> +++ b/arch/arm64/boot/dts/qcom/glymur-qcb.dts
> @@ -697,3 +697,21 @@ bluetooth {
> vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
> };
> };
> +
> +&ufs_mem_phy {
> + vdda-phy-supply = <&vreg_l1c_e1_0p82>;
> + vdda-pll-supply = <&vreg_l4f_e1_1p08>;
> +
> + status = "okay";
> +};
> +
> +&ufs_mem_hc {
Please keep the label references sorted alphabetically
Konrad
> + reset-gpios = <&tlmm 250 GPIO_ACTIVE_LOW>;
> +
> + vcc-supply = <&vreg_l17b_e0_2p4>;
> + vcc-max-microamp = <1200000>;
> + vccq-supply = <&vreg_l12b_e0_1p14>;
> + vccq-max-microamp = <1200000>;
> +
> + status = "okay";
> +};
>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 4/5] arm64: dts: qcom: glymur-qcb: Enable UFS
2026-09-14 9:14 ` Konrad Dybcio
@ 2026-09-16 14:49 ` Pradeep Pragallapati
0 siblings, 0 replies; 15+ messages in thread
From: Pradeep Pragallapati @ 2026-09-16 14:49 UTC (permalink / raw)
To: Konrad Dybcio, Vinod Koul, Neil Armstrong, Manivannan Sadhasivam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alim Akhtar,
Avri Altman, Bart Van Assche, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, gopikrishna.garmidi, jagadeesh.kona
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, sibi.sankar, Taniya Das
On 9/14/2026 2:44 PM, Konrad Dybcio wrote:
> On 9/11/26 6:47 PM, Pradeep P V K wrote:
>> Enable UFS for glymur-qcb board.
>>
>> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/glymur-qcb.dts | 18 ++++++++++++++++++
>> 1 file changed, 18 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/glymur-qcb.dts b/arch/arm64/boot/dts/qcom/glymur-qcb.dts
>> index 17d8ff3aed23..b6e384024dff 100644
>> --- a/arch/arm64/boot/dts/qcom/glymur-qcb.dts
>> +++ b/arch/arm64/boot/dts/qcom/glymur-qcb.dts
>> @@ -697,3 +697,21 @@ bluetooth {
>> vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
>> };
>> };
>> +
>> +&ufs_mem_phy {
>> + vdda-phy-supply = <&vreg_l1c_e1_0p82>;
>> + vdda-pll-supply = <&vreg_l4f_e1_1p08>;
>> +
>> + status = "okay";
>> +};
>> +
>> +&ufs_mem_hc {
>
> Please keep the label references sorted alphabetically
sure, i will sort it in my next patchset.>
> Konrad
>
>> + reset-gpios = <&tlmm 250 GPIO_ACTIVE_LOW>;
>> +
>> + vcc-supply = <&vreg_l17b_e0_2p4>;
>> + vcc-max-microamp = <1200000>;
>> + vccq-supply = <&vreg_l12b_e0_1p14>;
>> + vccq-max-microamp = <1200000>;
>> +
>> + status = "okay";
>> +};
>>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 4/5] arm64: dts: qcom: glymur-qcb: Enable UFS
2026-09-11 16:47 ` [PATCH 4/5] arm64: dts: qcom: glymur-qcb: Enable UFS Pradeep P V K
2026-09-14 9:14 ` Konrad Dybcio
@ 2026-09-14 14:04 ` Abel Vesa
1 sibling, 0 replies; 15+ messages in thread
From: Abel Vesa @ 2026-09-14 14:04 UTC (permalink / raw)
To: Pradeep P V K
Cc: Vinod Koul, Neil Armstrong, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Alim Akhtar, Avri Altman,
Bart Van Assche, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, gopikrishna.garmidi, jagadeesh.kona,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, sibi.sankar, Taniya Das
On 26-09-11 22:17:08, Pradeep P V K wrote:
> Enable UFS for glymur-qcb board.
>
> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
With Konrad's comment addressed, LGTM so:
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 5/5] phy: qcom-qmp-ufs: Add Glymur support
2026-09-11 16:47 [PATCH 0/5] Add UFS support for Glymur Qualcomm SoC Pradeep P V K
` (3 preceding siblings ...)
2026-09-11 16:47 ` [PATCH 4/5] arm64: dts: qcom: glymur-qcb: Enable UFS Pradeep P V K
@ 2026-09-11 16:47 ` Pradeep P V K
2026-09-14 13:49 ` Konrad Dybcio
2026-09-14 14:03 ` Abel Vesa
4 siblings, 2 replies; 15+ messages in thread
From: Pradeep P V K @ 2026-09-11 16:47 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Alim Akhtar, Avri Altman,
Bart Van Assche, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, gopikrishna.garmidi, jagadeesh.kona
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, sibi.sankar, Taniya Das, Pradeep P V K
Add the init sequence tables and config for the UFS QMP phy found in
the Glymur SoC.
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 99 +++++++++++++++++++++++++++++++++
1 file changed, 99 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index d4aca22c181e..ffef8801143a 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -93,6 +93,59 @@ static const unsigned int ufsphy_v7_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V7_PCS_UFS_POWER_DOWN_CONTROL,
};
+static const struct qmp_phy_init_tbl glymur_ufsphy_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL, 0xce),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0, 0xce),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1, 0xce),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6, 0x60),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7, 0x62),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B3, 0x9a),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B6, 0xe2),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B7, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B0, 0x1b),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B1, 0x1b),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B2, 0x98),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B3, 0x9b),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B4, 0x2a),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B5, 0x12),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B7, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B8, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0, 0x93),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1, 0x93),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2, 0x60),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3, 0x99),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4, 0x5f),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5, 0x92),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6, 0xe3),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1, 0x24),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2, 0xe0),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3, 0x99),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4, 0x5f),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5, 0x92),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6, 0xfb),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_SATURATION, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CTRL1, 0x94),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_TERM_BW_CTRL0, 0xfa),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM, 0x77),
+};
+
static const struct qmp_phy_init_tbl milos_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
@@ -1236,6 +1289,11 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
}
/* Regulator bulk data with load values for specific configurations */
+static const struct regulator_bulk_data glymur_ufsphy_vreg_l[] = {
+ { .supply = "vdda-phy", .init_load_uA = 217130 },
+ { .supply = "vdda-pll", .init_load_uA = 18340 },
+};
+
static const struct regulator_bulk_data milos_ufsphy_vreg_l[] = {
{ .supply = "vdda-phy", .init_load_uA = 140120 },
{ .supply = "vdda-pll", .init_load_uA = 18340 },
@@ -1348,6 +1406,44 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v7 = {
.rx2 = 0x3000,
};
+static const struct qmp_phy_cfg glymur_ufsphy_cfg = {
+ .lanes = 2,
+
+ .offsets = &qmp_ufs_offsets_v6,
+ .max_supported_gear = UFS_HS_G5,
+
+ .tbls = {
+ .serdes = sm8750_ufsphy_serdes,
+ .serdes_num = ARRAY_SIZE(sm8750_ufsphy_serdes),
+ .tx = sm8750_ufsphy_tx,
+ .tx_num = ARRAY_SIZE(sm8750_ufsphy_tx),
+ .rx = glymur_ufsphy_rx,
+ .rx_num = ARRAY_SIZE(glymur_ufsphy_rx),
+ .pcs = sm8750_ufsphy_pcs,
+ .pcs_num = ARRAY_SIZE(sm8750_ufsphy_pcs),
+ },
+
+ .tbls_hs_b = {
+ .pcs = sm8750_ufsphy_hs_b_pcs,
+ .pcs_num = ARRAY_SIZE(sm8750_ufsphy_hs_b_pcs),
+ },
+
+ .tbls_hs_overlay[0] = {
+ .pcs = sm8750_ufsphy_g4_pcs,
+ .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
+ },
+ .tbls_hs_overlay[1] = {
+ .pcs = sm8650_ufsphy_g5_pcs,
+ .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g5_pcs),
+ .max_gear = UFS_HS_G5,
+ },
+
+ .vreg_list = glymur_ufsphy_vreg_l,
+ .num_vregs = ARRAY_SIZE(glymur_ufsphy_vreg_l),
+ .regs = ufsphy_v6_regs_layout,
+};
+
static const struct qmp_phy_cfg milos_ufsphy_cfg = {
.lanes = 2,
@@ -2395,6 +2491,9 @@ static int qmp_ufs_probe(struct platform_device *pdev)
static const struct of_device_id qmp_ufs_of_match_table[] = {
{
+ .compatible = "qcom,glymur-qmp-ufs-phy",
+ .data = &glymur_ufsphy_cfg,
+ }, {
.compatible = "qcom,hawi-qmp-ufs-phy",
.data = &hawi_ufsphy_cfg,
}, {
--
2.34.1
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 5/5] phy: qcom-qmp-ufs: Add Glymur support
2026-09-11 16:47 ` [PATCH 5/5] phy: qcom-qmp-ufs: Add Glymur support Pradeep P V K
@ 2026-09-14 13:49 ` Konrad Dybcio
2026-09-14 14:03 ` Abel Vesa
1 sibling, 0 replies; 15+ messages in thread
From: Konrad Dybcio @ 2026-09-14 13:49 UTC (permalink / raw)
To: Pradeep P V K, Vinod Koul, Neil Armstrong, Manivannan Sadhasivam,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Alim Akhtar,
Avri Altman, Bart Van Assche, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, gopikrishna.garmidi, jagadeesh.kona
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, sibi.sankar, Taniya Das
On 9/11/26 6:47 PM, Pradeep P V K wrote:
> Add the init sequence tables and config for the UFS QMP phy found in
> the Glymur SoC.
>
> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
> ---
GPT confirms the sequences are OK and I can see that the 217 mA
load on the regulator also has some confirmation in docs. Not sure
about the other one.
in general:
Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 5/5] phy: qcom-qmp-ufs: Add Glymur support
2026-09-11 16:47 ` [PATCH 5/5] phy: qcom-qmp-ufs: Add Glymur support Pradeep P V K
2026-09-14 13:49 ` Konrad Dybcio
@ 2026-09-14 14:03 ` Abel Vesa
1 sibling, 0 replies; 15+ messages in thread
From: Abel Vesa @ 2026-09-14 14:03 UTC (permalink / raw)
To: Pradeep P V K
Cc: Vinod Koul, Neil Armstrong, Manivannan Sadhasivam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Alim Akhtar, Avri Altman,
Bart Van Assche, Bjorn Andersson, Konrad Dybcio,
Dmitry Baryshkov, gopikrishna.garmidi, jagadeesh.kona,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, sibi.sankar, Taniya Das
On 26-09-11 22:17:09, Pradeep P V K wrote:
> Add the init sequence tables and config for the UFS QMP phy found in
> the Glymur SoC.
>
> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 15+ messages in thread