* [PATCH v2 01/15] arm64: dts: qcom: qcs6490-vicharak-axon-mini: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 [PATCH v2 00/15] arm64: dts: qcom: Move PCIe phy/GPIOs to root port nodes Krishna Chaitanya Chundru
@ 2026-09-17 12:25 ` Krishna Chaitanya Chundru
2026-09-17 15:11 ` Abel Vesa
2026-09-17 12:25 ` [PATCH v2 02/15] arm64: dts: qcom: msm8998: " Krishna Chaitanya Chundru
` (13 subsequent siblings)
14 siblings, 1 reply; 42+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 12:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio
The perst/wake GPIO properties are per root port and belong in the
root port node, not in the RC controller node. Move perst-gpios/
wake-gpios from the &pcie0/&pcie1 controller overrides to the
respective &pcie0_port/&pcie1_port0 nodes, renaming perst-gpios to
reset-gpios to match the binding used in the root port context.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts b/arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts
index 141d263e6566..496b7583e4a2 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts
@@ -652,9 +652,6 @@ &ice {
};
&pcie0 {
- perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>;
pinctrl-names = "default";
@@ -668,10 +665,12 @@ &pcie0_phy {
status = "okay";
};
-&pcie1 {
- perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
+&pcie0_port {
+ reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
+};
+&pcie1 {
pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>;
pinctrl-names = "default";
@@ -685,6 +684,11 @@ &pcie1_phy {
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
+};
+
&pm7250b_adc {
channel@4d {
reg = <ADC5_AMUX_THM1_100K_PU>;
--
2.34.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 01/15] arm64: dts: qcom: qcs6490-vicharak-axon-mini: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 01/15] arm64: dts: qcom: qcs6490-vicharak-axon-mini: Move PCIe phy and GPIOs to root port node Krishna Chaitanya Chundru
@ 2026-09-17 15:11 ` Abel Vesa
0 siblings, 0 replies; 42+ messages in thread
From: Abel Vesa @ 2026-09-17 15:11 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
On 26-09-17 17:55:15, Krishna Chaitanya Chundru wrote:
> The perst/wake GPIO properties are per root port and belong in the
> root port node, not in the RC controller node. Move perst-gpios/
> wake-gpios from the &pcie0/&pcie1 controller overrides to the
> respective &pcie0_port/&pcie1_port0 nodes, renaming perst-gpios to
> reset-gpios to match the binding used in the root port context.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 02/15] arm64: dts: qcom: msm8998: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 [PATCH v2 00/15] arm64: dts: qcom: Move PCIe phy/GPIOs to root port nodes Krishna Chaitanya Chundru
2026-09-17 12:25 ` [PATCH v2 01/15] arm64: dts: qcom: qcs6490-vicharak-axon-mini: Move PCIe phy and GPIOs to root port node Krishna Chaitanya Chundru
@ 2026-09-17 12:25 ` Krishna Chaitanya Chundru
2026-09-17 15:11 ` Abel Vesa
2026-09-17 12:25 ` [PATCH v2 03/15] arm64: dts: qcom: qcs404: " Krishna Chaitanya Chundru
` (12 subsequent siblings)
14 siblings, 1 reply; 42+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 12:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio
The PCIe phy reference and the perst GPIO property are per root port
and belong in the root port node (pcie@0), not in the RC controller
node. Move phys, phy-names, and perst-gpios from the controller to
pcie0_port0, adding a label to this node to allow board-level
overrides, and renaming perst-gpios to reset-gpios to match the
binding used in the root port context.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 5038d0009c1a..bd8b69e323e1 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -928,8 +928,6 @@ pcie0: pcie@1c00000 {
#address-cells = <3>;
#size-cells = <2>;
num-lanes = <1>;
- phys = <&pcie_phy>;
- phy-names = "pciephy";
status = "disabled";
ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
@@ -969,13 +967,15 @@ pcie0: pcie@1c00000 {
power-domains = <&gcc PCIE_0_GDSC>;
iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie_phy>;
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
--
2.34.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 02/15] arm64: dts: qcom: msm8998: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 02/15] arm64: dts: qcom: msm8998: " Krishna Chaitanya Chundru
@ 2026-09-17 15:11 ` Abel Vesa
0 siblings, 0 replies; 42+ messages in thread
From: Abel Vesa @ 2026-09-17 15:11 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
On 26-09-17 17:55:16, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst GPIO property are per root port
> and belong in the root port node (pcie@0), not in the RC controller
> node. Move phys, phy-names, and perst-gpios from the controller to
> pcie0_port0, adding a label to this node to allow board-level
> overrides, and renaming perst-gpios to reset-gpios to match the
> binding used in the root port context.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 03/15] arm64: dts: qcom: qcs404: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 [PATCH v2 00/15] arm64: dts: qcom: Move PCIe phy/GPIOs to root port nodes Krishna Chaitanya Chundru
2026-09-17 12:25 ` [PATCH v2 01/15] arm64: dts: qcom: qcs6490-vicharak-axon-mini: Move PCIe phy and GPIOs to root port node Krishna Chaitanya Chundru
2026-09-17 12:25 ` [PATCH v2 02/15] arm64: dts: qcom: msm8998: " Krishna Chaitanya Chundru
@ 2026-09-17 12:25 ` Krishna Chaitanya Chundru
2026-09-17 15:11 ` Abel Vesa
2026-09-17 12:25 ` [PATCH v2 04/15] arm64: dts: qcom: sar2130p: " Krishna Chaitanya Chundru
` (11 subsequent siblings)
14 siblings, 1 reply; 42+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 12:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio
The PCIe phy reference and the perst GPIO property are per root port
and belong in the root port node (pcie@0), not in the RC controller
node. Move phys and phy-names from the controller to pcie0_port0,
adding a label to this node to allow board-level overrides. Move
perst-gpios from the &pcie controller override to &pcie0_port0 in
the board file, renaming perst-gpios to reset-gpios to match the
binding used in the root port context.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 6 ++++--
arch/arm64/boot/dts/qcom/qcs404.dtsi | 7 +++----
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index a22b4501ce1e..55bd53f8c159 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -101,8 +101,6 @@ pms405_s3: s3 {
&pcie {
status = "okay";
- perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&perst_state>;
};
@@ -114,6 +112,10 @@ &pcie_phy {
vdda-vph-supply = <&vreg_l5_1p8>;
};
+&pcie_port0 {
+ reset-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
+};
+
&remoteproc_adsp {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 736accfc34f9..7b622660c327 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -1517,16 +1517,15 @@ pcie: pcie@10000000 {
"pwr",
"ahb";
- phys = <&pcie_phy>;
- phy-names = "pciephy";
-
status = "disabled";
- pcie@0 {
+ pcie_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
--
2.34.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 03/15] arm64: dts: qcom: qcs404: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 03/15] arm64: dts: qcom: qcs404: " Krishna Chaitanya Chundru
@ 2026-09-17 15:11 ` Abel Vesa
0 siblings, 0 replies; 42+ messages in thread
From: Abel Vesa @ 2026-09-17 15:11 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
On 26-09-17 17:55:17, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst GPIO property are per root port
> and belong in the root port node (pcie@0), not in the RC controller
> node. Move phys and phy-names from the controller to pcie0_port0,
> adding a label to this node to allow board-level overrides. Move
> perst-gpios from the &pcie controller override to &pcie0_port0 in
> the board file, renaming perst-gpios to reset-gpios to match the
> binding used in the root port context.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 04/15] arm64: dts: qcom: sar2130p: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 [PATCH v2 00/15] arm64: dts: qcom: Move PCIe phy/GPIOs to root port nodes Krishna Chaitanya Chundru
` (2 preceding siblings ...)
2026-09-17 12:25 ` [PATCH v2 03/15] arm64: dts: qcom: qcs404: " Krishna Chaitanya Chundru
@ 2026-09-17 12:25 ` Krishna Chaitanya Chundru
2026-09-17 15:12 ` Abel Vesa
2026-09-17 12:25 ` [PATCH v2 05/15] arm64: dts: qcom: sc8180x: " Krishna Chaitanya Chundru
` (10 subsequent siblings)
14 siblings, 1 reply; 42+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 12:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
the existing pcieport0 and newly labeled pcie1_port0, allowing
board-level overrides. Move perst-gpios/wake-gpios from the &pcie0
controller override to &pcieport0 in the board file, renaming
perst-gpios to reset-gpios to match the binding used in the root
port context.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts | 6 +++---
arch/arm64/boot/dts/qcom/sar2130p.dtsi | 12 +++++-------
2 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts
index 7469134f42b7..cc04eefdfcff 100644
--- a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts
+++ b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts
@@ -357,9 +357,6 @@ &i2c10 {
};
&pcie0 {
- perst-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -367,6 +364,9 @@ &pcie0 {
};
&pcieport0 {
+ reset-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
index a2d93fd68299..678ecda1c99a 100644
--- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
@@ -1337,9 +1337,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
status = "disabled";
pcieport0: pcie@0 {
@@ -1347,6 +1344,8 @@ pcieport0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie0_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -1464,16 +1463,15 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
status = "disabled";
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie1_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
--
2.34.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 04/15] arm64: dts: qcom: sar2130p: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 04/15] arm64: dts: qcom: sar2130p: " Krishna Chaitanya Chundru
@ 2026-09-17 15:12 ` Abel Vesa
0 siblings, 0 replies; 42+ messages in thread
From: Abel Vesa @ 2026-09-17 15:12 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
On 26-09-17 17:55:18, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys and phy-names from the controller to
> the existing pcieport0 and newly labeled pcie1_port0, allowing
> board-level overrides. Move perst-gpios/wake-gpios from the &pcie0
> controller override to &pcieport0 in the board file, renaming
> perst-gpios to reset-gpios to match the binding used in the root
> port context.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 05/15] arm64: dts: qcom: sc8180x: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 [PATCH v2 00/15] arm64: dts: qcom: Move PCIe phy/GPIOs to root port nodes Krishna Chaitanya Chundru
` (3 preceding siblings ...)
2026-09-17 12:25 ` [PATCH v2 04/15] arm64: dts: qcom: sar2130p: " Krishna Chaitanya Chundru
@ 2026-09-17 12:25 ` Krishna Chaitanya Chundru
2026-09-17 15:13 ` Abel Vesa
2026-09-17 12:25 ` [PATCH v2 06/15] arm64: dts: qcom: sdm845: " Krishna Chaitanya Chundru
` (9 subsequent siblings)
14 siblings, 1 reply; 42+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 12:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Konrad Dybcio
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
pcie0_port0, pcie1_port0, pcie2_port0, and pcie3_port0, adding
labels to these nodes to allow board-level overrides. Move
perst-gpios/wake-gpios from the controller overrides to the
respective port nodes in the board files, renaming perst-gpios to
reset-gpios to match the binding used in the root port context.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
.../arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 7 +++++--
arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 7 +++++--
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 24 +++++++++++-----------
3 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
index e6ab523d249e..aa634a070283 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
+++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
@@ -491,8 +491,6 @@ &mdss_edp_out {
};
&pcie3 {
- perst-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 180 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie3_default_state>;
pinctrl-names = "default";
@@ -506,6 +504,11 @@ &pcie3_phy {
status = "okay";
};
+&pcie3_port0 {
+ reset-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 180 GPIO_ACTIVE_LOW>;
+};
+
&pmc8180_2_gpios {
bl_pwr_en: bl-pwr-en-state {
pins = "gpio1";
diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
index 327dba55a5ec..2311c5fb44e4 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
+++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
@@ -592,8 +592,6 @@ &mdss_edp_out {
};
&pcie1 {
- perst-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 177 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2_default_state>;
@@ -607,6 +605,11 @@ &pcie1_phy {
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 177 GPIO_ACTIVE_LOW>;
+};
+
&pmc8180_pwrkey {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index de1b72b64d96..a85e3211958d 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -1779,17 +1779,17 @@ pcie0: pcie@1c00000 {
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
dma-coherent;
status = "disabled";
- pcie@0 {
+ pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie0_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -1898,17 +1898,17 @@ pcie3: pcie@1c08000 {
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
- phys = <&pcie3_phy>;
- phy-names = "pciephy";
dma-coherent;
status = "disabled";
- pcie@0 {
+ pcie3_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie3_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -2018,17 +2018,17 @@ pcie1: pcie@1c10000 {
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
dma-coherent;
status = "disabled";
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie1_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -2138,17 +2138,17 @@ pcie2: pcie@1c18000 {
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
- phys = <&pcie2_phy>;
- phy-names = "pciephy";
dma-coherent;
status = "disabled";
- pcie@0 {
+ pcie2_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie2_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
--
2.34.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 05/15] arm64: dts: qcom: sc8180x: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 05/15] arm64: dts: qcom: sc8180x: " Krishna Chaitanya Chundru
@ 2026-09-17 15:13 ` Abel Vesa
0 siblings, 0 replies; 42+ messages in thread
From: Abel Vesa @ 2026-09-17 15:13 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio
On 26-09-17 17:55:19, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys and phy-names from the controller to
> pcie0_port0, pcie1_port0, pcie2_port0, and pcie3_port0, adding
> labels to these nodes to allow board-level overrides. Move
> perst-gpios/wake-gpios from the controller overrides to the
> respective port nodes in the board files, renaming perst-gpios to
> reset-gpios to match the binding used in the root port context.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 06/15] arm64: dts: qcom: sdm845: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 [PATCH v2 00/15] arm64: dts: qcom: Move PCIe phy/GPIOs to root port nodes Krishna Chaitanya Chundru
` (4 preceding siblings ...)
2026-09-17 12:25 ` [PATCH v2 05/15] arm64: dts: qcom: sc8180x: " Krishna Chaitanya Chundru
@ 2026-09-17 12:25 ` Krishna Chaitanya Chundru
2026-09-17 15:13 ` Abel Vesa
2026-09-18 10:04 ` Konrad Dybcio
2026-09-17 12:25 ` [PATCH v2 07/15] arm64: dts: qcom: sm8150: " Krishna Chaitanya Chundru
` (8 subsequent siblings)
14 siblings, 2 replies; 42+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 12:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Krishna Chaitanya Chundru
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
pcie0_port0 and pcie1_port0, adding labels to these nodes to allow
board-level overrides. Move perst-gpios/wake-gpios from the
controller overrides to the respective port nodes in the board files,
renaming perst-gpios to reset-gpios to match the binding used in the
root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 13 +++++++++----
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 12 ++++++++----
arch/arm64/boot/dts/qcom/sdm845.dtsi | 14 ++++++--------
3 files changed, 23 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
index 3e636926231d..02cb29afb246 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
@@ -618,9 +618,6 @@ &mss_pil {
&pcie0 {
status = "okay";
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 134 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&pcie0_3p3v_dual>;
pinctrl-names = "default";
@@ -634,9 +631,13 @@ &pcie0_phy {
vdda-pll-supply = <&vreg_l26a_1p2>;
};
+&pcie0_port0 {
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 134 GPIO_ACTIVE_LOW>;
+};
+
&pcie1 {
status = "okay";
- perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
@@ -649,6 +650,10 @@ &pcie1_phy {
vdda-pll-supply = <&vreg_l26a_1p2>;
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
+};
+
&pm8998_gpios {
gpio-line-names =
"NC",
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index c66df45eee64..88aa0b7de5fd 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -508,8 +508,6 @@ &mss_pil {
};
&pcie0 {
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -523,9 +521,11 @@ &pcie0_phy {
status = "okay";
};
-&pcie1 {
- perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
+&pcie0_port0 {
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+};
+&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
@@ -539,6 +539,10 @@ &pcie1_phy {
vdda-pll-supply = <&vreg_l26a_1p2>;
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
+};
+
&pm8998_adc {
channel@4c {
reg = <ADC5_XO_THERM_100K_PU>;
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index b1f6782a3ad9..cb7f93b02b5a 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2395,16 +2395,15 @@ pcie0: pcie@1c00000 {
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
status = "disabled";
- pcie@0 {
+ pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie0_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -2525,16 +2524,15 @@ pcie1: pcie@1c08000 {
power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
status = "disabled";
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie1_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
--
2.34.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 06/15] arm64: dts: qcom: sdm845: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 06/15] arm64: dts: qcom: sdm845: " Krishna Chaitanya Chundru
@ 2026-09-17 15:13 ` Abel Vesa
2026-09-18 10:04 ` Konrad Dybcio
1 sibling, 0 replies; 42+ messages in thread
From: Abel Vesa @ 2026-09-17 15:13 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 26-09-17 17:55:20, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys and phy-names from the controller to
> pcie0_port0 and pcie1_port0, adding labels to these nodes to allow
> board-level overrides. Move perst-gpios/wake-gpios from the
> controller overrides to the respective port nodes in the board files,
> renaming perst-gpios to reset-gpios to match the binding used in the
> root port context.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 06/15] arm64: dts: qcom: sdm845: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 06/15] arm64: dts: qcom: sdm845: " Krishna Chaitanya Chundru
2026-09-17 15:13 ` Abel Vesa
@ 2026-09-18 10:04 ` Konrad Dybcio
1 sibling, 0 replies; 42+ messages in thread
From: Konrad Dybcio @ 2026-09-18 10:04 UTC (permalink / raw)
To: Krishna Chaitanya Chundru, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 9/17/26 2:25 PM, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys and phy-names from the controller to
> pcie0_port0 and pcie1_port0, adding labels to these nodes to allow
> board-level overrides. Move perst-gpios/wake-gpios from the
> controller overrides to the respective port nodes in the board files,
> renaming perst-gpios to reset-gpios to match the binding used in the
> root port context.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 07/15] arm64: dts: qcom: sm8150: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 [PATCH v2 00/15] arm64: dts: qcom: Move PCIe phy/GPIOs to root port nodes Krishna Chaitanya Chundru
` (5 preceding siblings ...)
2026-09-17 12:25 ` [PATCH v2 06/15] arm64: dts: qcom: sdm845: " Krishna Chaitanya Chundru
@ 2026-09-17 12:25 ` Krishna Chaitanya Chundru
2026-09-17 15:19 ` Abel Vesa
` (2 more replies)
2026-09-17 12:25 ` [PATCH v2 08/15] arm64: dts: qcom: sm8250: " Krishna Chaitanya Chundru
` (7 subsequent siblings)
14 siblings, 3 replies; 42+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 12:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Krishna Chaitanya Chundru
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios
from the controller to pcie0_port0 and pcie1_port0, adding labels to
these nodes to allow board-level overrides, and renaming perst-gpios
to reset-gpios to match the binding used in the root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 17 +++++++----------
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 74df5cd86f04..50fd00bc9f3e 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1901,12 +1901,6 @@ pcie0: pcie@1c00000 {
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
- wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
@@ -1917,6 +1911,10 @@ pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie0_phy>;
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -2019,10 +2017,6 @@ pcie1: pcie@1c08000 {
power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
- perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
@@ -2035,6 +2029,9 @@ pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie1_phy>;
+ reset-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
--
2.34.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 07/15] arm64: dts: qcom: sm8150: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 07/15] arm64: dts: qcom: sm8150: " Krishna Chaitanya Chundru
@ 2026-09-17 15:19 ` Abel Vesa
2026-09-18 10:06 ` Konrad Dybcio
2026-09-18 10:06 ` Konrad Dybcio
2 siblings, 0 replies; 42+ messages in thread
From: Abel Vesa @ 2026-09-17 15:19 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 26-09-17 17:55:21, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios
> from the controller to pcie0_port0 and pcie1_port0, adding labels to
> these nodes to allow board-level overrides, and renaming perst-gpios
> to reset-gpios to match the binding used in the root port context.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 07/15] arm64: dts: qcom: sm8150: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 07/15] arm64: dts: qcom: sm8150: " Krishna Chaitanya Chundru
2026-09-17 15:19 ` Abel Vesa
@ 2026-09-18 10:06 ` Konrad Dybcio
2026-09-18 10:06 ` Konrad Dybcio
2 siblings, 0 replies; 42+ messages in thread
From: Konrad Dybcio @ 2026-09-18 10:06 UTC (permalink / raw)
To: Krishna Chaitanya Chundru, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 9/17/26 2:25 PM, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios
> from the controller to pcie0_port0 and pcie1_port0, adding labels to
> these nodes to allow board-level overrides, and renaming perst-gpios
> to reset-gpios to match the binding used in the root port context.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
[...]
> - perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;
> enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
I am mightily confused as to what this GPIO is.. bindings don't
explicitly allow it but don't seem to disallow it either?
Konrad
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 07/15] arm64: dts: qcom: sm8150: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 07/15] arm64: dts: qcom: sm8150: " Krishna Chaitanya Chundru
2026-09-17 15:19 ` Abel Vesa
2026-09-18 10:06 ` Konrad Dybcio
@ 2026-09-18 10:06 ` Konrad Dybcio
2 siblings, 0 replies; 42+ messages in thread
From: Konrad Dybcio @ 2026-09-18 10:06 UTC (permalink / raw)
To: Krishna Chaitanya Chundru, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 9/17/26 2:25 PM, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios
> from the controller to pcie0_port0 and pcie1_port0, adding labels to
> these nodes to allow board-level overrides, and renaming perst-gpios
> to reset-gpios to match the binding used in the root port context.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 08/15] arm64: dts: qcom: sm8250: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 [PATCH v2 00/15] arm64: dts: qcom: Move PCIe phy/GPIOs to root port nodes Krishna Chaitanya Chundru
` (6 preceding siblings ...)
2026-09-17 12:25 ` [PATCH v2 07/15] arm64: dts: qcom: sm8150: " Krishna Chaitanya Chundru
@ 2026-09-17 12:25 ` Krishna Chaitanya Chundru
2026-09-17 15:19 ` Abel Vesa
2026-09-18 10:06 ` Konrad Dybcio
2026-09-17 12:25 ` [PATCH v2 09/15] arm64: dts: qcom: sm8350: " Krishna Chaitanya Chundru
` (6 subsequent siblings)
14 siblings, 2 replies; 42+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 12:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Krishna Chaitanya Chundru
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios
from the controller to the existing pcieport0 and newly labeled
pcie1_port0 and pcie2_port0, allowing board-level overrides. Rename
perst-gpios to reset-gpios to match the binding used in the root
port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 30 ++++++++++++------------------
1 file changed, 12 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index e0c357222bc7..caabd201c0d9 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2207,12 +2207,6 @@ pcie0: pcie@1c00000 {
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
- perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 81 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
dma-coherent;
@@ -2224,6 +2218,10 @@ pcieport0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie0_phy>;
+ reset-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 81 GPIO_ACTIVE_LOW>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -2334,12 +2332,6 @@ pcie1: pcie@1c08000 {
power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
- perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
dma-coherent;
@@ -2351,6 +2343,10 @@ pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie1_phy>;
+ reset-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -2461,12 +2457,6 @@ pcie2: pcie@1c10000 {
power-domains = <&gcc PCIE_2_GDSC>;
- phys = <&pcie2_phy>;
- phy-names = "pciephy";
-
- perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie2_default_state>;
dma-coherent;
@@ -2478,6 +2468,10 @@ pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie2_phy>;
+ reset-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
--
2.34.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 08/15] arm64: dts: qcom: sm8250: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 08/15] arm64: dts: qcom: sm8250: " Krishna Chaitanya Chundru
@ 2026-09-17 15:19 ` Abel Vesa
2026-09-18 10:06 ` Konrad Dybcio
1 sibling, 0 replies; 42+ messages in thread
From: Abel Vesa @ 2026-09-17 15:19 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 26-09-17 17:55:22, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios
> from the controller to the existing pcieport0 and newly labeled
> pcie1_port0 and pcie2_port0, allowing board-level overrides. Rename
> perst-gpios to reset-gpios to match the binding used in the root
> port context.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 08/15] arm64: dts: qcom: sm8250: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 08/15] arm64: dts: qcom: sm8250: " Krishna Chaitanya Chundru
2026-09-17 15:19 ` Abel Vesa
@ 2026-09-18 10:06 ` Konrad Dybcio
1 sibling, 0 replies; 42+ messages in thread
From: Konrad Dybcio @ 2026-09-18 10:06 UTC (permalink / raw)
To: Krishna Chaitanya Chundru, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 9/17/26 2:25 PM, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios
> from the controller to the existing pcieport0 and newly labeled
> pcie1_port0 and pcie2_port0, allowing board-level overrides. Rename
> perst-gpios to reset-gpios to match the binding used in the root
> port context.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 09/15] arm64: dts: qcom: sm8350: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 [PATCH v2 00/15] arm64: dts: qcom: Move PCIe phy/GPIOs to root port nodes Krishna Chaitanya Chundru
` (7 preceding siblings ...)
2026-09-17 12:25 ` [PATCH v2 08/15] arm64: dts: qcom: sm8250: " Krishna Chaitanya Chundru
@ 2026-09-17 12:25 ` Krishna Chaitanya Chundru
2026-09-17 15:18 ` Abel Vesa
2026-09-18 10:07 ` Konrad Dybcio
2026-09-17 12:25 ` [PATCH v2 10/15] arm64: dts: qcom: sm8450: " Krishna Chaitanya Chundru
` (5 subsequent siblings)
14 siblings, 2 replies; 42+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 12:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Krishna Chaitanya Chundru
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
pcie0_port0 and pcie1_port0, adding labels to these nodes to allow
board-level overrides. Move perst-gpios/wake-gpios from the
controller overrides to the respective port nodes in the board file,
renaming perst-gpios to reset-gpios to match the binding used in the
root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 16 ++++++++++------
arch/arm64/boot/dts/qcom/sm8350.dtsi | 14 ++++++--------
2 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index e9b9e03f725e..37b9dc1b16d6 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -499,9 +499,6 @@ &pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
-
status = "okay";
};
@@ -512,10 +509,12 @@ &pcie0_phy {
status = "okay";
};
-&pcie1 {
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+&pcie0_port0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+};
+&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
@@ -528,6 +527,11 @@ &pcie1_phy {
vdda-pll-supply = <&vreg_l6b_1p2>;
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+};
+
&qupv3_id_0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 32b47f5ec1f6..74cd66d98c54 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1586,16 +1586,15 @@ pcie0: pcie@1c00000 {
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
status = "disabled";
- pcie@0 {
+ pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie0_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -1695,16 +1694,15 @@ pcie1: pcie@1c08000 {
power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
status = "disabled";
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie1_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
--
2.34.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 09/15] arm64: dts: qcom: sm8350: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 09/15] arm64: dts: qcom: sm8350: " Krishna Chaitanya Chundru
@ 2026-09-17 15:18 ` Abel Vesa
2026-09-18 10:07 ` Konrad Dybcio
1 sibling, 0 replies; 42+ messages in thread
From: Abel Vesa @ 2026-09-17 15:18 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 26-09-17 17:55:23, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys and phy-names from the controller to
> pcie0_port0 and pcie1_port0, adding labels to these nodes to allow
> board-level overrides. Move perst-gpios/wake-gpios from the
> controller overrides to the respective port nodes in the board file,
> renaming perst-gpios to reset-gpios to match the binding used in the
> root port context.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 09/15] arm64: dts: qcom: sm8350: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 09/15] arm64: dts: qcom: sm8350: " Krishna Chaitanya Chundru
2026-09-17 15:18 ` Abel Vesa
@ 2026-09-18 10:07 ` Konrad Dybcio
1 sibling, 0 replies; 42+ messages in thread
From: Konrad Dybcio @ 2026-09-18 10:07 UTC (permalink / raw)
To: Krishna Chaitanya Chundru, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 9/17/26 2:25 PM, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys and phy-names from the controller to
> pcie0_port0 and pcie1_port0, adding labels to these nodes to allow
> board-level overrides. Move perst-gpios/wake-gpios from the
> controller overrides to the respective port nodes in the board file,
> renaming perst-gpios to reset-gpios to match the binding used in the
> root port context.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 10/15] arm64: dts: qcom: sm8450: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 [PATCH v2 00/15] arm64: dts: qcom: Move PCIe phy/GPIOs to root port nodes Krishna Chaitanya Chundru
` (8 preceding siblings ...)
2026-09-17 12:25 ` [PATCH v2 09/15] arm64: dts: qcom: sm8350: " Krishna Chaitanya Chundru
@ 2026-09-17 12:25 ` Krishna Chaitanya Chundru
2026-09-17 15:18 ` Abel Vesa
2026-09-18 10:07 ` Konrad Dybcio
2026-09-17 12:25 ` [PATCH v2 11/15] arm64: dts: qcom: talos: " Krishna Chaitanya Chundru
` (4 subsequent siblings)
14 siblings, 2 replies; 42+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 12:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Neil Armstrong
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios
from the controller to the existing pcieport0 and newly labeled
pcie1_port0, allowing board-level overrides. Rename perst-gpios to
reset-gpios to match the binding used in the root port context.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 +++++++++-------------
1 file changed, 9 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 7bc5f85e7ebc..05e852ed7995 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -2017,12 +2017,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
@@ -2063,6 +2057,10 @@ pcieport0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie0_phy>;
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -2182,12 +2180,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
@@ -2263,11 +2255,15 @@ opp-32000000-4 {
};
};
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie1_phy>;
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
--
2.34.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 10/15] arm64: dts: qcom: sm8450: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 10/15] arm64: dts: qcom: sm8450: " Krishna Chaitanya Chundru
@ 2026-09-17 15:18 ` Abel Vesa
2026-09-18 10:07 ` Konrad Dybcio
1 sibling, 0 replies; 42+ messages in thread
From: Abel Vesa @ 2026-09-17 15:18 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Neil Armstrong
On 26-09-17 17:55:24, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios
> from the controller to the existing pcieport0 and newly labeled
> pcie1_port0, allowing board-level overrides. Rename perst-gpios to
> reset-gpios to match the binding used in the root port context.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
One nit below, the rest looks good:
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 +++++++++-------------
> 1 file changed, 9 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 7bc5f85e7ebc..05e852ed7995 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -2017,12 +2017,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>
> power-domains = <&gcc PCIE_0_GDSC>;
>
> - phys = <&pcie0_phy>;
> - phy-names = "pciephy";
> -
> - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
> - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
> -
> pinctrl-names = "default";
> pinctrl-0 = <&pcie0_default_state>;
>
> @@ -2063,6 +2057,10 @@ pcieport0: pcie@0 {
> reg = <0x0 0x0 0x0 0x0 0x0>;
> bus-range = <0x01 0xff>;
>
> + phys = <&pcie0_phy>;
Nit: If you respin, put a blank line here. Same for other places in this
patchset.
> + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
> +
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 10/15] arm64: dts: qcom: sm8450: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 10/15] arm64: dts: qcom: sm8450: " Krishna Chaitanya Chundru
2026-09-17 15:18 ` Abel Vesa
@ 2026-09-18 10:07 ` Konrad Dybcio
1 sibling, 0 replies; 42+ messages in thread
From: Konrad Dybcio @ 2026-09-18 10:07 UTC (permalink / raw)
To: Krishna Chaitanya Chundru, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong
On 9/17/26 2:25 PM, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios
> from the controller to the existing pcieport0 and newly labeled
> pcie1_port0, allowing board-level overrides. Rename perst-gpios to
> reset-gpios to match the binding used in the root port context.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 11/15] arm64: dts: qcom: talos: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 [PATCH v2 00/15] arm64: dts: qcom: Move PCIe phy/GPIOs to root port nodes Krishna Chaitanya Chundru
` (9 preceding siblings ...)
2026-09-17 12:25 ` [PATCH v2 10/15] arm64: dts: qcom: sm8450: " Krishna Chaitanya Chundru
@ 2026-09-17 12:25 ` Krishna Chaitanya Chundru
2026-09-17 15:14 ` Abel Vesa
2026-09-18 10:08 ` Konrad Dybcio
2026-09-17 12:25 ` [PATCH v2 12/15] arm64: dts: qcom: sm8650: " Krishna Chaitanya Chundru
` (3 subsequent siblings)
14 siblings, 2 replies; 42+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 12:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Krishna Chaitanya Chundru
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys from the controller to pcie_port0, and
move perst-gpios/wake-gpios from the &pcie controller overrides to the
&pcie_port0 node in the board files, renaming perst-gpios to reset-gpios
to match the binding used in the root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 5 ++---
arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 5 ++---
arch/arm64/boot/dts/qcom/talos.dtsi | 8 ++++----
3 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
index 43f110ba3a7c..142dafb04324 100644
--- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -444,9 +444,6 @@ &mdss_dsi0_phy {
};
&pcie {
- perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie_default_state>;
pinctrl-names = "default";
@@ -461,6 +458,8 @@ &pcie_phy {
};
&pcie_port0 {
+ reset-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi
index 198f656bddf1..aa2d9532d37f 100644
--- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi
@@ -366,9 +366,6 @@ &mdss_dsi0_phy {
};
&pcie {
- perst-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie_default_state>;
pinctrl-names = "default";
@@ -383,6 +380,8 @@ &pcie_phy {
};
&pcie_port0 {
+ reset-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index eedfdce3c479..a22f78f5a5de 100644
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -1367,9 +1367,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie_phy>;
- phy-names = "pciephy";
-
max-link-speed = <2>;
operating-points-v2 = <&pcie_opp_table>;
@@ -1397,10 +1394,13 @@ opp-5000000 {
pcie_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ phys = <&pcie_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
- bus-range = <0x01 0xff>;
};
};
--
2.34.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 11/15] arm64: dts: qcom: talos: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 11/15] arm64: dts: qcom: talos: " Krishna Chaitanya Chundru
@ 2026-09-17 15:14 ` Abel Vesa
2026-09-18 10:08 ` Konrad Dybcio
1 sibling, 0 replies; 42+ messages in thread
From: Abel Vesa @ 2026-09-17 15:14 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 26-09-17 17:55:25, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys from the controller to pcie_port0, and
> move perst-gpios/wake-gpios from the &pcie controller overrides to the
> &pcie_port0 node in the board files, renaming perst-gpios to reset-gpios
> to match the binding used in the root port context.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 11/15] arm64: dts: qcom: talos: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 11/15] arm64: dts: qcom: talos: " Krishna Chaitanya Chundru
2026-09-17 15:14 ` Abel Vesa
@ 2026-09-18 10:08 ` Konrad Dybcio
1 sibling, 0 replies; 42+ messages in thread
From: Konrad Dybcio @ 2026-09-18 10:08 UTC (permalink / raw)
To: Krishna Chaitanya Chundru, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 9/17/26 2:25 PM, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys from the controller to pcie_port0, and
> move perst-gpios/wake-gpios from the &pcie controller overrides to the
> &pcie_port0 node in the board files, renaming perst-gpios to reset-gpios
> to match the binding used in the root port context.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 5 ++---
> arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 5 ++---
> arch/arm64/boot/dts/qcom/talos.dtsi | 8 ++++----
> 3 files changed, 8 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> index 43f110ba3a7c..142dafb04324 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> @@ -444,9 +444,6 @@ &mdss_dsi0_phy {
> };
>
> &pcie {
> - perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
> - wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>;
> -
> pinctrl-0 = <&pcie_default_state>;
> pinctrl-names = "default";
>
> @@ -461,6 +458,8 @@ &pcie_phy {
> };
>
> &pcie_port0 {
> + reset-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>;
> wifi@0 {
Please retain a \n between properties and subnodes
Konrad
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 12/15] arm64: dts: qcom: sm8650: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 [PATCH v2 00/15] arm64: dts: qcom: Move PCIe phy/GPIOs to root port nodes Krishna Chaitanya Chundru
` (10 preceding siblings ...)
2026-09-17 12:25 ` [PATCH v2 11/15] arm64: dts: qcom: talos: " Krishna Chaitanya Chundru
@ 2026-09-17 12:25 ` Krishna Chaitanya Chundru
2026-09-17 15:15 ` Abel Vesa
2026-09-18 10:08 ` Konrad Dybcio
2026-09-17 12:25 ` [PATCH v2 13/15] arm64: dts: qcom: msm8996: " Krishna Chaitanya Chundru
` (2 subsequent siblings)
14 siblings, 2 replies; 42+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 12:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Neil Armstrong
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
the existing pcieport0 and pcie1_port0, allowing board-level
overrides. Move perst-gpios/wake-gpios from the controller overrides
to the respective port nodes in the board files, renaming perst-gpios
to reset-gpios to match the binding used in the root port context.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts | 11 +++++------
arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 14 ++++++++------
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 16 ++++++++++------
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 6 +++---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 ++++------
5 files changed, 30 insertions(+), 27 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
index 668c183bc177..022facada1b4 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts
@@ -1074,9 +1074,6 @@ &mdss_dp0_out {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -1084,6 +1081,9 @@ &pcie0 {
};
&pcieport0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -1108,9 +1108,6 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
@@ -1118,6 +1115,8 @@ &pcie1 {
};
&pcie1_port0 {
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
/* Renesas μPD720201 PCIe USB3.0 HOST CONTROLLER */
usb-controller@0 {
compatible = "pci1912,0014";
diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
index b73ad7861eb4..172f5edab30f 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts
@@ -1027,9 +1027,6 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -1037,6 +1034,9 @@ &pcie0 {
};
&pcieport0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -1061,9 +1061,6 @@ &pcie0_phy {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
@@ -1078,6 +1075,11 @@ &pcie1_phy {
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+};
+
&pm8550_gpios {
sdc2_card_det_n: sdc2-card-det-state {
pins = "gpio12";
diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
index 1332c864801f..f3ed42f81b0b 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
@@ -642,9 +642,6 @@ &mdss_dsi0_phy {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -658,10 +655,12 @@ &pcie0_phy {
status = "okay";
};
-&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+&pcieport0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+};
+&pcie1 {
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
@@ -676,6 +675,11 @@ &pcie1_phy {
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+};
+
&pm8550_gpios {
sdc2_card_det_n: sdc2-card-det-state {
pins = "gpio12";
diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
index 2e874f046a0e..c1971638561b 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
@@ -1021,9 +1021,6 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -1031,6 +1028,9 @@ &pcie0 {
};
&pcieport0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index b679fd8afb7d..39ecf4686c4b 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -3700,9 +3700,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
num-lanes = <2>;
bus-range = <0 0xff>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>,
@@ -3769,6 +3766,8 @@ pcieport0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie0_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -3893,9 +3892,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
num-lanes = <2>;
bus-range = <0 0xff>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
dma-coherent;
#address-cells = <3>;
@@ -3978,6 +3974,8 @@ pcie1_port0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie1_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
--
2.34.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 12/15] arm64: dts: qcom: sm8650: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 12/15] arm64: dts: qcom: sm8650: " Krishna Chaitanya Chundru
@ 2026-09-17 15:15 ` Abel Vesa
2026-09-18 10:08 ` Konrad Dybcio
1 sibling, 0 replies; 42+ messages in thread
From: Abel Vesa @ 2026-09-17 15:15 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Neil Armstrong
On 26-09-17 17:55:26, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys and phy-names from the controller to
> the existing pcieport0 and pcie1_port0, allowing board-level
> overrides. Move perst-gpios/wake-gpios from the controller overrides
> to the respective port nodes in the board files, renaming perst-gpios
> to reset-gpios to match the binding used in the root port context.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 12/15] arm64: dts: qcom: sm8650: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 12/15] arm64: dts: qcom: sm8650: " Krishna Chaitanya Chundru
2026-09-17 15:15 ` Abel Vesa
@ 2026-09-18 10:08 ` Konrad Dybcio
1 sibling, 0 replies; 42+ messages in thread
From: Konrad Dybcio @ 2026-09-18 10:08 UTC (permalink / raw)
To: Krishna Chaitanya Chundru, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong
On 9/17/26 2:25 PM, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys and phy-names from the controller to
> the existing pcieport0 and pcie1_port0, allowing board-level
> overrides. Move perst-gpios/wake-gpios from the controller overrides
> to the respective port nodes in the board files, renaming perst-gpios
> to reset-gpios to match the binding used in the root port context.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
[...]
> &pcie1_port0 {
> + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
> /* Renesas μPD720201 PCIe USB3.0 HOST CONTROLLER */
> usb-controller@0 {
ditto
Konrad
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 13/15] arm64: dts: qcom: msm8996: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 [PATCH v2 00/15] arm64: dts: qcom: Move PCIe phy/GPIOs to root port nodes Krishna Chaitanya Chundru
` (11 preceding siblings ...)
2026-09-17 12:25 ` [PATCH v2 12/15] arm64: dts: qcom: sm8650: " Krishna Chaitanya Chundru
@ 2026-09-17 12:25 ` Krishna Chaitanya Chundru
2026-09-17 15:15 ` Abel Vesa
2026-09-18 10:08 ` Konrad Dybcio
2026-09-17 12:25 ` [PATCH v2 14/15] arm64: dts: qcom: lemans: " Krishna Chaitanya Chundru
2026-09-17 12:25 ` [PATCH v2 15/15] arm64: dts: qcom: sm8550: " Krishna Chaitanya Chundru
14 siblings, 2 replies; 42+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 12:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Krishna Chaitanya Chundru
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
pcie0_port0, pcie1_port0, and pcie2_port0, adding labels to these
nodes to allow board-level overrides. Move perst-gpios/wake-gpios
from the controller overrides to the respective port nodes in the
board files, renaming perst-gpios to reset-gpios to match the binding
used in the root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 15 ++++++++++++---
.../arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi | 5 ++++-
.../boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 7 +++++--
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 4 +++-
arch/arm64/boot/dts/qcom/msm8996.dtsi | 21 +++++++++------------
5 files changed, 33 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 0c076852b494..ad435a13ba24 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -458,23 +458,32 @@ hdmi_ddc_suspend: hdmi-ddc-suspend-state {
&pcie0 {
status = "okay";
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&vreg_l28a_0p925>;
};
+&pcie0_port0 {
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+};
+
&pcie1 {
status = "okay";
- perst-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
vdda-supply = <&vreg_l28a_0p925>;
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
+};
+
&pcie2 {
status = "okay";
- perst-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>;
vdda-supply = <&vreg_l28a_0p925>;
};
+&pcie2_port0 {
+ reset-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>;
+};
+
&pcie_phy {
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi
index a4dcc88bb01f..7a3f8afae22d 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi
@@ -210,12 +210,15 @@ &mss_pil {
};
&pcie0 {
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&vreg_l28a_0p925>;
status = "okay";
};
+&pcie0_port0 {
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+};
+
&pcie_phy {
vdda-phy-supply = <&vreg_l28a_0p925>;
vdda-pll-supply = <&vreg_l12a_1p8>;
diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
index 5b42c266557a..20b5eeef46e4 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi
@@ -191,13 +191,16 @@ &mmcc {
};
&pcie0 {
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&pm8994_l28>;
status = "okay";
};
+&pcie0_port0 {
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+};
+
&pcie_phy {
vdda-phy-supply = <&pm8994_l28>;
vdda-pll-supply = <&pm8994_l12>;
diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
index 2abcc733dad8..3c70a9be45d2 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
@@ -278,8 +278,10 @@ &pcie0 {
/* Supplied by vdd_3v3, but choose wlan_en to drive enable pin high */
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&vreg_l28a_0p925>;
+};
- perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
+&pcie0_port0 {
+ reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 818e5660df91..f3c004f02cfc 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -1924,9 +1924,6 @@ pcie0: pcie@600000 {
<0x0c100000 0x100000>;
reg-names = "parf", "dbi", "elbi","config";
- phys = <&pciephy_0>;
- phy-names = "pciephy";
-
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
@@ -1975,11 +1972,13 @@ pcie0: pcie@600000 {
"bus_master",
"bus_slave";
- pcie@0 {
+ pcie0_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pciephy_0>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -2001,9 +2000,6 @@ pcie1: pcie@608000 {
reg-names = "parf", "dbi", "elbi","config";
- phys = <&pciephy_1>;
- phy-names = "pciephy";
-
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
@@ -2052,11 +2048,13 @@ pcie1: pcie@608000 {
"bus_master",
"bus_slave";
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pciephy_1>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -2076,9 +2074,6 @@ pcie2: pcie@610000 {
reg-names = "parf", "dbi", "elbi","config";
- phys = <&pciephy_2>;
- phy-names = "pciephy";
-
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
@@ -2126,11 +2121,13 @@ pcie2: pcie@610000 {
"bus_master",
"bus_slave";
- pcie@0 {
+ pcie2_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pciephy_2>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
--
2.34.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 13/15] arm64: dts: qcom: msm8996: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 13/15] arm64: dts: qcom: msm8996: " Krishna Chaitanya Chundru
@ 2026-09-17 15:15 ` Abel Vesa
2026-09-18 10:08 ` Konrad Dybcio
1 sibling, 0 replies; 42+ messages in thread
From: Abel Vesa @ 2026-09-17 15:15 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 26-09-17 17:55:27, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys and phy-names from the controller to
> pcie0_port0, pcie1_port0, and pcie2_port0, adding labels to these
> nodes to allow board-level overrides. Move perst-gpios/wake-gpios
> from the controller overrides to the respective port nodes in the
> board files, renaming perst-gpios to reset-gpios to match the binding
> used in the root port context.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 13/15] arm64: dts: qcom: msm8996: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 13/15] arm64: dts: qcom: msm8996: " Krishna Chaitanya Chundru
2026-09-17 15:15 ` Abel Vesa
@ 2026-09-18 10:08 ` Konrad Dybcio
1 sibling, 0 replies; 42+ messages in thread
From: Konrad Dybcio @ 2026-09-18 10:08 UTC (permalink / raw)
To: Krishna Chaitanya Chundru, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 9/17/26 2:25 PM, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys and phy-names from the controller to
> pcie0_port0, pcie1_port0, and pcie2_port0, adding labels to these
> nodes to allow board-level overrides. Move perst-gpios/wake-gpios
> from the controller overrides to the respective port nodes in the
> board files, renaming perst-gpios to reset-gpios to match the binding
> used in the root port context.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 14/15] arm64: dts: qcom: lemans: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 [PATCH v2 00/15] arm64: dts: qcom: Move PCIe phy/GPIOs to root port nodes Krishna Chaitanya Chundru
` (12 preceding siblings ...)
2026-09-17 12:25 ` [PATCH v2 13/15] arm64: dts: qcom: msm8996: " Krishna Chaitanya Chundru
@ 2026-09-17 12:25 ` Krishna Chaitanya Chundru
2026-09-17 15:15 ` Abel Vesa
2026-09-18 10:09 ` Konrad Dybcio
2026-09-17 12:25 ` [PATCH v2 15/15] arm64: dts: qcom: sm8550: " Krishna Chaitanya Chundru
14 siblings, 2 replies; 42+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 12:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Krishna Chaitanya Chundru
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys from the controller to pcieport0 and
pcieport1. Add the missing pcieport1 label to the pcie1 root port
node to allow board-level overrides. Move perst-gpios/wake-gpios from
the &pcie0/&pcie1 controller overrides to the respective &pcieport0/
&pcieport1 nodes in the board files, renaming perst-gpios to reset-gpios
to match the binding used in the root port context.
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans-evk.dts | 13 +++++++------
arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 13 +++++++------
arch/arm64/boot/dts/qcom/lemans.dtsi | 12 +++++-------
3 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts
index 194e114a12a0..89c721eb532f 100644
--- a/arch/arm64/boot/dts/qcom/lemans-evk.dts
+++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts
@@ -839,9 +839,6 @@ &mdss0_dp1_phy {
};
&pcie0 {
- perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -856,9 +853,6 @@ &pcie0_phy {
};
&pcie1 {
- perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
@@ -872,7 +866,14 @@ &pcie1_phy {
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
+};
+
&pcieport0 {
+ reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
port {
pcieport0_ep: endpoint {
remote-endpoint = <&m2_e_pcie_ep>;
diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
index 3ecf3d464dd7..6b540eb318d4 100644
--- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi
@@ -961,9 +961,6 @@ wake-pins {
};
&pcie0 {
- perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
@@ -971,9 +968,6 @@ &pcie0 {
};
&pcie1 {
- perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
@@ -994,7 +988,14 @@ &pcie1_phy {
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
+};
+
&pcieport0 {
+ reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1101";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 695eae1b7256..7ae08f29d974 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -2753,9 +2753,6 @@ pcie0: pcie@1c00000 {
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
eq-presets-16gts = /bits/ 8 <0x55 0x55>;
@@ -2767,6 +2764,8 @@ pcieport0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie0_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -2927,19 +2926,18 @@ pcie1: pcie@1c10000 {
power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
status = "disabled";
- pcie@0 {
+ pcie1_port0: pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie1_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
--
2.34.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 14/15] arm64: dts: qcom: lemans: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 14/15] arm64: dts: qcom: lemans: " Krishna Chaitanya Chundru
@ 2026-09-17 15:15 ` Abel Vesa
2026-09-18 10:09 ` Konrad Dybcio
1 sibling, 0 replies; 42+ messages in thread
From: Abel Vesa @ 2026-09-17 15:15 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
On 26-09-17 17:55:28, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys from the controller to pcieport0 and
> pcieport1. Add the missing pcieport1 label to the pcie1 root port
> node to allow board-level overrides. Move perst-gpios/wake-gpios from
> the &pcie0/&pcie1 controller overrides to the respective &pcieport0/
> &pcieport1 nodes in the board files, renaming perst-gpios to reset-gpios
> to match the binding used in the root port context.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 14/15] arm64: dts: qcom: lemans: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 14/15] arm64: dts: qcom: lemans: " Krishna Chaitanya Chundru
2026-09-17 15:15 ` Abel Vesa
@ 2026-09-18 10:09 ` Konrad Dybcio
1 sibling, 0 replies; 42+ messages in thread
From: Konrad Dybcio @ 2026-09-18 10:09 UTC (permalink / raw)
To: Krishna Chaitanya Chundru, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 9/17/26 2:25 PM, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys from the controller to pcieport0 and
> pcieport1. Add the missing pcieport1 label to the pcie1 root port
> node to allow board-level overrides. Move perst-gpios/wake-gpios from
> the &pcie0/&pcie1 controller overrides to the respective &pcieport0/
> &pcieport1 nodes in the board files, renaming perst-gpios to reset-gpios
> to match the binding used in the root port context.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
[...]
> +&pcie1_port0 {
> + reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
> +};
> +
> &pcieport0 {
> + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
> port {
ditto
Konrad
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 15/15] arm64: dts: qcom: sm8550: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 [PATCH v2 00/15] arm64: dts: qcom: Move PCIe phy/GPIOs to root port nodes Krishna Chaitanya Chundru
` (13 preceding siblings ...)
2026-09-17 12:25 ` [PATCH v2 14/15] arm64: dts: qcom: lemans: " Krishna Chaitanya Chundru
@ 2026-09-17 12:25 ` Krishna Chaitanya Chundru
2026-09-17 15:16 ` Abel Vesa
2026-09-18 10:09 ` Konrad Dybcio
14 siblings, 2 replies; 42+ messages in thread
From: Krishna Chaitanya Chundru @ 2026-09-17 12:25 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel,
Krishna Chaitanya Chundru, Neil Armstrong
The PCIe phy reference and the perst/wake GPIO properties are
per root port and belong in the root port node (pcie@0), not in the
RC controller node. Move phys and phy-names from the controller to
the existing pcieport0 and newly labeled pcie1_port0, allowing
board-level overrides. Move perst-gpios/wake-gpios from the
controller overrides to the respective port nodes in the board files,
renaming perst-gpios to reset-gpios to match the binding used in the
root port context.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 16 ++++++++-----
arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts | 12 +++++-----
arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 28 ++++++++++++----------
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 16 ++++++++-----
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 20 ++++++++--------
arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 7 ++++--
.../dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 8 ++++---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 ++++----
8 files changed, 65 insertions(+), 52 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
index aaf5eb57ce23..4faedcca3c5b 100644
--- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
@@ -335,9 +335,6 @@ &mdss_dsi0_phy {
};
&pcie0 {
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
};
@@ -347,10 +344,12 @@ &pcie0_phy {
vdda-pll-supply = <&vreg_l3e_1p2>;
};
-&pcie1 {
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+&pcie0_port0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+};
+&pcie1 {
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
};
@@ -361,6 +360,11 @@ &pcie1_phy {
vdda-qref-supply = <&vreg_l1e_0p88>;
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+};
+
&pm8550b_eusb2_repeater {
vdd18-supply = <&vreg_l15b_1p8>;
vdd3-supply = <&vreg_l5b_3p1>;
diff --git a/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts
index 41b09ab43d0c..42e3e862e6f4 100644
--- a/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts
@@ -1045,9 +1045,6 @@ &mdss_dp0 {
&pcie0 {
vddpe-3v3-supply = <&pcie_upd_3p3>;
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -1074,6 +1071,9 @@ &pcie0_phy {
};
&pcie0_port0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+
pcie@0,0 {
compatible = "pci1179,0623";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -1146,9 +1146,6 @@ pci@0,1 {
};
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
@@ -1176,6 +1173,9 @@ &pcie1_phy {
};
&pcie1_port0 {
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+
pcie@0,0 {
compatible = "pci1179,0623";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
index 4777c908c4d7..e75e3b878e89 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
@@ -1087,16 +1087,23 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
status = "okay";
};
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1e_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
&pcie0_port0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -1113,17 +1120,7 @@ wifi@0 {
};
};
-&pcie0_phy {
- vdda-phy-supply = <&vreg_l1e_0p88>;
- vdda-pll-supply = <&vreg_l3e_1p2>;
-
- status = "okay";
-};
-
&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie1_default_state>;
pinctrl-names = "default";
@@ -1138,6 +1135,11 @@ &pcie1_phy {
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+};
+
&pm8550_gpios {
sdc2_card_det_n: sdc2-card-det-state {
pins = "gpio12";
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index eb1de33e5ba5..7b191c9553f0 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -739,9 +739,6 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
@@ -755,10 +752,12 @@ &pcie0_phy {
status = "okay";
};
-&pcie1 {
- wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+&pcie0_port0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+};
+&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
@@ -773,6 +772,11 @@ &pcie1_phy {
status = "okay";
};
+&pcie1_port0 {
+ reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
+};
+
&pm8550_gpios {
sdc2_card_det_n: sdc2-card-det-state {
pins = "gpio12";
diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
index 13cdb5b0ce40..a3ab0bd3fb01 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
@@ -987,16 +987,23 @@ &mdss_dp0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
status = "okay";
};
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1e_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
&pcie0_port0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -1013,13 +1020,6 @@ wifi@0 {
};
};
-&pcie0_phy {
- vdda-phy-supply = <&vreg_l1e_0p88>;
- vdda-pll-supply = <&vreg_l3e_1p2>;
-
- status = "okay";
-};
-
&pm8550_flash {
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
index cf4e4e9d9e26..bf0b16d690e6 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts
@@ -510,8 +510,6 @@ &i2c_master_hub_0 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
status = "okay";
@@ -523,6 +521,11 @@ &pcie0_phy {
status = "okay";
};
+&pcie0_port0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+};
+
&pm8550_gpios {
volume_up_n: volume-up-n-state {
pins = "gpio6";
diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
index 9f347bea6c74..a23ebd3cd065 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts
@@ -584,9 +584,6 @@ cirrus,gpio-ctrl2 {
};
&pcie0 {
- wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
- perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
@@ -600,6 +597,11 @@ &pcie0_phy {
status = "okay";
};
+&pcie0_port0 {
+ reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+};
+
&pm8550_flash {
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 0e701e709235..9bbc31346f90 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2397,9 +2397,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
power-domains = <&gcc PCIE_0_GDSC>;
- phys = <&pcie0_phy>;
- phy-names = "pciephy";
-
operating-points-v2 = <&pcie0_opp_table>;
status = "disabled";
@@ -2461,6 +2458,8 @@ pcie0_port0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie0_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -2583,9 +2582,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
power-domains = <&gcc PCIE_1_GDSC>;
- phys = <&pcie1_phy>;
- phy-names = "pciephy";
-
operating-points-v2 = <&pcie1_opp_table>;
status = "disabled";
@@ -2663,6 +2659,8 @@ pcie1_port0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie1_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
--
2.34.1
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v2 15/15] arm64: dts: qcom: sm8550: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 15/15] arm64: dts: qcom: sm8550: " Krishna Chaitanya Chundru
@ 2026-09-17 15:16 ` Abel Vesa
2026-09-18 10:09 ` Konrad Dybcio
1 sibling, 0 replies; 42+ messages in thread
From: Abel Vesa @ 2026-09-17 15:16 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel,
Neil Armstrong
On 26-09-17 17:55:29, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys and phy-names from the controller to
> the existing pcieport0 and newly labeled pcie1_port0, allowing
> board-level overrides. Move perst-gpios/wake-gpios from the
> controller overrides to the respective port nodes in the board files,
> renaming perst-gpios to reset-gpios to match the binding used in the
> root port context.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 15/15] arm64: dts: qcom: sm8550: Move PCIe phy and GPIOs to root port node
2026-09-17 12:25 ` [PATCH v2 15/15] arm64: dts: qcom: sm8550: " Krishna Chaitanya Chundru
2026-09-17 15:16 ` Abel Vesa
@ 2026-09-18 10:09 ` Konrad Dybcio
1 sibling, 0 replies; 42+ messages in thread
From: Konrad Dybcio @ 2026-09-18 10:09 UTC (permalink / raw)
To: Krishna Chaitanya Chundru, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong
On 9/17/26 2:25 PM, Krishna Chaitanya Chundru wrote:
> The PCIe phy reference and the perst/wake GPIO properties are
> per root port and belong in the root port node (pcie@0), not in the
> RC controller node. Move phys and phy-names from the controller to
> the existing pcieport0 and newly labeled pcie1_port0, allowing
> board-level overrides. Move perst-gpios/wake-gpios from the
> controller overrides to the respective port nodes in the board files,
> renaming perst-gpios to reset-gpios to match the binding used in the
> root port context.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 42+ messages in thread