Re: [PATCH 4/4] MIPS: sgi-ip32: Fence PIO reads on CRIME 1.1

["Imre Kaloz" <kaloz@kernel.org>]

On Thu, Nov 5, 2026, at 16:43, Thomas Bogendoerfer wrote:
> On Wed, Oct 21, 2026 at 09:24:18PM +0200, Imre Kaloz wrote:
>> On CRIME 1.1, a MACE or PCI read within about 2us of a read of some PCI
>> registers (aic7880 HCNTRL, INTSTAT, ERROR) can return that read's data.
>
> this reads strange, can you clarify what is happening ?

When the CPU reads one of those aic7880 registers and issues another
uncached load right after it, the second load sometimes returns the
first one's data instead of its own: readb() of HCNTRL returns 0x02,
and the readb() that follows returns 0x02 as well. The second read
does not have to go to the same chip; the other aic7880 and MACE's
MAC_CTRL get the stale data too.

It only shows up with audio and SCSI DMA running, a few hundred times
in 25 million read pairs. A gap of 2us between the two loads cures it,
masking interrupts alone does not. CRIME 1.4 does not do it, and IRIX
also delays around each PCI PIO read on CRIME 1.1.

I'll reword that paragraph in a v2.


Thanks,
Imre