[PATCH v7 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs

[PATCH v7 0/5] iommu/arm-smmu: introduction of ACTLR implementation for Qualcomm SoCs

[Bibek Kumar Patro]

This patch series consist of five parts and covers the following:

1. Re-enable context caching for Qualcomm SoCs to retain prefetcher
   settings during reset and runtime suspend.

2. Remove cfg inside qcom_smmu structure and replace it with single
   pointer to qcom_smmu_match_data avoiding replication of multiple
   members from same.

3. Introduce intital set of driver changes to implement ACTLR register
   for custom prefetcher settings in Qualcomm SoCs.

4. Add ACTLR data and implementation operations for SM8550.

5. Add ACTLR data and implementation operations for SC7280.

Changes in v7 from v6:
 Changes to incorporate suggestions from Dmitry as follows:
 - Use io_start address instead of compatible string to identify the
   correct instance by comparing with smmu start address and check for
   which smmu the corresponding actlr table is to be picked.
Link to v6:
https://lore.kernel.org/all/20231220133808.5654-1-quic_bibekkum@quicinc.com/

Changes in v6 from v5:
 - Remove extra Suggested-by tags.
 - Add return check for arm_mmu500_reset in 1/5 as discussed.
Link to v5:
https://lore.kernel.org/all/20231219135947.1623-1-quic_bibekkum@quicinc.com/

Changes in v5 from v4:
 New addition:
 - Modify copyright year in arm-smmu-qcom.h to 2023 from 2022.
 Changes to incorporate suggestions from Dmitry as follows:
 - Modify the defines for prefetch in (foo << bar) format
   as suggested.(FIELD_PREP could not be used in defines
   is not inside any block/function)
 Changes to incorporate suggestions from Konrad as follows:
 - Shift context caching enablement patch as 1/5 instead of 5/5 to
   be picked up as independent patch.
 - Fix the codestyle to orient variables in reverse xmas tree format
   for patch 1/5.
 - Fix variable name in patch 1/5 as suggested.
 Link to v4:
https://lore.kernel.org/all/20231215101827.30549-1-quic_bibekkum@quicinc.com/

Changes in v4 from v3:
 New addition:
 - Remove actlrcfg_size and use NULL end element instead to traverse
   the actlr table, as this would be a cleaner approach by removing
   redundancy of actlrcfg_size.
 - Renaming of actlr set function to arm_smmu_qcom based proprietary
   convention.
 - break from loop once sid is found and ACTLR value is initialized
   in qcom_smmu_set_actlr.
 - Modify the GFX prefetch value separating into 2 sensible defines.
 - Modify comments for prefetch defines as per SMMU-500 TRM.
 Changes to incorporate suggestions from Konrad as follows:
 - Use Reverse-Christmas-tree sorting wherever applicable.
 - Pass arguments directly to arm_smmu_set_actlr instead of creating
   duplicate variables.
 - Use array indexing instead of direct pointer addressed by new
   addition of eliminating actlrcfg_size.
 - Switch the HEX value's case from upper to lower case in SC7280
   actlrcfg table.
 Changes to incorporate suggestions from Dmitry as follows:
 - Separate changes not related to ACTLR support to different commit
   with patch 5/5.
 - Using pointer to struct for arguments in smr_is_subset().
 Changes to incorporate suggestions from Bjorn as follows:
 - fix the commit message for patch 2/5 to properly document the
   value space to avoid confusion.
 Fixed build issues reported by kernel test robot [1] for
 arm64-allyesconfig [2].
 [1]: https://lore.kernel.org/all/202312011750.Pwca3TWE-lkp@intel.com/
 [2]:
https://download.01.org/0day-ci/archive/20231201/202312011750.Pwca3TWE-lkp@intel.com/config
 Link to v3:
https://lore.kernel.org/all/20231127145412.3981-1-quic_bibekkum@quicinc.com/

Changes in v3 from v2:
 New addition:
 - Include patch 3/4 for adding ACTLR support and data for SC7280.
 - Add driver changes for actlr support in gpu smmu.
 - Add target wise actlr data and implementation ops for gpu smmu.
 Changes to incorporate suggestions from Robin as follows:
 - Match the ACTLR values with individual corresponding SID instead
   of assuming that any SMR will be programmed to match a superset of
   the data.
 - Instead of replicating each elements from qcom_smmu_match_data to
   qcom_smmu structre during smmu device creation, replace the
   replicated members with qcom_smmu_match_data structure inside
   qcom_smmu structre and handle the dereference in places that
   requires them.
 Changes to incorporate suggestions from Dmitry and Konrad as follows:
 - Maintain actlr table inside a single structure instead of
   nested structure.
 - Rename prefetch defines to more appropriately describe their
   behavior.
 - Remove SM8550 specific implementation ops and roll back to default
   qcom_smmu_500_impl implementation ops.
 - Add back the removed comments which are NAK.
 - Fix commit description for patch 4/4.
 Link to v2:
https://lore.kernel.org/all/20231114135654.30475-1-quic_bibekkum@quicinc.com/

Changes in v2 from v1:
 - Incorporated suggestions on v1 from Dmitry,Konrad,Pratyush.
 - Added defines for ACTLR values.
 - Linked sm8550 implementation structure to corresponding
   compatible string.
 - Repackaged actlr value set implementation to separate function.
 - Fixed indentation errors.
 - Link to v1:
https://lore.kernel.org/all/20231103215124.1095-1-quic_bibekkum@quicinc.com/

Changes in v1 from RFC:
 - Incorporated suggestion form Robin on RFC
 - Moved the actlr data table into driver, instead of maintaining
   it inside soc specific DT and piggybacking on exisiting iommus
   property (iommu = <SID, MASK, ACTLR>) to set this value during
   smmu probe.
 - Link to RFC:
https://lore.kernel.org/all/a01e7e60-6ead-4a9e-ba90-22a8a6bbd03f@quicinc.com/

Bibek Kumar Patro (5):
  iommu/arm-smmu: re-enable context caching in smmu reset operation
  iommu/arm-smmu: refactor qcom_smmu structure to include single pointer
  iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings
  iommu/arm-smmu: add ACTLR data and support for SM8550
  iommu/arm-smmu: add ACTLR data and support for SC7280

 .../iommu/arm/arm-smmu/arm-smmu-qcom-debug.c  |   2 +-
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c    | 216 +++++++++++++++++-
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h    |  13 +-
 drivers/iommu/arm/arm-smmu/arm-smmu.c         |   5 +-
 drivers/iommu/arm/arm-smmu/arm-smmu.h         |   5 +
 5 files changed, 231 insertions(+), 10 deletions(-)

--
2.17.1

[PATCH v7 1/5] iommu/arm-smmu: re-enable context caching in smmu reset operation

[Bibek Kumar Patro]

Default MMU-500 reset operation disables context caching in
prefetch buffer. It is however expected for context banks using
the ACTLR register to retain their prefetch value during reset
and runtime suspend.

Replace default MMU-500 reset operation with Qualcomm specific reset
operation which envelope the default reset operation and re-enables
context caching in prefetch buffer for Qualcomm SoCs.

Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
---
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 37 ++++++++++++++++++++--
 1 file changed, 34 insertions(+), 3 deletions(-)

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 549ae4dba3a6..000e207346af 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -14,6 +14,16 @@

 #define QCOM_DUMMY_VAL	-1

+/*
+ * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching in the
+ * macro TLB) and BIT(1) as CPRE (Enable context caching in the prefetch
+ * buffer). The remaining bits are implementation defined and vary across
+ * SoCs.
+ */
+
+#define CPRE			(1 << 1)
+#define CMTLB			(1 << 0)
+
 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
 {
 	return container_of(smmu, struct qcom_smmu, smmu);
@@ -376,11 +386,32 @@ static int qcom_smmu_def_domain_type(struct device *dev)
 	return match ? IOMMU_DOMAIN_IDENTITY : 0;
 }

+static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
+{
+	int ret;
+	u32 val;
+	int i;
+
+	ret = arm_mmu500_reset(smmu);
+
+	if (ret)
+		return ret;
+
+	/* arm_mmu500_reset() disables CPRE which is re-enabled here */
+	for (i = 0; i < smmu->num_context_banks; ++i) {
+		val = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
+		val |= CPRE;
+		arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, val);
+	}
+
+	return 0;
+}
+
 static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu)
 {
 	int ret;

-	arm_mmu500_reset(smmu);
+	qcom_smmu500_reset(smmu);

 	/*
 	 * To address performance degradation in non-real time clients,
@@ -407,7 +438,7 @@ static const struct arm_smmu_impl qcom_smmu_500_impl = {
 	.init_context = qcom_smmu_init_context,
 	.cfg_probe = qcom_smmu_cfg_probe,
 	.def_domain_type = qcom_smmu_def_domain_type,
-	.reset = arm_mmu500_reset,
+	.reset = qcom_smmu500_reset,
 	.write_s2cr = qcom_smmu_write_s2cr,
 	.tlb_sync = qcom_smmu_tlb_sync,
 };
@@ -432,7 +463,7 @@ static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = {
 static const struct arm_smmu_impl qcom_adreno_smmu_500_impl = {
 	.init_context = qcom_adreno_smmu_init_context,
 	.def_domain_type = qcom_smmu_def_domain_type,
-	.reset = arm_mmu500_reset,
+	.reset = qcom_smmu500_reset,
 	.alloc_context_bank = qcom_adreno_smmu_alloc_context_bank,
 	.write_sctlr = qcom_adreno_smmu_write_sctlr,
 	.tlb_sync = qcom_smmu_tlb_sync,
--
2.17.1

Re: [PATCH v7 1/5] iommu/arm-smmu: re-enable context caching in smmu reset operation

[Konrad Dybcio]

On 1/9/24 12:42, Bibek Kumar Patro wrote:
> Default MMU-500 reset operation disables context caching in
> prefetch buffer. It is however expected for context banks using
> the ACTLR register to retain their prefetch value during reset
> and runtime suspend.
> 
> Replace default MMU-500 reset operation with Qualcomm specific reset
> operation which envelope the default reset operation and re-enables
> context caching in prefetch buffer for Qualcomm SoCs.
> 
> Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
> ---
>   drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 37 ++++++++++++++++++++--
>   1 file changed, 34 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index 549ae4dba3a6..000e207346af 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -14,6 +14,16 @@
> 
>   #define QCOM_DUMMY_VAL	-1
> 
> +/*
> + * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching in the
> + * macro TLB) and BIT(1) as CPRE (Enable context caching in the prefetch
> + * buffer). The remaining bits are implementation defined and vary across
> + * SoCs.
> + */
> +
> +#define CPRE			(1 << 1)
> +#define CMTLB			(1 << 0)
> +
>   static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
>   {
>   	return container_of(smmu, struct qcom_smmu, smmu);
> @@ -376,11 +386,32 @@ static int qcom_smmu_def_domain_type(struct device *dev)
>   	return match ? IOMMU_DOMAIN_IDENTITY : 0;
>   }
> 
> +static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
> +{
> +	int ret;
> +	u32 val;
> +	int i;
> +
> +	ret = arm_mmu500_reset(smmu);
> +
> +	if (ret)
Weird empty line.. Please remove it in the next revision since you're
already going to send a new one..

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad

Re: [PATCH v7 1/5] iommu/arm-smmu: re-enable context caching in smmu reset operation

[Bibek Kumar Patro]

On 1/10/2024 4:30 PM, Konrad Dybcio wrote:
> 
> 
> On 1/9/24 12:42, Bibek Kumar Patro wrote:
>> Default MMU-500 reset operation disables context caching in
>> prefetch buffer. It is however expected for context banks using
>> the ACTLR register to retain their prefetch value during reset
>> and runtime suspend.
>>
>> Replace default MMU-500 reset operation with Qualcomm specific reset
>> operation which envelope the default reset operation and re-enables
>> context caching in prefetch buffer for Qualcomm SoCs.
>>
>> Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
>> ---
>>   drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 37 ++++++++++++++++++++--
>>   1 file changed, 34 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c 
>> b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> index 549ae4dba3a6..000e207346af 100644
>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
>> @@ -14,6 +14,16 @@
>>
>>   #define QCOM_DUMMY_VAL    -1
>>
>> +/*
>> + * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching in the
>> + * macro TLB) and BIT(1) as CPRE (Enable context caching in the prefetch
>> + * buffer). The remaining bits are implementation defined and vary 
>> across
>> + * SoCs.
>> + */
>> +
>> +#define CPRE            (1 << 1)
>> +#define CMTLB            (1 << 0)
>> +
>>   static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
>>   {
>>       return container_of(smmu, struct qcom_smmu, smmu);
>> @@ -376,11 +386,32 @@ static int qcom_smmu_def_domain_type(struct 
>> device *dev)
>>       return match ? IOMMU_DOMAIN_IDENTITY : 0;
>>   }
>>
>> +static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
>> +{
>> +    int ret;
>> +    u32 val;
>> +    int i;
>> +
>> +    ret = arm_mmu500_reset(smmu);
>> +
>> +    if (ret)
> Weird empty line.. Please remove it in the next revision since you're
> already going to send a new one..
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> 

Ack, thanks for pointing this out.
Will remove this while sending out the new patch.

Thanks & regards,
Bibek

> Konrad

[PATCH v7 2/5] iommu/arm-smmu: refactor qcom_smmu structure to include single pointer

[Bibek Kumar Patro]

qcom_smmu_match_data is static and constant so refactor qcom_smmu
to store single pointer to qcom_smmu_match_data instead of
replicating multiple child members of the same and handle the further
dereferences in the places that want them.

Suggested-by: Robin Murphy <robin.murphy@arm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
---
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c | 2 +-
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c       | 2 +-
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h       | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
index bb89d49adf8d..e9798b133cbb 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c
@@ -22,7 +22,7 @@ void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu)
 	if (__ratelimit(&rs)) {
 		dev_err(smmu->dev, "TLB sync timed out -- SMMU may be deadlocked\n");

-		cfg = qsmmu->cfg;
+		cfg = qsmmu->data->cfg;
 		if (!cfg)
 			return;

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 000e207346af..20c9836d859b 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -496,7 +496,7 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu,
 		return ERR_PTR(-ENOMEM);

 	qsmmu->smmu.impl = impl;
-	qsmmu->cfg = data->cfg;
+	qsmmu->data = data;

 	return &qsmmu->smmu;
 }
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
index 593910567b88..f3b91963e234 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
@@ -8,7 +8,7 @@

 struct qcom_smmu {
 	struct arm_smmu_device smmu;
-	const struct qcom_smmu_config *cfg;
+	const struct qcom_smmu_match_data *data;
 	bool bypass_quirk;
 	u8 bypass_cbndx;
 	u32 stall_enabled;
--
2.17.1

[PATCH v7 3/5] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings

[Bibek Kumar Patro]

Currently in Qualcomm  SoCs the default prefetch is set to 1 which allows
the TLB to fetch just the next page table. MMU-500 features ACTLR
register which is implementation defined and is used for Qualcomm SoCs
to have a custom prefetch setting enabling TLB to prefetch the next set
of page tables accordingly allowing for faster translations.

ACTLR value is unique for each SMR (Stream matching register) and stored
in a pre-populated table. This value is set to the register during
context bank initialisation.

Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
---
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 62 ++++++++++++++++++++++
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 11 +++-
 drivers/iommu/arm/arm-smmu/arm-smmu.c      |  5 +-
 drivers/iommu/arm/arm-smmu/arm-smmu.h      |  5 ++
 4 files changed, 80 insertions(+), 3 deletions(-)

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 20c9836d859b..48586952fae4 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -24,6 +24,12 @@
 #define CPRE			(1 << 1)
 #define CMTLB			(1 << 0)

+struct actlr_config {
+	u16 sid;
+	u16 mask;
+	u32 actlr;
+};
+
 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
 {
 	return container_of(smmu, struct qcom_smmu, smmu);
@@ -215,9 +221,40 @@ static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu)
 	return true;
 }

+static void qcom_smmu_set_actlr(struct device *dev, struct arm_smmu_device *smmu, int cbndx,
+		const struct actlr_config *actlrcfg)
+{
+	struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev);
+	struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
+	struct arm_smmu_smr *smr;
+	u16 mask;
+	int idx;
+	u16 id;
+	int i;
+	int j;
+
+	for (i = 0; actlrcfg[i].sid || actlrcfg[i].mask || actlrcfg[i].actlr; i++) {
+		id = actlrcfg[i].sid;
+		mask = actlrcfg[i].mask;
+
+		for_each_cfg_sme(cfg, fwspec, j, idx) {
+			smr = &smmu->smrs[idx];
+			if (smr_is_subset(smr, id, mask)) {
+				arm_smmu_cb_write(smmu, cbndx, ARM_SMMU_CB_ACTLR,
+						actlrcfg[i].actlr);
+				break;
+			}
+		}
+	}
+}
+
 static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
 		struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
 {
+	struct arm_smmu_device *smmu = smmu_domain->smmu;
+	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
+	const struct actlr_variant *actlrvar;
+	int cbndx = smmu_domain->cfg.cbndx;
 	struct adreno_smmu_priv *priv;

 	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;
@@ -248,6 +285,16 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
 	priv->set_stall = qcom_adreno_smmu_set_stall;
 	priv->resume_translation = qcom_adreno_smmu_resume_translation;

+	if (qsmmu->data->actlrvar) {
+		actlrvar = qsmmu->data->actlrvar;
+		for (; actlrvar->io_start; actlrvar++) {
+			if (actlrvar->io_start == smmu->ioaddr) {
+				qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar->actlrcfg);
+				break;
+			}
+		}
+	}
+
 	return 0;
 }

@@ -274,6 +321,21 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
 static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain,
 		struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
 {
+	struct arm_smmu_device *smmu = smmu_domain->smmu;
+	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
+	const struct actlr_variant *actlrvar;
+	int cbndx = smmu_domain->cfg.cbndx;
+
+	if (qsmmu->data->actlrvar) {
+		actlrvar = qsmmu->data->actlrvar;
+		for (; actlrvar->io_start; actlrvar++) {
+			if (actlrvar->io_start == smmu->ioaddr) {
+				qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar->actlrcfg);
+				break;
+			}
+		}
+	}
+
 	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;

 	return 0;
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
index f3b91963e234..29d26dfa2ed9 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */

 #ifndef _ARM_SMMU_QCOM_H
@@ -24,8 +24,17 @@ struct qcom_smmu_config {
 	const u32 *reg_offset;
 };

+struct actlr_config;
+
+struct actlr_variant {
+	const struct actlr_config *actlrcfg;
+	const resource_size_t io_start;
+};
+
 struct qcom_smmu_match_data {
+	const struct actlr_variant *actlrvar;
 	const struct qcom_smmu_config *cfg;
+	const int num_smmu;
 	const struct arm_smmu_impl *impl;
 	const struct arm_smmu_impl *adreno_impl;
 };
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
index d6d1a2a55cc0..0c7f700b27dd 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
@@ -990,9 +990,10 @@ static int arm_smmu_find_sme(struct arm_smmu_device *smmu, u16 id, u16 mask)
 		 * expect simply identical entries for this case, but there's
 		 * no harm in accommodating the generalisation.
 		 */
-		if ((mask & smrs[i].mask) == mask &&
-		    !((id ^ smrs[i].id) & ~smrs[i].mask))
+
+		if (smr_is_subset(&smrs[i], id, mask))
 			return i;
+
 		/*
 		 * If the new entry has any other overlap with an existing one,
 		 * though, then there always exists at least one stream ID
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
index 703fd5817ec1..2e4f65412c6b 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
@@ -501,6 +501,11 @@ static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page,
 		writeq_relaxed(val, arm_smmu_page(smmu, page) + offset);
 }

+static inline bool smr_is_subset(struct arm_smmu_smr *smrs, u16 id, u16 mask)
+{
+	return (mask & smrs->mask) == mask && !((id ^ smrs->id) & ~smrs->mask);
+}
+
 #define ARM_SMMU_GR0		0
 #define ARM_SMMU_GR1		1
 #define ARM_SMMU_CB(s, n)	((s)->numpage + (n))
--
2.17.1

Re: [PATCH v7 3/5] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings

[Pavan Kondeti]

On Tue, Jan 09, 2024 at 05:12:18PM +0530, Bibek Kumar Patro wrote:
>  static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
>  		struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
>  {
> +	struct arm_smmu_device *smmu = smmu_domain->smmu;
> +	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
> +	const struct actlr_variant *actlrvar;
> +	int cbndx = smmu_domain->cfg.cbndx;
>  	struct adreno_smmu_priv *priv;
> 
>  	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;
> @@ -248,6 +285,16 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
>  	priv->set_stall = qcom_adreno_smmu_set_stall;
>  	priv->resume_translation = qcom_adreno_smmu_resume_translation;
> 
> +	if (qsmmu->data->actlrvar) {
> +		actlrvar = qsmmu->data->actlrvar;
> +		for (; actlrvar->io_start; actlrvar++) {
> +			if (actlrvar->io_start == smmu->ioaddr) {
> +				qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar->actlrcfg);
> +				break;
> +			}
> +		}
> +	}
> +
>  	return 0;
>  }
> 
> @@ -274,6 +321,21 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
>  static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain,
>  		struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
>  {
> +	struct arm_smmu_device *smmu = smmu_domain->smmu;
> +	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
> +	const struct actlr_variant *actlrvar;
> +	int cbndx = smmu_domain->cfg.cbndx;
> +
> +	if (qsmmu->data->actlrvar) {
> +		actlrvar = qsmmu->data->actlrvar;
> +		for (; actlrvar->io_start; actlrvar++) {
> +			if (actlrvar->io_start == smmu->ioaddr) {
> +				qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar->actlrcfg);
> +				break;
> +			}
> +		}
> +	}
> +

This block and the one in qcom_adreno_smmu_init_context() are exactly
the same. Possible to do some refactoring?

>  	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;
> 
>  	return 0;
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
> index f3b91963e234..29d26dfa2ed9 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
> @@ -1,6 +1,6 @@
>  /* SPDX-License-Identifier: GPL-2.0-only */
>  /*
> - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>   */
> 

It should be 2022-2023 . 

>  #ifndef _ARM_SMMU_QCOM_H
> @@ -24,8 +24,17 @@ struct qcom_smmu_config {
>  	const u32 *reg_offset;
>  };
> 
> +struct actlr_config;
> +
> +struct actlr_variant {
> +	const struct actlr_config *actlrcfg;
> +	const resource_size_t io_start;
> +};
> +
>  struct qcom_smmu_match_data {
> +	const struct actlr_variant *actlrvar;
>  	const struct qcom_smmu_config *cfg;
> +	const int num_smmu;
>  	const struct arm_smmu_impl *impl;
>  	const struct arm_smmu_impl *adreno_impl;
>  };

qcom_smmu_match_data::num_smmu needs cleanup.

Thanks,
Pavan

Re: [PATCH v7 3/5] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings

[Bibek Kumar Patro]

On 1/10/2024 9:36 AM, Pavan Kondeti wrote:
> On Tue, Jan 09, 2024 at 05:12:18PM +0530, Bibek Kumar Patro wrote:
>>   static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
>>   		struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
>>   {
>> +	struct arm_smmu_device *smmu = smmu_domain->smmu;
>> +	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
>> +	const struct actlr_variant *actlrvar;
>> +	int cbndx = smmu_domain->cfg.cbndx;
>>   	struct adreno_smmu_priv *priv;
>>
>>   	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;
>> @@ -248,6 +285,16 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
>>   	priv->set_stall = qcom_adreno_smmu_set_stall;
>>   	priv->resume_translation = qcom_adreno_smmu_resume_translation;
>>
>> +	if (qsmmu->data->actlrvar) {
>> +		actlrvar = qsmmu->data->actlrvar;
>> +		for (; actlrvar->io_start; actlrvar++) {
>> +			if (actlrvar->io_start == smmu->ioaddr) {
>> +				qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar->actlrcfg);
>> +				break;
>> +			}
>> +		}
>> +	}
>> +
>>   	return 0;
>>   }
>>
>> @@ -274,6 +321,21 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
>>   static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain,
>>   		struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
>>   {
>> +	struct arm_smmu_device *smmu = smmu_domain->smmu;
>> +	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
>> +	const struct actlr_variant *actlrvar;
>> +	int cbndx = smmu_domain->cfg.cbndx;
>> +
>> +	if (qsmmu->data->actlrvar) {
>> +		actlrvar = qsmmu->data->actlrvar;
>> +		for (; actlrvar->io_start; actlrvar++) {
>> +			if (actlrvar->io_start == smmu->ioaddr) {
>> +				qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar->actlrcfg);
>> +				break;
>> +			}
>> +		}
>> +	}
>> +
> 
> This block and the one in qcom_adreno_smmu_init_context() are exactly
> the same. Possible to do some refactoring?
> 

I will check if this repeated blocks can be accomodated this into 
qcom_smmu_set_actlr function if that would be fine.

>>   	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;
>>
>>   	return 0;
>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
>> index f3b91963e234..29d26dfa2ed9 100644
>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h
>> @@ -1,6 +1,6 @@
>>   /* SPDX-License-Identifier: GPL-2.0-only */
>>   /*
>> - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
>> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>>    */
>>
> 
> It should be 2022-2023 .
> 

Ack

>>   #ifndef _ARM_SMMU_QCOM_H
>> @@ -24,8 +24,17 @@ struct qcom_smmu_config {
>>   	const u32 *reg_offset;
>>   };
>>
>> +struct actlr_config;
>> +
>> +struct actlr_variant {
>> +	const struct actlr_config *actlrcfg;
>> +	const resource_size_t io_start;
>> +};
>> +
>>   struct qcom_smmu_match_data {
>> +	const struct actlr_variant *actlrvar;
>>   	const struct qcom_smmu_config *cfg;
>> +	const int num_smmu;
>>   	const struct arm_smmu_impl *impl;
>>   	const struct arm_smmu_impl *adreno_impl;
>>   };
> 
> qcom_smmu_match_data::num_smmu needs cleanup.
> 

Ack, thanks for pointing this out.

Thanks & regards,
Bibek

> Thanks,
> Pavan

Re: [PATCH v7 3/5] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings

[Bibek Kumar Patro]

On 1/10/2024 4:46 PM, Bibek Kumar Patro wrote:
> 
> 
> On 1/10/2024 9:36 AM, Pavan Kondeti wrote:

[...]

>>> @@ -274,6 +321,21 @@ static const struct of_device_id 
>>> qcom_smmu_client_of_match[] __maybe_unused = {
>>>   static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain,
>>>           struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
>>>   {
>>> +    struct arm_smmu_device *smmu = smmu_domain->smmu;
>>> +    struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
>>> +    const struct actlr_variant *actlrvar;
>>> +    int cbndx = smmu_domain->cfg.cbndx;
>>> +
>>> +    if (qsmmu->data->actlrvar) {
>>> +        actlrvar = qsmmu->data->actlrvar;
>>> +        for (; actlrvar->io_start; actlrvar++) {
>>> +            if (actlrvar->io_start == smmu->ioaddr) {
>>> +                qcom_smmu_set_actlr(dev, smmu, cbndx, 
>>> actlrvar->actlrcfg);
>>> +                break;
>>> +            }
>>> +        }
>>> +    }
>>> +
>>
>> This block and the one in qcom_adreno_smmu_init_context() are exactly
>> the same. Possible to do some refactoring?
>>
> 
> I will check if this repeated blocks can be accomodated this into 
> qcom_smmu_set_actlr function if that would be fine.
> 

Also adding to this, this might increase the number of indentation 
inside qcom_smmu_set_actlr as well, to around 5. So wouldn't this
be an issue?

Thanks,
Bibek

Re: [PATCH v7 3/5] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings

[Konrad Dybcio]

On 1/10/24 13:55, Bibek Kumar Patro wrote:
> 
> 
> On 1/10/2024 4:46 PM, Bibek Kumar Patro wrote:
>>
>>
>> On 1/10/2024 9:36 AM, Pavan Kondeti wrote:
> 
> [...]
> 
>>>> @@ -274,6 +321,21 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
>>>>   static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain,
>>>>           struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
>>>>   {
>>>> +    struct arm_smmu_device *smmu = smmu_domain->smmu;
>>>> +    struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
>>>> +    const struct actlr_variant *actlrvar;
>>>> +    int cbndx = smmu_domain->cfg.cbndx;
>>>> +
>>>> +    if (qsmmu->data->actlrvar) {
>>>> +        actlrvar = qsmmu->data->actlrvar;
>>>> +        for (; actlrvar->io_start; actlrvar++) {
>>>> +            if (actlrvar->io_start == smmu->ioaddr) {
>>>> +                qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar->actlrcfg);
>>>> +                break;
>>>> +            }
>>>> +        }
>>>> +    }
>>>> +
>>>
>>> This block and the one in qcom_adreno_smmu_init_context() are exactly
>>> the same. Possible to do some refactoring?
>>>
>>
>> I will check if this repeated blocks can be accomodated this into qcom_smmu_set_actlr function if that would be fine.
>>
> 
> Also adding to this, this might increase the number of indentation inside qcom_smmu_set_actlr as well, to around 5. So wouldn't this
> be an issue?

By the way, we can refactor this:

if (qsmmu->data->actlrvar) {
	actlrvar = qsmmu->data->actlrvar;
	for (; actlrvar->io_start; actlrvar++) {
		if (actlrvar->io_start == smmu->ioaddr) {
			qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar->actlrcfg);
			break;
		}
	}
}

into

// add const u8 num_actlrcfgs to struct actrl_variant to
// save on sentinel space:
//   sizeof(u8) < sizeof(ptr) + sizeof(resource_size_t)


[declarations]
const struct actlr_variant *actlrvar = qsmmu->data->actlrvar;
int i;

[rest of the functions]

if (!actlrvar)
	return 0;

for (i = 0; i < actrlvar->num_actrlcfgs; i++) {
	if (actlrvar[i].io_start == smmu->ioaddr) {
		qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar->actlrcfg);
		break;
	}
}

Saving both on .TEXT size and indentation levels :)

Konrad

Re: [PATCH v7 3/5] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings

[Bibek Kumar Patro]

On 1/10/2024 11:26 PM, Konrad Dybcio wrote:
> 
> 
> On 1/10/24 13:55, Bibek Kumar Patro wrote:
>>
>>
>> On 1/10/2024 4:46 PM, Bibek Kumar Patro wrote:
>>>
>>>
>>> On 1/10/2024 9:36 AM, Pavan Kondeti wrote:
>>
>> [...]
>>
>>>>> @@ -274,6 +321,21 @@ static const struct of_device_id 
>>>>> qcom_smmu_client_of_match[] __maybe_unused = {
>>>>>   static int qcom_smmu_init_context(struct arm_smmu_domain 
>>>>> *smmu_domain,
>>>>>           struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
>>>>>   {
>>>>> +    struct arm_smmu_device *smmu = smmu_domain->smmu;
>>>>> +    struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
>>>>> +    const struct actlr_variant *actlrvar;
>>>>> +    int cbndx = smmu_domain->cfg.cbndx;
>>>>> +
>>>>> +    if (qsmmu->data->actlrvar) {
>>>>> +        actlrvar = qsmmu->data->actlrvar;
>>>>> +        for (; actlrvar->io_start; actlrvar++) {
>>>>> +            if (actlrvar->io_start == smmu->ioaddr) {
>>>>> +                qcom_smmu_set_actlr(dev, smmu, cbndx, 
>>>>> actlrvar->actlrcfg);
>>>>> +                break;
>>>>> +            }
>>>>> +        }
>>>>> +    }
>>>>> +
>>>>
>>>> This block and the one in qcom_adreno_smmu_init_context() are exactly
>>>> the same. Possible to do some refactoring?
>>>>
>>>
>>> I will check if this repeated blocks can be accomodated this into 
>>> qcom_smmu_set_actlr function if that would be fine.
>>>
>>
>> Also adding to this, this might increase the number of indentation 
>> inside qcom_smmu_set_actlr as well, to around 5. So wouldn't this
>> be an issue?
> 
> By the way, we can refactor this:
> 
> if (qsmmu->data->actlrvar) {
>      actlrvar = qsmmu->data->actlrvar;
>      for (; actlrvar->io_start; actlrvar++) {
>          if (actlrvar->io_start == smmu->ioaddr) {
>              qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar->actlrcfg);
>              break;
>          }
>      }
> }
> 
> into
> 
> // add const u8 num_actlrcfgs to struct actrl_variant to
> // save on sentinel space:
> //   sizeof(u8) < sizeof(ptr) + sizeof(resource_size_t)
> 

Git it, Would it be better to add this in struct qcom_smmu_match_data ?
Posted a sample below.

> 
> [declarations]
> const struct actlr_variant *actlrvar = qsmmu->data->actlrvar;
> int i;
> 
> [rest of the functions]
> 
> if (!actlrvar)
>      return 0;
>  > for (i = 0; i < actrlvar->num_actrlcfgs; i++) {
>      if (actlrvar[i].io_start == smmu->ioaddr) {
>          qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar->actlrcfg);
>          break;
>      }
> }
>  > Saving both on .TEXT size and indentation levels :)
> 
Thanks for this suggestion Konrad, will try to implement this, as it 
would reduce the indent levels to good extent.
Would something like this be okay?

static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain,
  	struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
  	const struct actlr_variant *actlrvar;
  	int cbndx = smmu_domain->cfg.cbndx;
+	int i;

+	actlrvar = qsmmu->data->actlrvar;
+
+	if (!actlrvar)
+		goto end;
+
+	for (i = 0; i < qsmmu->data->num_smmu ; i++) {
+		if (actlrvar[i].io_start == smmu->ioaddr) {
+			qcom_smmu_set_actlr(dev, smmu, cbndx,
+						actlrvar[i].actlrcfg);
+			break;
  		}
  	}

+end:
  	smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;

  	return 0;

Thanks & regards,
Bibek

> Konrad

Re: [PATCH v7 3/5] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings

[Konrad Dybcio]

On 1/11/24 19:09, Bibek Kumar Patro wrote:
> 
> 
> On 1/10/2024 11:26 PM, Konrad Dybcio wrote:
>>
>>
>> On 1/10/24 13:55, Bibek Kumar Patro wrote:
>>>
>>>
>>> On 1/10/2024 4:46 PM, Bibek Kumar Patro wrote:
>>>>
>>>>
>>>> On 1/10/2024 9:36 AM, Pavan Kondeti wrote:
>>>
>>> [...]
>>>
>>>>>> @@ -274,6 +321,21 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
>>>>>>   static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain,
>>>>>>           struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
>>>>>>   {
>>>>>> +    struct arm_smmu_device *smmu = smmu_domain->smmu;
>>>>>> +    struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
>>>>>> +    const struct actlr_variant *actlrvar;
>>>>>> +    int cbndx = smmu_domain->cfg.cbndx;
>>>>>> +
>>>>>> +    if (qsmmu->data->actlrvar) {
>>>>>> +        actlrvar = qsmmu->data->actlrvar;
>>>>>> +        for (; actlrvar->io_start; actlrvar++) {
>>>>>> +            if (actlrvar->io_start == smmu->ioaddr) {
>>>>>> +                qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar->actlrcfg);
>>>>>> +                break;
>>>>>> +            }
>>>>>> +        }
>>>>>> +    }
>>>>>> +
>>>>>
>>>>> This block and the one in qcom_adreno_smmu_init_context() are exactly
>>>>> the same. Possible to do some refactoring?
>>>>>
>>>>
>>>> I will check if this repeated blocks can be accomodated this into qcom_smmu_set_actlr function if that would be fine.
>>>>
>>>
>>> Also adding to this, this might increase the number of indentation inside qcom_smmu_set_actlr as well, to around 5. So wouldn't this
>>> be an issue?
>>
>> By the way, we can refactor this:
>>
>> if (qsmmu->data->actlrvar) {
>>      actlrvar = qsmmu->data->actlrvar;
>>      for (; actlrvar->io_start; actlrvar++) {
>>          if (actlrvar->io_start == smmu->ioaddr) {
>>              qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar->actlrcfg);
>>              break;
>>          }
>>      }
>> }
>>
>> into
>>
>> // add const u8 num_actlrcfgs to struct actrl_variant to
>> // save on sentinel space:
>> //   sizeof(u8) < sizeof(ptr) + sizeof(resource_size_t)
>>
> 
> Git it, Would it be better to add this in struct qcom_smmu_match_data ?

Yes, right.

> Posted a sample below.
> 
>>
>> [declarations]
>> const struct actlr_variant *actlrvar = qsmmu->data->actlrvar;
>> int i;
>>
>> [rest of the functions]
>>
>> if (!actlrvar)
>>      return 0;
>>  > for (i = 0; i < actrlvar->num_actrlcfgs; i++) {
>>      if (actlrvar[i].io_start == smmu->ioaddr) {
>>          qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar->actlrcfg);
>>          break;
>>      }
>> }
>>  > Saving both on .TEXT size and indentation levels :)
>>
> Thanks for this suggestion Konrad, will try to implement this, as it would reduce the indent levels to good extent.
> Would something like this be okay?
> 
> static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain,
>       struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
>       const struct actlr_variant *actlrvar;
>       int cbndx = smmu_domain->cfg.cbndx;
> +    int i;
> 
> +    actlrvar = qsmmu->data->actlrvar;
> +
> +    if (!actlrvar)
> +        goto end;
> +
> +    for (i = 0; i < qsmmu->data->num_smmu ; i++) {
> +        if (actlrvar[i].io_start == smmu->ioaddr) {
> +            qcom_smmu_set_actlr(dev, smmu, cbndx,
> +                        actlrvar[i].actlrcfg);
> +            break;
>           }
>       }
> 
> +end:
>       smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;

If you move this assignment before the actlrvar checking (there's no
dependency between them), you will get rid of the goto.

I also noticed that qcom_smmu_match_data.actlrvar could likely be
const struct actlr_variant * const (const pointer to a const
resource), similarly for actlr_variant.actlrcfg

Konrad

Re: [PATCH v7 3/5] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings

[Bibek Kumar Patro]

On 1/12/2024 3:31 PM, Konrad Dybcio wrote:
> 
> 
> On 1/11/24 19:09, Bibek Kumar Patro wrote:
>>
>>
>> On 1/10/2024 11:26 PM, Konrad Dybcio wrote:
>>>
>>>
>>> On 1/10/24 13:55, Bibek Kumar Patro wrote:
>>>>
>>>>
>>>> On 1/10/2024 4:46 PM, Bibek Kumar Patro wrote:
>>>>>
>>>>>
>>>>> On 1/10/2024 9:36 AM, Pavan Kondeti wrote:
>>>>
>>>> [...]
>>>>
>>>>>>> @@ -274,6 +321,21 @@ static const struct of_device_id 
>>>>>>> qcom_smmu_client_of_match[] __maybe_unused = {
>>>>>>>   static int qcom_smmu_init_context(struct arm_smmu_domain 
>>>>>>> *smmu_domain,
>>>>>>>           struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
>>>>>>>   {
>>>>>>> +    struct arm_smmu_device *smmu = smmu_domain->smmu;
>>>>>>> +    struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
>>>>>>> +    const struct actlr_variant *actlrvar;
>>>>>>> +    int cbndx = smmu_domain->cfg.cbndx;
>>>>>>> +
>>>>>>> +    if (qsmmu->data->actlrvar) {
>>>>>>> +        actlrvar = qsmmu->data->actlrvar;
>>>>>>> +        for (; actlrvar->io_start; actlrvar++) {
>>>>>>> +            if (actlrvar->io_start == smmu->ioaddr) {
>>>>>>> +                qcom_smmu_set_actlr(dev, smmu, cbndx, 
>>>>>>> actlrvar->actlrcfg);
>>>>>>> +                break;
>>>>>>> +            }
>>>>>>> +        }
>>>>>>> +    }
>>>>>>> +
>>>>>>
>>>>>> This block and the one in qcom_adreno_smmu_init_context() are exactly
>>>>>> the same. Possible to do some refactoring?
>>>>>>
>>>>>
>>>>> I will check if this repeated blocks can be accomodated this into 
>>>>> qcom_smmu_set_actlr function if that would be fine.
>>>>>
>>>>
>>>> Also adding to this, this might increase the number of indentation 
>>>> inside qcom_smmu_set_actlr as well, to around 5. So wouldn't this
>>>> be an issue?
>>>
>>> By the way, we can refactor this:
>>>
>>> if (qsmmu->data->actlrvar) {
>>>      actlrvar = qsmmu->data->actlrvar;
>>>      for (; actlrvar->io_start; actlrvar++) {
>>>          if (actlrvar->io_start == smmu->ioaddr) {
>>>              qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar->actlrcfg);
>>>              break;
>>>          }
>>>      }
>>> }
>>>
>>> into
>>>
>>> // add const u8 num_actlrcfgs to struct actrl_variant to
>>> // save on sentinel space:
>>> //   sizeof(u8) < sizeof(ptr) + sizeof(resource_size_t)
>>>
>>
>> Git it, Would it be better to add this in struct qcom_smmu_match_data ?
> 
> Yes, right.
> 

Actually, I noticed now, we can do both the actlr_config (num_actlrcfg 
is used) and actlr_var (num_smmu is used) in the similar by storing the 
number of elements in each of them.
something like this:

+static const struct actlr_config sc7280_apps_actlr_cfg[] = {
+	{ 0x0800, 0x24e1, PREFETCH_DEFAULT | CMTLB },
+	{ 0x2000, 0x0163, PREFETCH_DEFAULT | CMTLB },
+	{ 0x2080, 0x0461, PREFETCH_DEFAULT | CMTLB },
+	{ 0x2100, 0x0161, PREFETCH_DEFAULT | CMTLB },
+	{ 0x0900, 0x0407, PREFETCH_SHALLOW | CPRE | CMTLB },
+	{ 0x2180, 0x0027, PREFETCH_SHALLOW | CPRE | CMTLB },
+	{ 0x1000, 0x07ff, PREFETCH_DEEP | CPRE | CMTLB },
+};
+
+static const struct actlr_config sc7280_gfx_actlr_cfg[] = {
+	{ 0x0000, 0x07ff, PREFETCH_SWITCH_GFX | PREFETCH_DEEP | CPRE | CMTLB },
+};
+
+static const struct actlr_variant sc7280_actlr[] = {
+	{ .io_start = 0x15000000, .actlrcfg = sc7280_apps_actlr_cfg, 
.num_actlrcfg = 7 },
+	{ .io_start = 0x03da0000, .actlrcfg = sc7280_gfx_actlr_cfg, 
.num_actlrcfg = 1 },
+};
+
  static const struct actlr_config sm8550_apps_actlr_cfg[] = {
  	{ 0x18a0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
  	{ 0x18e0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
@@ -661,6 +680,13 @@ static const struct qcom_smmu_match_data 
sdm845_smmu_500_data = {
  	/* Also no debug configuration. */
  };

+static const struct qcom_smmu_match_data sc7280_smmu_500_impl0_data = {
+	.impl = &qcom_smmu_500_impl,
+	.adreno_impl = &qcom_adreno_smmu_500_impl,
+	.cfg = &qcom_smmu_impl0_cfg,
+	.actlrvar = sc7280_actlr,
+	.num_smmu = 2,
+};

Just for note , there's a small hiccup here as we have to manually
calculate and the number of elements in actlr_config size everytime we
add this info for a new target, won't be an issue though but just a
hindrance to automation (?)

>> Posted a sample below.
>>
>>>
>>> [declarations]
>>> const struct actlr_variant *actlrvar = qsmmu->data->actlrvar;
>>> int i;
>>>
>>> [rest of the functions]
>>>
>>> if (!actlrvar)
>>>      return 0;
>>>  > for (i = 0; i < actrlvar->num_actrlcfgs; i++) {
>>>      if (actlrvar[i].io_start == smmu->ioaddr) {
>>>          qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar->actlrcfg);
>>>          break;
>>>      }
>>> }
>>>  > Saving both on .TEXT size and indentation levels :)
>>>
>> Thanks for this suggestion Konrad, will try to implement this, as it 
>> would reduce the indent levels to good extent.
>> Would something like this be okay?
>>
>> static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain,
>>       struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
>>       const struct actlr_variant *actlrvar;
>>       int cbndx = smmu_domain->cfg.cbndx;
>> +    int i;
>>
>> +    actlrvar = qsmmu->data->actlrvar;
>> +
>> +    if (!actlrvar)
>> +        goto end;
>> +
>> +    for (i = 0; i < qsmmu->data->num_smmu ; i++) {
>> +        if (actlrvar[i].io_start == smmu->ioaddr) {
>> +            qcom_smmu_set_actlr(dev, smmu, cbndx,
>> +                        actlrvar[i].actlrcfg);
>> +            break;
>>           }
>>       }
>>
>> +end:
>>       smmu_domain->cfg.flush_walk_prefer_tlbiasid = true;
> 
> If you move this assignment before the actlrvar checking (there's no
> dependency between them), you will get rid of the goto.
> 

Ack thanks, it's tlb flush operation so won't be an issue moving this
before the check.

> I also noticed that qcom_smmu_match_data.actlrvar could likely be
> const struct actlr_variant * const (const pointer to a const
> resource), similarly for actlr_variant.actlrcfg
> 

Sure, make sense, as we aren't aiming to modify these values later on.

Would address all these inputs in next version.

Thanks & regards,
Bibek

> Konrad

Re: [PATCH v7 3/5] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings

[Dmitry Baryshkov]

On Fri, 12 Jan 2024 at 15:07, Bibek Kumar Patro
<quic_bibekkum@quicinc.com> wrote:
>
>
>
> On 1/12/2024 3:31 PM, Konrad Dybcio wrote:
> >
> >
> > On 1/11/24 19:09, Bibek Kumar Patro wrote:
> >>
> >>
> >> On 1/10/2024 11:26 PM, Konrad Dybcio wrote:
> >>>
> >>>
> >>> On 1/10/24 13:55, Bibek Kumar Patro wrote:
> >>>>
> >>>>
> >>>> On 1/10/2024 4:46 PM, Bibek Kumar Patro wrote:
> >>>>>
> >>>>>
> >>>>> On 1/10/2024 9:36 AM, Pavan Kondeti wrote:
> >>>>
> >>>> [...]
> >>>>
> >>>>>>> @@ -274,6 +321,21 @@ static const struct of_device_id
> >>>>>>> qcom_smmu_client_of_match[] __maybe_unused = {
> >>>>>>>   static int qcom_smmu_init_context(struct arm_smmu_domain
> >>>>>>> *smmu_domain,
> >>>>>>>           struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
> >>>>>>>   {
> >>>>>>> +    struct arm_smmu_device *smmu = smmu_domain->smmu;
> >>>>>>> +    struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
> >>>>>>> +    const struct actlr_variant *actlrvar;
> >>>>>>> +    int cbndx = smmu_domain->cfg.cbndx;
> >>>>>>> +
> >>>>>>> +    if (qsmmu->data->actlrvar) {
> >>>>>>> +        actlrvar = qsmmu->data->actlrvar;
> >>>>>>> +        for (; actlrvar->io_start; actlrvar++) {
> >>>>>>> +            if (actlrvar->io_start == smmu->ioaddr) {
> >>>>>>> +                qcom_smmu_set_actlr(dev, smmu, cbndx,
> >>>>>>> actlrvar->actlrcfg);
> >>>>>>> +                break;
> >>>>>>> +            }
> >>>>>>> +        }
> >>>>>>> +    }
> >>>>>>> +
> >>>>>>
> >>>>>> This block and the one in qcom_adreno_smmu_init_context() are exactly
> >>>>>> the same. Possible to do some refactoring?
> >>>>>>
> >>>>>
> >>>>> I will check if this repeated blocks can be accomodated this into
> >>>>> qcom_smmu_set_actlr function if that would be fine.
> >>>>>
> >>>>
> >>>> Also adding to this, this might increase the number of indentation
> >>>> inside qcom_smmu_set_actlr as well, to around 5. So wouldn't this
> >>>> be an issue?
> >>>
> >>> By the way, we can refactor this:
> >>>
> >>> if (qsmmu->data->actlrvar) {
> >>>      actlrvar = qsmmu->data->actlrvar;
> >>>      for (; actlrvar->io_start; actlrvar++) {
> >>>          if (actlrvar->io_start == smmu->ioaddr) {
> >>>              qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar->actlrcfg);
> >>>              break;
> >>>          }
> >>>      }
> >>> }
> >>>
> >>> into
> >>>
> >>> // add const u8 num_actlrcfgs to struct actrl_variant to
> >>> // save on sentinel space:
> >>> //   sizeof(u8) < sizeof(ptr) + sizeof(resource_size_t)
> >>>
> >>
> >> Git it, Would it be better to add this in struct qcom_smmu_match_data ?
> >
> > Yes, right.
> >
>
> Actually, I noticed now, we can do both the actlr_config (num_actlrcfg
> is used) and actlr_var (num_smmu is used) in the similar by storing the
> number of elements in each of them.
> something like this:
>
> +static const struct actlr_config sc7280_apps_actlr_cfg[] = {
> +       { 0x0800, 0x24e1, PREFETCH_DEFAULT | CMTLB },
> +       { 0x2000, 0x0163, PREFETCH_DEFAULT | CMTLB },
> +       { 0x2080, 0x0461, PREFETCH_DEFAULT | CMTLB },
> +       { 0x2100, 0x0161, PREFETCH_DEFAULT | CMTLB },
> +       { 0x0900, 0x0407, PREFETCH_SHALLOW | CPRE | CMTLB },
> +       { 0x2180, 0x0027, PREFETCH_SHALLOW | CPRE | CMTLB },
> +       { 0x1000, 0x07ff, PREFETCH_DEEP | CPRE | CMTLB },
> +};
> +
> +static const struct actlr_config sc7280_gfx_actlr_cfg[] = {
> +       { 0x0000, 0x07ff, PREFETCH_SWITCH_GFX | PREFETCH_DEEP | CPRE | CMTLB },
> +};
> +
> +static const struct actlr_variant sc7280_actlr[] = {
> +       { .io_start = 0x15000000, .actlrcfg = sc7280_apps_actlr_cfg,
> .num_actlrcfg = 7 },
> +       { .io_start = 0x03da0000, .actlrcfg = sc7280_gfx_actlr_cfg,
> .num_actlrcfg = 1 },
> +};
> +
>   static const struct actlr_config sm8550_apps_actlr_cfg[] = {
>         { 0x18a0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
>         { 0x18e0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
> @@ -661,6 +680,13 @@ static const struct qcom_smmu_match_data
> sdm845_smmu_500_data = {
>         /* Also no debug configuration. */
>   };
>
> +static const struct qcom_smmu_match_data sc7280_smmu_500_impl0_data = {
> +       .impl = &qcom_smmu_500_impl,
> +       .adreno_impl = &qcom_adreno_smmu_500_impl,
> +       .cfg = &qcom_smmu_impl0_cfg,
> +       .actlrvar = sc7280_actlr,
> +       .num_smmu = 2,
> +};
>
> Just for note , there's a small hiccup here as we have to manually
> calculate and the number of elements in actlr_config size everytime we
> add this info for a new target, won't be an issue though but just a
> hindrance to automation (?)

Just use ARRAY_SIZE(sc7280_actlr).


-- 
With best wishes
Dmitry

Re: [PATCH v7 3/5] iommu/arm-smmu: introduction of ACTLR for custom prefetcher settings

[Bibek Kumar Patro]

On 1/12/2024 6:44 PM, Dmitry Baryshkov wrote:
> On Fri, 12 Jan 2024 at 15:07, Bibek Kumar Patro
> <quic_bibekkum@quicinc.com> wrote:
>>
>>
>>
>> On 1/12/2024 3:31 PM, Konrad Dybcio wrote:
>>>
>>>
>>> On 1/11/24 19:09, Bibek Kumar Patro wrote:
>>>>
>>>>
>>>> On 1/10/2024 11:26 PM, Konrad Dybcio wrote:
>>>>>
>>>>>
>>>>> On 1/10/24 13:55, Bibek Kumar Patro wrote:
>>>>>>
>>>>>>
>>>>>> On 1/10/2024 4:46 PM, Bibek Kumar Patro wrote:
>>>>>>>
>>>>>>>
>>>>>>> On 1/10/2024 9:36 AM, Pavan Kondeti wrote:
>>>>>>
>>>>>> [...]
>>>>>>
>>>>>>>>> @@ -274,6 +321,21 @@ static const struct of_device_id
>>>>>>>>> qcom_smmu_client_of_match[] __maybe_unused = {
>>>>>>>>>    static int qcom_smmu_init_context(struct arm_smmu_domain
>>>>>>>>> *smmu_domain,
>>>>>>>>>            struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
>>>>>>>>>    {
>>>>>>>>> +    struct arm_smmu_device *smmu = smmu_domain->smmu;
>>>>>>>>> +    struct qcom_smmu *qsmmu = to_qcom_smmu(smmu);
>>>>>>>>> +    const struct actlr_variant *actlrvar;
>>>>>>>>> +    int cbndx = smmu_domain->cfg.cbndx;
>>>>>>>>> +
>>>>>>>>> +    if (qsmmu->data->actlrvar) {
>>>>>>>>> +        actlrvar = qsmmu->data->actlrvar;
>>>>>>>>> +        for (; actlrvar->io_start; actlrvar++) {
>>>>>>>>> +            if (actlrvar->io_start == smmu->ioaddr) {
>>>>>>>>> +                qcom_smmu_set_actlr(dev, smmu, cbndx,
>>>>>>>>> actlrvar->actlrcfg);
>>>>>>>>> +                break;
>>>>>>>>> +            }
>>>>>>>>> +        }
>>>>>>>>> +    }
>>>>>>>>> +
>>>>>>>>
>>>>>>>> This block and the one in qcom_adreno_smmu_init_context() are exactly
>>>>>>>> the same. Possible to do some refactoring?
>>>>>>>>
>>>>>>>
>>>>>>> I will check if this repeated blocks can be accomodated this into
>>>>>>> qcom_smmu_set_actlr function if that would be fine.
>>>>>>>
>>>>>>
>>>>>> Also adding to this, this might increase the number of indentation
>>>>>> inside qcom_smmu_set_actlr as well, to around 5. So wouldn't this
>>>>>> be an issue?
>>>>>
>>>>> By the way, we can refactor this:
>>>>>
>>>>> if (qsmmu->data->actlrvar) {
>>>>>       actlrvar = qsmmu->data->actlrvar;
>>>>>       for (; actlrvar->io_start; actlrvar++) {
>>>>>           if (actlrvar->io_start == smmu->ioaddr) {
>>>>>               qcom_smmu_set_actlr(dev, smmu, cbndx, actlrvar->actlrcfg);
>>>>>               break;
>>>>>           }
>>>>>       }
>>>>> }
>>>>>
>>>>> into
>>>>>
>>>>> // add const u8 num_actlrcfgs to struct actrl_variant to
>>>>> // save on sentinel space:
>>>>> //   sizeof(u8) < sizeof(ptr) + sizeof(resource_size_t)
>>>>>
>>>>
>>>> Git it, Would it be better to add this in struct qcom_smmu_match_data ?
>>>
>>> Yes, right.
>>>
>>
>> Actually, I noticed now, we can do both the actlr_config (num_actlrcfg
>> is used) and actlr_var (num_smmu is used) in the similar by storing the
>> number of elements in each of them.
>> something like this:
>>
>> +static const struct actlr_config sc7280_apps_actlr_cfg[] = {
>> +       { 0x0800, 0x24e1, PREFETCH_DEFAULT | CMTLB },
>> +       { 0x2000, 0x0163, PREFETCH_DEFAULT | CMTLB },
>> +       { 0x2080, 0x0461, PREFETCH_DEFAULT | CMTLB },
>> +       { 0x2100, 0x0161, PREFETCH_DEFAULT | CMTLB },
>> +       { 0x0900, 0x0407, PREFETCH_SHALLOW | CPRE | CMTLB },
>> +       { 0x2180, 0x0027, PREFETCH_SHALLOW | CPRE | CMTLB },
>> +       { 0x1000, 0x07ff, PREFETCH_DEEP | CPRE | CMTLB },
>> +};
>> +
>> +static const struct actlr_config sc7280_gfx_actlr_cfg[] = {
>> +       { 0x0000, 0x07ff, PREFETCH_SWITCH_GFX | PREFETCH_DEEP | CPRE | CMTLB },
>> +};
>> +
>> +static const struct actlr_variant sc7280_actlr[] = {
>> +       { .io_start = 0x15000000, .actlrcfg = sc7280_apps_actlr_cfg,
>> .num_actlrcfg = 7 },
>> +       { .io_start = 0x03da0000, .actlrcfg = sc7280_gfx_actlr_cfg,
>> .num_actlrcfg = 1 },
>> +};
>> +
>>    static const struct actlr_config sm8550_apps_actlr_cfg[] = {
>>          { 0x18a0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
>>          { 0x18e0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
>> @@ -661,6 +680,13 @@ static const struct qcom_smmu_match_data
>> sdm845_smmu_500_data = {
>>          /* Also no debug configuration. */
>>    };
>>
>> +static const struct qcom_smmu_match_data sc7280_smmu_500_impl0_data = {
>> +       .impl = &qcom_smmu_500_impl,
>> +       .adreno_impl = &qcom_adreno_smmu_500_impl,
>> +       .cfg = &qcom_smmu_impl0_cfg,
>> +       .actlrvar = sc7280_actlr,
>> +       .num_smmu = 2,
>> +};
>>
>> Just for note , there's a small hiccup here as we have to manually
>> calculate and the number of elements in actlr_config size everytime we
>> add this info for a new target, won't be an issue though but just a
>> hindrance to automation (?)
> 
> Just use ARRAY_SIZE(sc7280_actlr).
> 

Noted, ARRAY_SIZE makes sense now for this new io_address based
matching.

Thanks & regards,
Bibek

> 

[PATCH v7 4/5] iommu/arm-smmu: add ACTLR data and support for SM8550

[Bibek Kumar Patro]

Add ACTLR data table for SM8550 along with support for
same including SM8550 specific implementation operations.

Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
---
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 85 ++++++++++++++++++++++
 1 file changed, 85 insertions(+)

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 48586952fae4..24a289149cd3 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -23,6 +23,12 @@

 #define CPRE			(1 << 1)
 #define CMTLB			(1 << 0)
+#define PREFETCH_SHIFT		8
+#define PREFETCH_DEFAULT	0
+#define PREFETCH_SHALLOW	(1 << PREFETCH_SHIFT)
+#define PREFETCH_MODERATE	(2 << PREFETCH_SHIFT)
+#define PREFETCH_DEEP		(3 << PREFETCH_SHIFT)
+#define PREFETCH_SWITCH_GFX	(5 << 3)

 struct actlr_config {
 	u16 sid;
@@ -30,6 +36,76 @@ struct actlr_config {
 	u32 actlr;
 };

+static const struct actlr_config sm8550_apps_actlr_cfg[] = {
+	{ 0x18a0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+	{ 0x18e0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+	{ 0x0800, 0x0020, PREFETCH_DEFAULT | CMTLB },
+	{ 0x1800, 0x00c0, PREFETCH_DEFAULT | CMTLB },
+	{ 0x1820, 0x0000, PREFETCH_DEFAULT | CMTLB },
+	{ 0x1860, 0x0000, PREFETCH_DEFAULT | CMTLB },
+	{ 0x0c01, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x0c02, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x0c03, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x0c04, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x0c05, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x0c06, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x0c07, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x0c08, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x0c09, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x0c0c, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x0c0d, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x0c0e, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x0c0f, 0x0020, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x1961, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x1962, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x1963, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x1964, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x1965, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x1966, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x1967, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x1968, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x1969, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x196c, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x196d, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x196e, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x196f, 0x0000, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x19c1, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x19c2, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x19c3, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x19c4, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x19c5, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x19c6, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x19c7, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x19c8, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x19c9, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x19cc, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x19cd, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x19ce, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x19cf, 0x0010, PREFETCH_DEEP | CPRE | CMTLB },
+	{ 0x1c00, 0x0002, PREFETCH_SHALLOW | CPRE | CMTLB },
+	{ 0x1c01, 0x0000, PREFETCH_DEFAULT | CMTLB },
+	{ 0x1920, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+	{ 0x1923, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+	{ 0x1924, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+	{ 0x1940, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+	{ 0x1941, 0x0004, PREFETCH_SHALLOW | CPRE | CMTLB },
+	{ 0x1943, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+	{ 0x1944, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+	{ 0x1947, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
+	{},
+};
+
+static const struct actlr_config sm8550_gfx_actlr_cfg[] = {
+	{ 0x0000, 0x03ff, PREFETCH_SWITCH_GFX | PREFETCH_DEEP | CPRE | CMTLB },
+	{},
+};
+
+static const struct actlr_variant sm8550_actlr[] = {
+	{ sm8550_apps_actlr_cfg, 0x15000000 },
+	{ sm8550_gfx_actlr_cfg, 0x03da0000 },
+	{},
+};
+
 static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
 {
 	return container_of(smmu, struct qcom_smmu, smmu);
@@ -597,6 +673,14 @@ static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
 	/* Also no debug configuration. */
 };

+
+static const struct qcom_smmu_match_data sm8550_smmu_500_impl0_data = {
+	.impl = &qcom_smmu_500_impl,
+	.adreno_impl = &qcom_adreno_smmu_500_impl,
+	.cfg = &qcom_smmu_impl0_cfg,
+	.actlrvar = sm8550_actlr,
+};
+
 static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
 	.impl = &qcom_smmu_500_impl,
 	.adreno_impl = &qcom_adreno_smmu_500_impl,
@@ -631,6 +715,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
 	{ .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
 	{ .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
 	{ .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
+	{ .compatible = "qcom,sm8550-smmu-500", .data = &sm8550_smmu_500_impl0_data },
 	{ .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },
 	{ }
 };
--
2.17.1

Re: [PATCH v7 4/5] iommu/arm-smmu: add ACTLR data and support for SM8550

[Pavan Kondeti]

On Tue, Jan 09, 2024 at 05:12:19PM +0530, Bibek Kumar Patro wrote:
> +static const struct actlr_variant sm8550_actlr[] = {
> +	{ sm8550_apps_actlr_cfg, 0x15000000 },
> +	{ sm8550_gfx_actlr_cfg, 0x03da0000 },
> +	{},
> +};
> +
>  static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu)
>  {
>  	return container_of(smmu, struct qcom_smmu, smmu);
> @@ -597,6 +673,14 @@ static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
>  	/* Also no debug configuration. */
>  };
> 
> +
> +static const struct qcom_smmu_match_data sm8550_smmu_500_impl0_data = {
> +	.impl = &qcom_smmu_500_impl,
> +	.adreno_impl = &qcom_adreno_smmu_500_impl,
> +	.cfg = &qcom_smmu_impl0_cfg,
> +	.actlrvar = sm8550_actlr,
> +};
> +

I wish there is Rust like struct update syntax possible here. All we need
here is to update qcom_smmu_match_data::actlrvar member here to the generic
qcom_smmu_500_impl0_data struct data.

>  static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = {
>  	.impl = &qcom_smmu_500_impl,
>  	.adreno_impl = &qcom_adreno_smmu_500_impl,
> @@ -631,6 +715,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
>  	{ .compatible = "qcom,sm8250-smmu-500", .data = &qcom_smmu_500_impl0_data },
>  	{ .compatible = "qcom,sm8350-smmu-500", .data = &qcom_smmu_500_impl0_data },
>  	{ .compatible = "qcom,sm8450-smmu-500", .data = &qcom_smmu_500_impl0_data },
> +	{ .compatible = "qcom,sm8550-smmu-500", .data = &sm8550_smmu_500_impl0_data },
>  	{ .compatible = "qcom,smmu-500", .data = &qcom_smmu_500_impl0_data },
>  	{ }
>  };

Given that ACTLR data is different across SoCs, would it be a good idea
to decouple it from the qcom_smmu_match_data struct and directly get it
via of_device_is_compatible() from context init functions.  The ACTLR
data will have a compatible string associated with it, we lookup for the
device compatible in this table and select the ACTLR accordingly. This
way, we don't need to add more entries to qcom_smmu_impl_of_match and
keep using the "qcom,smmu-500" for driver match data. 

I have made this suggestion to keep the rule introduced in commit
80b71080720e ("iommu/arm-smmu-qcom: Add generic qcom,smmu-500 match
entry") relavant. I will let Dmitry to provide the guidance here.

Thanks,
Pavan

Re: [PATCH v7 4/5] iommu/arm-smmu: add ACTLR data and support for SM8550

[Konrad Dybcio]

On 1/9/24 12:42, Bibek Kumar Patro wrote:
> Add ACTLR data table for SM8550 along with support for
> same including SM8550 specific implementation operations.
> 
> Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
> ---
[...]

> +static const struct actlr_variant sm8550_actlr[] = {
> +	{ sm8550_apps_actlr_cfg, 0x15000000 },
> +	{ sm8550_gfx_actlr_cfg, 0x03da0000 },
> +	{},
> +};

Please use C99 designated initializers and put the address first.

Konrad

Re: [PATCH v7 4/5] iommu/arm-smmu: add ACTLR data and support for SM8550

[Bibek Kumar Patro]

On 1/10/2024 4:19 PM, Konrad Dybcio wrote:
> 
> 
> On 1/9/24 12:42, Bibek Kumar Patro wrote:
>> Add ACTLR data table for SM8550 along with support for
>> same including SM8550 specific implementation operations.
>>
>> Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
>> ---
> [...]
> 
>> +static const struct actlr_variant sm8550_actlr[] = {
>> +    { sm8550_apps_actlr_cfg, 0x15000000 },
>> +    { sm8550_gfx_actlr_cfg, 0x03da0000 },
>> +    {},
>> +};
> 
> Please use C99 designated initializers and put the address first.
> 

Noted, thanks for this input. Will take care of this in next patch.

Thanks & regards,
Bibek

> Konrad

[PATCH v7 5/5] iommu/arm-smmu: add ACTLR data and support for SC7280

[Bibek Kumar Patro]

Add ACTLR data table for SC7280 along with support for
same including SC7280 specific implementation operations.

Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
---
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 30 +++++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 24a289149cd3..a4dab3dd0b4e 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -36,6 +36,28 @@ struct actlr_config {
 	u32 actlr;
 };

+static const struct actlr_config sc7280_apps_actlr_cfg[] = {
+	{ 0x0800, 0x24e1, PREFETCH_DEFAULT | CMTLB },
+	{ 0x2000, 0x0163, PREFETCH_DEFAULT | CMTLB },
+	{ 0x2080, 0x0461, PREFETCH_DEFAULT | CMTLB },
+	{ 0x2100, 0x0161, PREFETCH_DEFAULT | CMTLB },
+	{ 0x0900, 0x0407, PREFETCH_SHALLOW | CPRE | CMTLB },
+	{ 0x2180, 0x0027, PREFETCH_SHALLOW | CPRE | CMTLB },
+	{ 0x1000, 0x07ff, PREFETCH_DEEP | CPRE | CMTLB },
+	{},
+};
+
+static const struct actlr_config sc7280_gfx_actlr_cfg[] = {
+	{ 0x0000, 0x07ff, PREFETCH_SWITCH_GFX | PREFETCH_DEEP | CPRE | CMTLB },
+	{},
+};
+
+static const struct actlr_variant sc7280_actlr[] = {
+	{ sc7280_apps_actlr_cfg, 0x15000000 },
+	{ sc7280_gfx_actlr_cfg, 0x03da0000 },
+	{},
+};
+
 static const struct actlr_config sm8550_apps_actlr_cfg[] = {
 	{ 0x18a0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
 	{ 0x18e0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB },
@@ -673,6 +695,12 @@ static const struct qcom_smmu_match_data sdm845_smmu_500_data = {
 	/* Also no debug configuration. */
 };

+static const struct qcom_smmu_match_data sc7280_smmu_500_impl0_data = {
+	.impl = &qcom_smmu_500_impl,
+	.adreno_impl = &qcom_adreno_smmu_500_impl,
+	.cfg = &qcom_smmu_impl0_cfg,
+	.actlrvar = sc7280_actlr,
+};

 static const struct qcom_smmu_match_data sm8550_smmu_500_impl0_data = {
 	.impl = &qcom_smmu_500_impl,
@@ -698,7 +726,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = {
 	{ .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data  },
 	{ .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data },
 	{ .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data },
-	{ .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data },
+	{ .compatible = "qcom,sc7280-smmu-500", .data = &sc7280_smmu_500_impl0_data },
 	{ .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data },
 	{ .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data },
 	{ .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data },
--
2.17.1