[PATCH 0/6] riscv: hwprobe: do not report disabled extensions

[PATCH 0/6] riscv: hwprobe: do not report disabled extensions

[Radim Krčmář]

I understand hwprobe to be an interface to query the features of
user-mode execution environment.
Some RISC-V extensions need to be enabled in user-mode through the use
of higher-mode controls (like sstatus, senvcfg, or sstateen), and when
we for some reason never enable the extensions (disabled in config, by
boot parameter, heterogenous platform alignment, etc.), hwprobe should
not report that the extensions are present.

This series brings the user-mode extension reporting into a state that
is more consistent with the user-mode observable extension set.

There are minor overlaps with Andy Chui's series to report the dynamic
state of higher-mode controls through hwprobe [1].
Andy's series adds another layer that can query features whose
availability depends on runtime variables, while this series is covering
constraints that the user-mode cannot influence.

This series doesn't touch Zicntr and Zihpm since those will require more
discussion.  Zicntr could be reported through Andy's mechanism based on
the sysctl status and Zihpm might be somehow reinterpreted for perf
availability or just ignored.

Applies to riscv/for-next just as well as to v7.3-rc6.

---
1: https://lore.kernel.org/linux-riscv/20260725001614.2578617-1-tchiu@tenstorrent.com/


Radim Krčmář (6):
  riscv: hwprobe: Report FP extensions only when available
  riscv: hwprobe: Report Zicbom and Zicboz only when available
  riscv: hwprobe: Report Zicfilp and Zicfiss only when available
  riscv: hwprobe: Report Supm only when available
  riscv: hwprobe: Report XTheadVector only when available
  riscv: hwprobe: Report SiFive vector extensions only when available

 arch/riscv/include/asm/usercfi.h              |  9 ++-
 arch/riscv/kernel/sys_hwprobe.c               | 55 ++++++++++++-------
 .../kernel/vendor_extensions/sifive_hwprobe.c | 14 +++--
 .../kernel/vendor_extensions/thead_hwprobe.c  |  5 +-
 4 files changed, 55 insertions(+), 28 deletions(-)

-- 
2.55.0

[PATCH 1/6] riscv: hwprobe: Report FP extensions only when available

[Radim Krčmář]

User-mode use of Zcd, Zcf, Zfa, Zfbfmin, Zfh and Zfhmin requires
non-Off sstatus.FS, which we set only when has_fpu() (CONFIG_FPU and D
on all harts).  The vector floating-point extensions Zve32f, Zve64f,
Zve64d, Zvfbfmin, Zvfbfwma, Zvfh and Zvfhmin require it as well, but
hwprobe gates them only on has_vector().  hwprobe otherwise reports the
extensions from the per-hart ISA bitmaps alone, so it can advertise
extensions that are always disabled in user-mode.

Report correct environment to user-mode.

Fixes: 2e2cf5581fcc ("riscv: cpufeature: add validation for zfa, zfh and zfhmin")
Fixes: de8f8282a969 ("riscv: hwprobe: add zve Vector subextensions into hwprobe interface")
Fixes: 5dadda5e6a59 ("riscv: hwprobe: export Zvfh[min] ISA extensions")
Signed-off-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
---
 arch/riscv/kernel/sys_hwprobe.c | 31 ++++++++++++++++++-------------
 1 file changed, 18 insertions(+), 13 deletions(-)

diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 7818e1d32622..b57ccd116bb1 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -146,15 +146,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 		if (has_vector()) {
 			EXT_KEY(isainfo->isa, ZVBB, pair->value, missing);
 			EXT_KEY(isainfo->isa, ZVBC, pair->value, missing);
-			EXT_KEY(isainfo->isa, ZVE32F, pair->value, missing);
 			EXT_KEY(isainfo->isa, ZVE32X, pair->value, missing);
-			EXT_KEY(isainfo->isa, ZVE64D, pair->value, missing);
-			EXT_KEY(isainfo->isa, ZVE64F, pair->value, missing);
 			EXT_KEY(isainfo->isa, ZVE64X, pair->value, missing);
-			EXT_KEY(isainfo->isa, ZVFBFMIN, pair->value, missing);
-			EXT_KEY(isainfo->isa, ZVFBFWMA, pair->value, missing);
-			EXT_KEY(isainfo->isa, ZVFH, pair->value, missing);
-			EXT_KEY(isainfo->isa, ZVFHMIN, pair->value, missing);
 			EXT_KEY(isainfo->isa, ZVKB, pair->value, missing);
 			EXT_KEY(isainfo->isa, ZVKG, pair->value, missing);
 			EXT_KEY(isainfo->isa, ZVKNED, pair->value, missing);
@@ -163,14 +156,26 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 			EXT_KEY(isainfo->isa, ZVKSED, pair->value, missing);
 			EXT_KEY(isainfo->isa, ZVKSH, pair->value, missing);
 			EXT_KEY(isainfo->isa, ZVKT, pair->value, missing);
+
+			if (has_fpu()) {
+				EXT_KEY(isainfo->isa, ZVE32F, pair->value, missing);
+				EXT_KEY(isainfo->isa, ZVE64D, pair->value, missing);
+				EXT_KEY(isainfo->isa, ZVE64F, pair->value, missing);
+				EXT_KEY(isainfo->isa, ZVFBFMIN, pair->value, missing);
+				EXT_KEY(isainfo->isa, ZVFBFWMA, pair->value, missing);
+				EXT_KEY(isainfo->isa, ZVFH, pair->value, missing);
+				EXT_KEY(isainfo->isa, ZVFHMIN, pair->value, missing);
+			}
 		}
 
-		EXT_KEY(isainfo->isa, ZCD, pair->value, missing);
-		EXT_KEY(isainfo->isa, ZCF, pair->value, missing);
-		EXT_KEY(isainfo->isa, ZFA, pair->value, missing);
-		EXT_KEY(isainfo->isa, ZFBFMIN, pair->value, missing);
-		EXT_KEY(isainfo->isa, ZFH, pair->value, missing);
-		EXT_KEY(isainfo->isa, ZFHMIN, pair->value, missing);
+		if (has_fpu()) {
+			EXT_KEY(isainfo->isa, ZCD, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZCF, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZFA, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZFBFMIN, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZFH, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZFHMIN, pair->value, missing);
+		}
 
 		if (IS_ENABLED(CONFIG_RISCV_ISA_SUPM))
 			EXT_KEY(isainfo->isa, SUPM, pair->value, missing);
-- 
2.55.0

Re: [PATCH 1/6] riscv: hwprobe: Report FP extensions only when available

[Charlie Jenkins]

> User-mode use of Zcd, Zcf, Zfa, Zfbfmin, Zfh and Zfhmin requires
> non-Off sstatus.FS, which we set only when has_fpu() (CONFIG_FPU and D
> on all harts).  The vector floating-point extensions Zve32f, Zve64f,
> Zve64d, Zvfbfmin, Zvfbfwma, Zvfh and Zvfhmin require it as well, but
> hwprobe gates them only on has_vector().  hwprobe otherwise reports the
> extensions from the per-hart ISA bitmaps alone, so it can advertise
> extensions that are always disabled in user-mode.
> 
> Report correct environment to user-mode.
> 
> Fixes: 2e2cf5581fcc ("riscv: cpufeature: add validation for zfa, zfh and zfhmin")
> Fixes: de8f8282a969 ("riscv: hwprobe: add zve Vector subextensions into hwprobe interface")
> Fixes: 5dadda5e6a59 ("riscv: hwprobe: export Zvfh[min] ISA extensions")
> Signed-off-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
>
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index 7818e1d32622..b57ccd116bb1 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -146,15 +146,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
>  		if (has_vector()) {
>  			EXT_KEY(isainfo->isa, ZVBB, pair->value, missing);
>  			EXT_KEY(isainfo->isa, ZVBC, pair->value, missing);
> -			EXT_KEY(isainfo->isa, ZVE32F, pair->value, missing);
>  			EXT_KEY(isainfo->isa, ZVE32X, pair->value, missing);
> -			EXT_KEY(isainfo->isa, ZVE64D, pair->value, missing);
> -			EXT_KEY(isainfo->isa, ZVE64F, pair->value, missing);
>  			EXT_KEY(isainfo->isa, ZVE64X, pair->value, missing);
> -			EXT_KEY(isainfo->isa, ZVFBFMIN, pair->value, missing);
> -			EXT_KEY(isainfo->isa, ZVFBFWMA, pair->value, missing);
> -			EXT_KEY(isainfo->isa, ZVFH, pair->value, missing);
> -			EXT_KEY(isainfo->isa, ZVFHMIN, pair->value, missing);
>  			EXT_KEY(isainfo->isa, ZVKB, pair->value, missing);
>  			EXT_KEY(isainfo->isa, ZVKG, pair->value, missing);
>  			EXT_KEY(isainfo->isa, ZVKNED, pair->value, missing);
> @@ -163,14 +156,26 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
>  			EXT_KEY(isainfo->isa, ZVKSED, pair->value, missing);
>  			EXT_KEY(isainfo->isa, ZVKSH, pair->value, missing);
>  			EXT_KEY(isainfo->isa, ZVKT, pair->value, missing);
> +
> +			if (has_fpu()) {
> +				EXT_KEY(isainfo->isa, ZVE32F, pair->value, missing);
> +				EXT_KEY(isainfo->isa, ZVE64D, pair->value, missing);
> +				EXT_KEY(isainfo->isa, ZVE64F, pair->value, missing);
> +				EXT_KEY(isainfo->isa, ZVFBFMIN, pair->value, missing);
> +				EXT_KEY(isainfo->isa, ZVFBFWMA, pair->value, missing);
> +				EXT_KEY(isainfo->isa, ZVFH, pair->value, missing);
> +				EXT_KEY(isainfo->isa, ZVFHMIN, pair->value, missing);

The vector Kconfig is gated on FPU=y so the vector instructions can't
ever be enabled when FPU=n.

-- 
- Charlie

Re: [PATCH 1/6] riscv: hwprobe: Report FP extensions only when available

[Radim Krčmář]

2026-10-06T16:54:53-07:00, Charlie Jenkins <thecharlesjenkins@gmail.com>:
>> User-mode use of Zcd, Zcf, Zfa, Zfbfmin, Zfh and Zfhmin requires
>> non-Off sstatus.FS, which we set only when has_fpu() (CONFIG_FPU and D
>> on all harts).  The vector floating-point extensions Zve32f, Zve64f,
>> Zve64d, Zvfbfmin, Zvfbfwma, Zvfh and Zvfhmin require it as well, but
>> hwprobe gates them only on has_vector().  hwprobe otherwise reports the
>> extensions from the per-hart ISA bitmaps alone, so it can advertise
>> extensions that are always disabled in user-mode.
>> 
>> Report correct environment to user-mode.
>> 
>> Fixes: 2e2cf5581fcc ("riscv: cpufeature: add validation for zfa, zfh and zfhmin")
>> Fixes: de8f8282a969 ("riscv: hwprobe: add zve Vector subextensions into hwprobe interface")
>> Fixes: 5dadda5e6a59 ("riscv: hwprobe: export Zvfh[min] ISA extensions")
>> Signed-off-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
>>
>> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
>> index 7818e1d32622..b57ccd116bb1 100644
>> --- a/arch/riscv/kernel/sys_hwprobe.c
>> +++ b/arch/riscv/kernel/sys_hwprobe.c
>> @@ -146,15 +146,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
>>  		if (has_vector()) {
>>  			EXT_KEY(isainfo->isa, ZVBB, pair->value, missing);
>>  			EXT_KEY(isainfo->isa, ZVBC, pair->value, missing);
>> -			EXT_KEY(isainfo->isa, ZVE32F, pair->value, missing);
>>  			EXT_KEY(isainfo->isa, ZVE32X, pair->value, missing);
>> -			EXT_KEY(isainfo->isa, ZVE64D, pair->value, missing);
>> -			EXT_KEY(isainfo->isa, ZVE64F, pair->value, missing);
>>  			EXT_KEY(isainfo->isa, ZVE64X, pair->value, missing);
>> -			EXT_KEY(isainfo->isa, ZVFBFMIN, pair->value, missing);
>> -			EXT_KEY(isainfo->isa, ZVFBFWMA, pair->value, missing);
>> -			EXT_KEY(isainfo->isa, ZVFH, pair->value, missing);
>> -			EXT_KEY(isainfo->isa, ZVFHMIN, pair->value, missing);
>>  			EXT_KEY(isainfo->isa, ZVKB, pair->value, missing);
>>  			EXT_KEY(isainfo->isa, ZVKG, pair->value, missing);
>>  			EXT_KEY(isainfo->isa, ZVKNED, pair->value, missing);
>> @@ -163,14 +156,26 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
>>  			EXT_KEY(isainfo->isa, ZVKSED, pair->value, missing);
>>  			EXT_KEY(isainfo->isa, ZVKSH, pair->value, missing);
>>  			EXT_KEY(isainfo->isa, ZVKT, pair->value, missing);
>> +
>> +			if (has_fpu()) {
>> +				EXT_KEY(isainfo->isa, ZVE32F, pair->value, missing);
>> +				EXT_KEY(isainfo->isa, ZVE64D, pair->value, missing);
>> +				EXT_KEY(isainfo->isa, ZVE64F, pair->value, missing);
>> +				EXT_KEY(isainfo->isa, ZVFBFMIN, pair->value, missing);
>> +				EXT_KEY(isainfo->isa, ZVFBFWMA, pair->value, missing);
>> +				EXT_KEY(isainfo->isa, ZVFH, pair->value, missing);
>> +				EXT_KEY(isainfo->isa, ZVFHMIN, pair->value, missing);
>
> The vector Kconfig is gated on FPU=y so the vector instructions can't
> ever be enabled when FPU=n.

Right, I'll make the commit message clearer in v2.
(Zve32x and hence has_vector() can technically exist without CONFIG_FPU,
 so future implementations might require use to remove the dependency.)

I think this check is adding a bit of sanity, although the platforms
where it comes into play are already very wild.

has_fpu()=false and has_vector()=true is possible on heterogenous
platforms since the filtering/validation of floating vector extensions
happens on F extension support on that hart alone.

If other hart doesn't support F, all harts will trap floating vector
extension as mstatus.FS=Off, although scalar vector should still work
because has_vector() isn't keyed on V support, but only on Zve32x.

Thanks.

Re: [PATCH 1/6] riscv: hwprobe: Report FP extensions only when available

[Charlie Jenkins]

On Wed, Oct 07, 2026 at 09:46:31AM +0200, Radim Krčmář wrote:
> 2026-10-06T16:54:53-07:00, Charlie Jenkins <thecharlesjenkins@gmail.com>:
> >> User-mode use of Zcd, Zcf, Zfa, Zfbfmin, Zfh and Zfhmin requires
> >> non-Off sstatus.FS, which we set only when has_fpu() (CONFIG_FPU and D
> >> on all harts).  The vector floating-point extensions Zve32f, Zve64f,
> >> Zve64d, Zvfbfmin, Zvfbfwma, Zvfh and Zvfhmin require it as well, but
> >> hwprobe gates them only on has_vector().  hwprobe otherwise reports the
> >> extensions from the per-hart ISA bitmaps alone, so it can advertise
> >> extensions that are always disabled in user-mode.
> >> 
> >> Report correct environment to user-mode.
> >> 
> >> Fixes: 2e2cf5581fcc ("riscv: cpufeature: add validation for zfa, zfh and zfhmin")
> >> Fixes: de8f8282a969 ("riscv: hwprobe: add zve Vector subextensions into hwprobe interface")
> >> Fixes: 5dadda5e6a59 ("riscv: hwprobe: export Zvfh[min] ISA extensions")
> >> Signed-off-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
> >>
> >> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> >> index 7818e1d32622..b57ccd116bb1 100644
> >> --- a/arch/riscv/kernel/sys_hwprobe.c
> >> +++ b/arch/riscv/kernel/sys_hwprobe.c
> >> @@ -146,15 +146,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> >>  		if (has_vector()) {
> >>  			EXT_KEY(isainfo->isa, ZVBB, pair->value, missing);
> >>  			EXT_KEY(isainfo->isa, ZVBC, pair->value, missing);
> >> -			EXT_KEY(isainfo->isa, ZVE32F, pair->value, missing);
> >>  			EXT_KEY(isainfo->isa, ZVE32X, pair->value, missing);
> >> -			EXT_KEY(isainfo->isa, ZVE64D, pair->value, missing);
> >> -			EXT_KEY(isainfo->isa, ZVE64F, pair->value, missing);
> >>  			EXT_KEY(isainfo->isa, ZVE64X, pair->value, missing);
> >> -			EXT_KEY(isainfo->isa, ZVFBFMIN, pair->value, missing);
> >> -			EXT_KEY(isainfo->isa, ZVFBFWMA, pair->value, missing);
> >> -			EXT_KEY(isainfo->isa, ZVFH, pair->value, missing);
> >> -			EXT_KEY(isainfo->isa, ZVFHMIN, pair->value, missing);
> >>  			EXT_KEY(isainfo->isa, ZVKB, pair->value, missing);
> >>  			EXT_KEY(isainfo->isa, ZVKG, pair->value, missing);
> >>  			EXT_KEY(isainfo->isa, ZVKNED, pair->value, missing);
> >> @@ -163,14 +156,26 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> >>  			EXT_KEY(isainfo->isa, ZVKSED, pair->value, missing);
> >>  			EXT_KEY(isainfo->isa, ZVKSH, pair->value, missing);
> >>  			EXT_KEY(isainfo->isa, ZVKT, pair->value, missing);
> >> +
> >> +			if (has_fpu()) {
> >> +				EXT_KEY(isainfo->isa, ZVE32F, pair->value, missing);
> >> +				EXT_KEY(isainfo->isa, ZVE64D, pair->value, missing);
> >> +				EXT_KEY(isainfo->isa, ZVE64F, pair->value, missing);
> >> +				EXT_KEY(isainfo->isa, ZVFBFMIN, pair->value, missing);
> >> +				EXT_KEY(isainfo->isa, ZVFBFWMA, pair->value, missing);
> >> +				EXT_KEY(isainfo->isa, ZVFH, pair->value, missing);
> >> +				EXT_KEY(isainfo->isa, ZVFHMIN, pair->value, missing);
> >
> > The vector Kconfig is gated on FPU=y so the vector instructions can't
> > ever be enabled when FPU=n.
> 
> Right, I'll make the commit message clearer in v2.
> (Zve32x and hence has_vector() can technically exist without CONFIG_FPU,
>  so future implementations might require use to remove the dependency.)

Yeah having vector dependent on FPU is not really accurate but since
nobody has built vector hardware without an FPU it hasn't come up yet. I
feel that would be highly unlikely to happen and probably not a good
idea so maybe it won't ever happen...

> 
> I think this check is adding a bit of sanity, although the platforms
> where it comes into play are already very wild.

Yeah I agree, it is reasonable to add the check here.

- Charlie

> 
> has_fpu()=false and has_vector()=true is possible on heterogenous
> platforms since the filtering/validation of floating vector extensions
> happens on F extension support on that hart alone.
> 
> If other hart doesn't support F, all harts will trap floating vector
> extension as mstatus.FS=Off, although scalar vector should still work
> because has_vector() isn't keyed on V support, but only on Zve32x.
> 
> Thanks.

[PATCH 2/6] riscv: hwprobe: Report Zicbom and Zicboz only when available

[Radim Krčmář]

User-mode use of Zicbom and Zicboz requires senvcfg.CBCFE and
senvcfg.CBZE, respectively, which we set only when all harts have the
extension.  hwprobe reports the extensions from the per-hart ISA bitmaps
alone, so it can advertise extensions that are always disabled in
user-mode.

Report correct environment to user-mode.

Fixes: 1b57747e978f ("riscv: Enable cbo.zero only when all harts support Zicboz")
Fixes: eb1003970940 ("RISC-V: hwprobe: Expose Zicbom extension and its block size")
Signed-off-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
---
 arch/riscv/kernel/sys_hwprobe.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index b57ccd116bb1..c74e36e8fcdd 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -91,6 +91,12 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 	if (has_vector() && riscv_isa_extension_available(NULL, V))
 		pair->value |= RISCV_HWPROBE_IMA_V;
 
+	if (riscv_isa_extension_available(NULL, ZICBOM))
+		pair->value |= RISCV_HWPROBE_EXT_ZICBOM;
+
+	if (riscv_isa_extension_available(NULL, ZICBOZ))
+		pair->value |= RISCV_HWPROBE_EXT_ZICBOZ;
+
 	/*
 	 * Loop through and record extensions that 1) anyone has, and 2) anyone
 	 * doesn't have.
@@ -120,9 +126,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 		EXT_KEY(isainfo->isa, ZCB, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZCLSD, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZCMOP, pair->value, missing);
-		EXT_KEY(isainfo->isa, ZICBOM, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICBOP, pair->value, missing);
-		EXT_KEY(isainfo->isa, ZICBOZ, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICFILP, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICNTR, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICOND, pair->value, missing);
-- 
2.55.0

[PATCH 3/6] riscv: hwprobe: Report Zicfilp and Zicfiss only when available

[Radim Krčmář]

User-mode use of Zicfilp and Zicfiss requires senvcfg.LPE and
senvcfg.SSE, respectively, which we set only when is_user_lpad_enabled()
and is_user_shstk_enabled() (CONFIG_RISCV_USER_CFI, the extension on all
harts, and not disabled by riscv_nousercfi).  hwprobe reports the
extensions from the per-hart ISA bitmaps alone, so it can advertise
extensions that are always disabled in user-mode.

Report correct environment to user-mode.

The changes to arch/riscv/include/asm/usercfi.h avoid
IS_ENABLED(CONFIG_RISCV_USER_CFI) guards in the conditions.

Fixes: 30c3099036a9 ("riscv/hwprobe: add zicfilp / zicfiss enumeration in hwprobe")
Signed-off-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
---
 Cases where new harts fail to enable user cfi aren't curently handled
 very well.

 The rest of usercfi.h is currently using macros instead of inline
 functions, but I couldn't really bear to follow the same pattern...

 arch/riscv/include/asm/usercfi.h | 9 ++++++---
 arch/riscv/kernel/sys_hwprobe.c  | 9 +++++++--
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/include/asm/usercfi.h b/arch/riscv/include/asm/usercfi.h
index 61ee02cee297..bbde171bccde 100644
--- a/arch/riscv/include/asm/usercfi.h
+++ b/arch/riscv/include/asm/usercfi.h
@@ -48,6 +48,8 @@ bool is_indir_lp_enabled(struct task_struct *task);
 bool is_indir_lp_locked(struct task_struct *task);
 void set_indir_lp_status(struct task_struct *task, bool enable);
 void set_indir_lp_lock(struct task_struct *task, bool lock);
+bool is_user_shstk_enabled(void);
+bool is_user_lpad_enabled(void);
 
 #define PR_SHADOW_STACK_SUPPORTED_STATUS_MASK (PR_SHADOW_STACK_ENABLE)
 #define PR_CFI_SUPPORTED_STATUS_MASK (PR_CFI_ENABLE | PR_CFI_DISABLE | PR_CFI_LOCK)
@@ -88,10 +90,11 @@ void set_indir_lp_lock(struct task_struct *task, bool lock);
 
 #define get_active_shstk(task) 0UL
 
-#endif /* CONFIG_RISCV_USER_CFI */
+static __always_inline bool is_user_shstk_enabled(void) { return false; }
 
-bool is_user_shstk_enabled(void);
-bool is_user_lpad_enabled(void);
+static __always_inline bool is_user_lpad_enabled(void) { return false; }
+
+#endif /* CONFIG_RISCV_USER_CFI */
 
 #endif /* __ASSEMBLER__ */
 
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index c74e36e8fcdd..477d8fd780a6 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -14,6 +14,7 @@
 #include <asm/switch_to.h>
 #include <asm/uaccess.h>
 #include <asm/unistd.h>
+#include <asm/usercfi.h>
 #include <asm/vector.h>
 #include <asm/vendor_extensions/mips_hwprobe.h>
 #include <asm/vendor_extensions/sifive_hwprobe.h>
@@ -97,6 +98,9 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 	if (riscv_isa_extension_available(NULL, ZICBOZ))
 		pair->value |= RISCV_HWPROBE_EXT_ZICBOZ;
 
+	if (is_user_lpad_enabled())
+		pair->value |= RISCV_HWPROBE_EXT_ZICFILP;
+
 	/*
 	 * Loop through and record extensions that 1) anyone has, and 2) anyone
 	 * doesn't have.
@@ -127,7 +131,6 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 		EXT_KEY(isainfo->isa, ZCLSD, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZCMOP, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICBOP, pair->value, missing);
-		EXT_KEY(isainfo->isa, ZICFILP, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICNTR, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICOND, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZIHINTNTL, pair->value, missing);
@@ -197,6 +200,9 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair,
 
 	pair->value = 0;
 
+	if (is_user_shstk_enabled())
+		pair->value |= RISCV_HWPROBE_EXT_ZICFISS;
+
 	/*
 	 * Loop through and record extensions that 1) anyone has, and 2) anyone
 	 * doesn't have.
@@ -210,7 +216,6 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair,
 		 * configuration, as no other checks, besides presence
 		 * in the hart_isa bitmap, are made.
 		 */
-		EXT_KEY(isainfo->isa, ZICFISS, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICCLSM, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICCAMOA, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICCIF, pair->value, missing);
-- 
2.55.0

[PATCH 4/6] riscv: hwprobe: Report Supm only when available

[Radim Krčmář]

The RISC-V ISA defines Supm as

  "An extension that indicates that there is pointer-masking support
  available in user mode, with some facility provided in the application
  execution environment to control pointer masking."

Our facility always returns -EINVAL unless Supm support is configured,
the pointer masking ISA extension is globally present, and the user-mode
is running in 64-bit mode.

Hiding Supm in compat tasks would add complexity that doesn't seem
justified as 32-bit code has no reason to look at Supm anyway.
Reporting based on the a global sysctl toggle isn't done.

Do not report Supm when some harts lack the extension, because it's not
available on any hart in that case.

(Reporting Supm when only PMLEN=0 is supported isn't great, but doesn't
 violate the text of the extension and we ought to have Supm7 and Supm16
 extensions if we care about precision.)

Fixes: 3c2e0aff7b4f ("riscv: hwprobe: Export the Supm ISA extension")
Signed-off-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
---
 The compat hiding and global sysctl toggle better fit in Andy's series.

 arch/riscv/kernel/sys_hwprobe.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 477d8fd780a6..9a864e050acf 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -101,6 +101,10 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 	if (is_user_lpad_enabled())
 		pair->value |= RISCV_HWPROBE_EXT_ZICFILP;
 
+	if (IS_ENABLED(CONFIG_RISCV_ISA_SUPM) &&
+	    riscv_isa_extension_available(NULL, SUPM))
+		pair->value |= RISCV_HWPROBE_EXT_SUPM;
+
 	/*
 	 * Loop through and record extensions that 1) anyone has, and 2) anyone
 	 * doesn't have.
@@ -183,9 +187,6 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 			EXT_KEY(isainfo->isa, ZFH, pair->value, missing);
 			EXT_KEY(isainfo->isa, ZFHMIN, pair->value, missing);
 		}
-
-		if (IS_ENABLED(CONFIG_RISCV_ISA_SUPM))
-			EXT_KEY(isainfo->isa, SUPM, pair->value, missing);
 	}
 
 	/* Now turn off reporting features if any CPU is missing it. */
-- 
2.55.0

[PATCH 5/6] riscv: hwprobe: Report XTheadVector only when available

[Radim Krčmář]

User-mode use of XTheadVector requires non-Off sstatus.VS, which we set
only when has_xtheadvector() (CONFIG_RISCV_ISA_XTHEADVECTOR and
XTheadVector on all harts).  XTheadVector also bundles operations with
floating state, which additionally requires non-Off sstatus.FS and hence
has_fpu().  hwprobe reports XTheadVector from the per-hart vendor ISA
bitmaps alone, so it can advertise an extension that is always disabled
in user-mode.

Report correct environment to user-mode.

Fixes: a5ea53da65c5 ("riscv: hwprobe: Add thead vendor extension probing")
Signed-off-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
---
 The check could be done before the loop if we care about optimizing the
 code.
 XTheadVector can also be per-process disabled by prctl, which belongs
 to Andy's series.

 arch/riscv/kernel/vendor_extensions/thead_hwprobe.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c
index 2eba34011786..f07aa1c8acac 100644
--- a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c
+++ b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 
+#include <asm/switch_to.h>
+#include <asm/vector.h>
 #include <asm/vendor_extensions/thead.h>
 #include <asm/vendor_extensions/thead_hwprobe.h>
 #include <asm/vendor_extensions/vendor_hwprobe.h>
@@ -14,6 +16,7 @@ void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpu
 {
 	VENDOR_EXTENSION_SUPPORTED(pair, cpus,
 				   riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap, {
-		VENDOR_EXT_KEY(XTHEADVECTOR);
+		if (has_xtheadvector() && has_fpu())
+			VENDOR_EXT_KEY(XTHEADVECTOR);
 	});
 }
-- 
2.55.0

Re: [PATCH 5/6] riscv: hwprobe: Report XTheadVector only when available

[Charlie Jenkins]

> User-mode use of XTheadVector requires non-Off sstatus.VS, which we set
> only when has_xtheadvector() (CONFIG_RISCV_ISA_XTHEADVECTOR and
> XTheadVector on all harts).  XTheadVector also bundles operations with
> floating state, which additionally requires non-Off sstatus.FS and hence
> has_fpu().  hwprobe reports XTheadVector from the per-hart vendor ISA
> bitmaps alone, so it can advertise an extension that is always disabled
> in user-mode.
> 
> Report correct environment to user-mode.
> 
> Fixes: a5ea53da65c5 ("riscv: hwprobe: Add thead vendor extension probing")
> Signed-off-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
>
> diff --git a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c
> index 2eba34011786..f07aa1c8acac 100644
> --- a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c
> +++ b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c
> @@ -1,5 +1,7 @@
>  // SPDX-License-Identifier: GPL-2.0-only
>  
> +#include <asm/switch_to.h>
> +#include <asm/vector.h>
>  #include <asm/vendor_extensions/thead.h>
>  #include <asm/vendor_extensions/thead_hwprobe.h>
>  #include <asm/vendor_extensions/vendor_hwprobe.h>
> @@ -14,6 +16,7 @@ void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpu
>  {
>  	VENDOR_EXTENSION_SUPPORTED(pair, cpus,
>  				   riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap, {
> -		VENDOR_EXT_KEY(XTHEADVECTOR);
> +		if (has_xtheadvector() && has_fpu())

xtheadvector is also gated on FPU=y so this is a reduntant addition. Is
it worthwhile to make this change?

-- 
- Charlie

Re: [PATCH 5/6] riscv: hwprobe: Report XTheadVector only when available

[Radim Krčmář]

2026-10-06T16:54:53-07:00, Charlie Jenkins <thecharlesjenkins@gmail.com>:
>> User-mode use of XTheadVector requires non-Off sstatus.VS, which we set
>> only when has_xtheadvector() (CONFIG_RISCV_ISA_XTHEADVECTOR and
>> XTheadVector on all harts).  XTheadVector also bundles operations with
>> floating state, which additionally requires non-Off sstatus.FS and hence
>> has_fpu().  hwprobe reports XTheadVector from the per-hart vendor ISA
>> bitmaps alone, so it can advertise an extension that is always disabled
>> in user-mode.
>> 
>> Report correct environment to user-mode.
>> 
>> Fixes: a5ea53da65c5 ("riscv: hwprobe: Add thead vendor extension probing")
>> Signed-off-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
>>
>> diff --git a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c
>> index 2eba34011786..f07aa1c8acac 100644
>> --- a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c
>> +++ b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c
>> @@ -1,5 +1,7 @@
>>  // SPDX-License-Identifier: GPL-2.0-only
>>  
>> +#include <asm/switch_to.h>
>> +#include <asm/vector.h>
>>  #include <asm/vendor_extensions/thead.h>
>>  #include <asm/vendor_extensions/thead_hwprobe.h>
>>  #include <asm/vendor_extensions/vendor_hwprobe.h>
>> @@ -14,6 +16,7 @@ void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpu
>>  {
>>  	VENDOR_EXTENSION_SUPPORTED(pair, cpus,
>>  				   riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap, {
>> -		VENDOR_EXT_KEY(XTHEADVECTOR);
>> +		if (has_xtheadvector() && has_fpu())
>
> xtheadvector is also gated on FPU=y so this is a reduntant addition. Is
> it worthwhile to make this change?

With CONFIG_FPU=y, has_fpu() is set to false when a single hart doesn't
have the D, and has_xtheadvector() could still be true.

>                                                                      Is
> it worthwhile to make this change?

I think that it's sensible to mimic the validation we do for the
non-vendor extension, but users of vendor extensions likely already have
to go out of their way to utilize them, so they can do the sanity checks
too... I can drop the last two patches in v2.

Thanks.

Re: [PATCH 5/6] riscv: hwprobe: Report XTheadVector only when available

[Charlie Jenkins]

On Wed, Oct 07, 2026 at 09:59:30AM +0200, Radim Krčmář wrote:
> 2026-10-06T16:54:53-07:00, Charlie Jenkins <thecharlesjenkins@gmail.com>:
> >> User-mode use of XTheadVector requires non-Off sstatus.VS, which we set
> >> only when has_xtheadvector() (CONFIG_RISCV_ISA_XTHEADVECTOR and
> >> XTheadVector on all harts).  XTheadVector also bundles operations with
> >> floating state, which additionally requires non-Off sstatus.FS and hence
> >> has_fpu().  hwprobe reports XTheadVector from the per-hart vendor ISA
> >> bitmaps alone, so it can advertise an extension that is always disabled
> >> in user-mode.
> >> 
> >> Report correct environment to user-mode.
> >> 
> >> Fixes: a5ea53da65c5 ("riscv: hwprobe: Add thead vendor extension probing")
> >> Signed-off-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
> >>
> >> diff --git a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c
> >> index 2eba34011786..f07aa1c8acac 100644
> >> --- a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c
> >> +++ b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c
> >> @@ -1,5 +1,7 @@
> >>  // SPDX-License-Identifier: GPL-2.0-only
> >>  
> >> +#include <asm/switch_to.h>
> >> +#include <asm/vector.h>
> >>  #include <asm/vendor_extensions/thead.h>
> >>  #include <asm/vendor_extensions/thead_hwprobe.h>
> >>  #include <asm/vendor_extensions/vendor_hwprobe.h>
> >> @@ -14,6 +16,7 @@ void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpu
> >>  {
> >>  	VENDOR_EXTENSION_SUPPORTED(pair, cpus,
> >>  				   riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap, {
> >> -		VENDOR_EXT_KEY(XTHEADVECTOR);
> >> +		if (has_xtheadvector() && has_fpu())
> >
> > xtheadvector is also gated on FPU=y so this is a reduntant addition. Is
> > it worthwhile to make this change?
> 
> With CONFIG_FPU=y, has_fpu() is set to false when a single hart doesn't
> have the D, and has_xtheadvector() could still be true.

Ahh that's a good point.

> 
> >                                                                      Is
> > it worthwhile to make this change?
> 
> I think that it's sensible to mimic the validation we do for the
> non-vendor extension, but users of vendor extensions likely already have
> to go out of their way to utilize them, so they can do the sanity checks
> too... I can drop the last two patches in v2.

I don't know, it seems better to keep standardization if possible and
leave the check in here to mimic the standard extensions?

- Charlie

> 
> Thanks.

[PATCH 6/6] riscv: hwprobe: Report SiFive vector extensions only when available

[Radim Krčmář]

User-mode use of the SiFive vector extensions requires non-Off
sstatus.VS, which we set only when has_vector() (CONFIG_RISCV_ISA_V and
Zve32x on all harts).  Xsfvfnrclipxfqf and Xsfvfwmaccqqq also execute
floating-point instructions, which additionally require non-Off
sstatus.FS and hence has_fpu().  hwprobe reports the extensions from the
per-hart vendor ISA bitmaps alone, so it can advertise extensions that
are always disabled in user-mode.

Report correct environment to user-mode.

Fixes: 1a6274f03534 ("riscv: hwprobe: Add SiFive vendor extension support and probe for xsfqmaccdod and xsfqmaccqoq")
Fixes: 1d91224394c9 ("riscv: hwprobe: Add SiFive xsfvfnrclipxfqf vendor extension")
Fixes: d9669e33c8fa ("riscv: hwprobe: Add SiFive xsfvfwmaccqqq vendor extension")
Signed-off-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
---
 Same as THeadVector, this could be optimized better.

 .../kernel/vendor_extensions/sifive_hwprobe.c      | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c b/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c
index 1f77f6309763..bcea4f7a81c4 100644
--- a/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c
+++ b/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 
+#include <asm/switch_to.h>
+#include <asm/vector.h>
 #include <asm/vendor_extensions/sifive.h>
 #include <asm/vendor_extensions/sifive_hwprobe.h>
 #include <asm/vendor_extensions/vendor_hwprobe.h>
@@ -14,9 +16,13 @@ void hwprobe_isa_vendor_ext_sifive_0(struct riscv_hwprobe *pair, const struct cp
 {
 	VENDOR_EXTENSION_SUPPORTED(pair, cpus,
 				   riscv_isa_vendor_ext_list_sifive.per_hart_isa_bitmap, {
-		VENDOR_EXT_KEY(XSFVQMACCDOD);
-		VENDOR_EXT_KEY(XSFVQMACCQOQ);
-		VENDOR_EXT_KEY(XSFVFNRCLIPXFQF);
-		VENDOR_EXT_KEY(XSFVFWMACCQQQ);
+		if (has_vector()) {
+			VENDOR_EXT_KEY(XSFVQMACCDOD);
+			VENDOR_EXT_KEY(XSFVQMACCQOQ);
+			if (has_fpu()) {
+				VENDOR_EXT_KEY(XSFVFNRCLIPXFQF);
+				VENDOR_EXT_KEY(XSFVFWMACCQQQ);
+			}
+		}
 	});
 }
-- 
2.55.0