[PATCH v1 0/3] qcom: ipq5424: Add LLCC/system-cache-controller

[PATCH v1 0/3] qcom: ipq5424: Add LLCC/system-cache-controller

[Varadarajan Narayanan]

Unlike other Qcom SoCs, IPQ5424 doesn't have multiple instances
of LLCC IP and hence doesn't have a LLCC_BROADCAST register
space, and the LLCC & LLCC_BROADCAST point to the same register
space.

Alter the driver accordingly and add the relevant entries for
enabling LLCC/system-cache-controller on the Qcom IPQ5424 SoC.

Depends On:
https://lore.kernel.org/linux-arm-msm/20241028060506.246606-1-quic_srichara@quicinc.com/

Varadarajan Narayanan (3):
  dt-bindings: cache: qcom,llcc: Add IPQ5424 compatible
  soc: qcom: llcc: Update configuration data for IPQ5424
  arm64: dts: qcom: ipq5424: Add LLCC/system-cache-controller

 .../devicetree/bindings/cache/qcom,llcc.yaml  | 20 ++++++-
 arch/arm64/boot/dts/qcom/ipq5424.dtsi         |  7 +++
 drivers/soc/qcom/llcc-qcom.c                  | 60 +++++++++++++++++--
 3 files changed, 81 insertions(+), 6 deletions(-)


base-commit: a39230ecf6b3057f5897bc4744a790070cfbe7a8
prerequisite-patch-id: 1090fe9cee19a52dc8595e2fecef659199828246
prerequisite-patch-id: 491c9f6c32738c4eb4398962c1ae7c625cd43238
prerequisite-patch-id: 1651c75547b539eb46eb4d02630e364f262860bf
prerequisite-patch-id: 7ce54f0af6083e897067a7e5cd9561198f3d4d41
prerequisite-patch-id: 0a04fdee4b5b76cd5b734c666f7c8f5561e3e9d8
prerequisite-patch-id: 084f6dced27c39b600711dde2f797b43393cde73
-- 
2.34.1

[PATCH v1 1/3] dt-bindings: cache: qcom,llcc: Add IPQ5424 compatible

[Varadarajan Narayanan]

Document the Last Level Cache Controller on IPQ5424. The
'broadcast' register space is present only in chipsets that have
multiple instances of LLCC IP. Since IPQ5424 has only one
instance, both the LLCC and LLCC_BROADCAST points to the same
register space.

Hence, allow only '1' reg & reg-names entry for IPQ5424.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
 .../devicetree/bindings/cache/qcom,llcc.yaml  | 20 +++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
index 68ea5f70b75f..0b03cb35aa47 100644
--- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
@@ -21,6 +21,7 @@ properties:
   compatible:
     enum:
       - qcom,qdu1000-llcc
+      - qcom,ipq5424-llcc
       - qcom,sa8775p-llcc
       - qcom,sc7180-llcc
       - qcom,sc7280-llcc
@@ -38,11 +39,11 @@ properties:
       - qcom,x1e80100-llcc
 
   reg:
-    minItems: 2
+    minItems: 1
     maxItems: 9
 
   reg-names:
-    minItems: 2
+    minItems: 1
     maxItems: 9
 
   interrupts:
@@ -62,6 +63,21 @@ required:
   - reg-names
 
 allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,ipq5424-llcc
+    then:
+      properties:
+        reg:
+          items:
+            - description: LLCC0 base register region
+        reg-names:
+          items:
+            - const: llcc0_base
+
   - if:
       properties:
         compatible:
-- 
2.34.1

Re: [PATCH v1 1/3] dt-bindings: cache: qcom,llcc: Add IPQ5424 compatible

[Rob Herring (Arm)]

On Mon, 04 Nov 2024 13:08:38 +0530, Varadarajan Narayanan wrote:
> Document the Last Level Cache Controller on IPQ5424. The
> 'broadcast' register space is present only in chipsets that have
> multiple instances of LLCC IP. Since IPQ5424 has only one
> instance, both the LLCC and LLCC_BROADCAST points to the same
> register space.
> 
> Hence, allow only '1' reg & reg-names entry for IPQ5424.
> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
>  .../devicetree/bindings/cache/qcom,llcc.yaml  | 20 +++++++++++++++++--
>  1 file changed, 18 insertions(+), 2 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH v1 2/3] soc: qcom: llcc: Update configuration data for IPQ5424

[Varadarajan Narayanan]

The 'broadcast' register space is present only in chipsets that
have multiple instances of LLCC IP. Since IPQ5424 has only one
instance, both the LLCC and LLCC_BROADCAST points to the same
register space.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
 drivers/soc/qcom/llcc-qcom.c | 60 +++++++++++++++++++++++++++++++++---
 1 file changed, 56 insertions(+), 4 deletions(-)

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index a470285f54a8..51dba8ec2183 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -152,6 +152,38 @@ enum llcc_reg_offset {
 	LLCC_COMMON_STATUS0,
 };
 
+static const struct llcc_slice_config ipq5424_data[] =  {
+	{
+		.usecase_id = LLCC_CPUSS,
+		.slice_id = 1,
+		.max_cap = 768,
+		.priority = 1,
+		.bonus_ways = 0xFFFF,
+		.retain_on_pc = 1,
+		.activate_on_init = 1,
+		.write_scid_cacheable_en = 1,
+		.stale_en = 1,
+		.stale_cap_en = 1,
+		.alloc_oneway_en = 1,
+		.ovcap_en = 1,
+		.ovcap_prio = 1,
+		.vict_prio = 1,
+	},
+	{
+		.usecase_id = LLCC_VIDSC0,
+		.slice_id = 2,
+		.max_cap = 256,
+		.priority = 2,
+		.fixed_size = 1,
+		.bonus_ways = 0xF000,
+		.retain_on_pc = 1,
+		.activate_on_init = 1,
+		.write_scid_cacheable_en = 1,
+		.stale_en = 1,
+		.stale_cap_en = 1,
+	},
+};
+
 static const struct llcc_slice_config sa8775p_data[] =  {
 	{
 		.usecase_id = LLCC_CPUSS,
@@ -2677,6 +2709,16 @@ static const struct qcom_llcc_config qdu1000_cfg[] = {
 	},
 };
 
+static const struct qcom_llcc_config ipq5424_cfg[] = {
+	{
+		.sct_data       = ipq5424_data,
+		.size           = ARRAY_SIZE(ipq5424_data),
+		.need_llcc_cfg  = true,
+		.reg_offset     = llcc_v2_1_reg_offset,
+		.edac_reg_offset = &llcc_v2_1_edac_reg_offset,
+	},
+};
+
 static const struct qcom_llcc_config sa8775p_cfg[] = {
 	{
 		.sct_data	= sa8775p_data,
@@ -2834,6 +2876,11 @@ static const struct qcom_sct_config qdu1000_cfgs = {
 	.num_config	= ARRAY_SIZE(qdu1000_cfg),
 };
 
+static const struct qcom_sct_config ipq5424_cfgs = {
+	.llcc_config	= ipq5424_cfg,
+	.num_config	= ARRAY_SIZE(ipq5424_cfg),
+};
+
 static const struct qcom_sct_config sa8775p_cfgs = {
 	.llcc_config	= sa8775p_cfg,
 	.num_config	= ARRAY_SIZE(sa8775p_cfg),
@@ -3410,10 +3457,14 @@ static int qcom_llcc_probe(struct platform_device *pdev)
 		}
 	}
 
-	drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base");
-	if (IS_ERR(drv_data->bcast_regmap)) {
-		ret = PTR_ERR(drv_data->bcast_regmap);
-		goto err;
+	if (num_banks == 1) {
+		drv_data->bcast_regmap = regmap;
+	} else {
+		drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base");
+		if (IS_ERR(drv_data->bcast_regmap)) {
+			ret = PTR_ERR(drv_data->bcast_regmap);
+			goto err;
+		}
 	}
 
 	/* Extract version of the IP */
@@ -3485,6 +3536,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
 
 static const struct of_device_id qcom_llcc_of_match[] = {
 	{ .compatible = "qcom,qdu1000-llcc", .data = &qdu1000_cfgs},
+	{ .compatible = "qcom,ipq5424-llcc", .data = &ipq5424_cfgs},
 	{ .compatible = "qcom,sa8775p-llcc", .data = &sa8775p_cfgs },
 	{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfgs },
 	{ .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfgs },
-- 
2.34.1

Re: [PATCH v1 2/3] soc: qcom: llcc: Update configuration data for IPQ5424

[Konrad Dybcio]

On 4.11.2024 8:38 AM, Varadarajan Narayanan wrote:
> The 'broadcast' register space is present only in chipsets that
> have multiple instances of LLCC IP. Since IPQ5424 has only one
> instance, both the LLCC and LLCC_BROADCAST points to the same
> register space.
> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---

[...]

> +static const struct llcc_slice_config ipq5424_data[] =  {
> +	{
> +		.usecase_id = LLCC_CPUSS,
> +		.slice_id = 1,
> +		.max_cap = 768,
> +		.priority = 1,
> +		.bonus_ways = 0xFFFF,
> +		.retain_on_pc = 1,
> +		.activate_on_init = 1,
> +		.write_scid_cacheable_en = 1,
> +		.stale_en = 1,
> +		.stale_cap_en = 1,
> +		.alloc_oneway_en = 1,
> +		.ovcap_en = 1,
> +		.ovcap_prio = 1,
> +		.vict_prio = 1,

Many of these are booleans, please use true/false values

[...]

>  
> -	drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base");
> -	if (IS_ERR(drv_data->bcast_regmap)) {
> -		ret = PTR_ERR(drv_data->bcast_regmap);
> -		goto err;
> +	if (num_banks == 1) {
> +		drv_data->bcast_regmap = regmap;
> +	} else {
> +		drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base");
> +		if (IS_ERR(drv_data->bcast_regmap)) {
> +			ret = PTR_ERR(drv_data->bcast_regmap);
> +			goto err;
> +		}
>  	}

This won't work. See for example

https://lore.kernel.org/linux-arm-msm/20241031-add_llcc_dts_node_for_qcs615-v2-1-205766a607ca@quicinc.com/

Which has both just one bank and llcc_broadcase_base.

You probably want to introduce a quirk like:

if (IS_ERR(drv_data->bcast_regmap)) {
	if (cfg->no_broadcast_register)
		bcast_regmap = drv_data->regmaps[0];
	else {
		ret = PTR_ERR(drv_data->bcast_regmap);
		goto err;
	}
}

Konrad

Re: [PATCH v1 2/3] soc: qcom: llcc: Update configuration data for IPQ5424

[Varadarajan Narayanan]

On Mon, Nov 04, 2024 at 12:04:52PM +0100, Konrad Dybcio wrote:
> On 4.11.2024 8:38 AM, Varadarajan Narayanan wrote:
> > The 'broadcast' register space is present only in chipsets that
> > have multiple instances of LLCC IP. Since IPQ5424 has only one
> > instance, both the LLCC and LLCC_BROADCAST points to the same
> > register space.
> >
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
>
> [...]
>
> > +static const struct llcc_slice_config ipq5424_data[] =  {
> > +	{
> > +		.usecase_id = LLCC_CPUSS,
> > +		.slice_id = 1,
> > +		.max_cap = 768,
> > +		.priority = 1,
> > +		.bonus_ways = 0xFFFF,
> > +		.retain_on_pc = 1,
> > +		.activate_on_init = 1,
> > +		.write_scid_cacheable_en = 1,
> > +		.stale_en = 1,
> > +		.stale_cap_en = 1,
> > +		.alloc_oneway_en = 1,
> > +		.ovcap_en = 1,
> > +		.ovcap_prio = 1,
> > +		.vict_prio = 1,
>
> Many of these are booleans, please use true/false values
>
> [...]
>
> >
> > -	drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base");
> > -	if (IS_ERR(drv_data->bcast_regmap)) {
> > -		ret = PTR_ERR(drv_data->bcast_regmap);
> > -		goto err;
> > +	if (num_banks == 1) {
> > +		drv_data->bcast_regmap = regmap;
> > +	} else {
> > +		drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base");
> > +		if (IS_ERR(drv_data->bcast_regmap)) {
> > +			ret = PTR_ERR(drv_data->bcast_regmap);
> > +			goto err;
> > +		}
> >  	}
>
> This won't work. See for example
>
> https://lore.kernel.org/linux-arm-msm/20241031-add_llcc_dts_node_for_qcs615-v2-1-205766a607ca@quicinc.com/
>
> Which has both just one bank and llcc_broadcase_base.
>
> You probably want to introduce a quirk like:
>
> if (IS_ERR(drv_data->bcast_regmap)) {
> 	if (cfg->no_broadcast_register)
> 		bcast_regmap = drv_data->regmaps[0];
> 	else {
> 		ret = PTR_ERR(drv_data->bcast_regmap);
> 		goto err;
> 	}
> }

Konrad,

Have posted v2 incorporating the above comments, please review.

Thanks
Varada

[PATCH v1 3/3] arm64: dts: qcom: ipq5424: Add LLCC/system-cache-controller

[Varadarajan Narayanan]

Add a DT node for Last level cache (aka. system cache) controller
which provides control over the last level cache present on
IPQ5424 SoCs.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq5424.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index 76af0d87e9a8..497df93acf47 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -137,6 +137,13 @@ soc@0 {
 		#size-cells = <2>;
 		ranges = <0 0 0 0 0x10 0>;
 
+		system-cache-controller@800000 {
+			compatible = "qcom,ipq5424-llcc";
+			reg = <0 0x00800000 0 0x200000>;
+			reg-names = "llcc0_base";
+			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		tlmm: pinctrl@1000000 {
 			compatible = "qcom,ipq5424-tlmm";
 			reg = <0 0x01000000 0 0x300000>;
-- 
2.34.1

Re: [PATCH v1 3/3] arm64: dts: qcom: ipq5424: Add LLCC/system-cache-controller

[Konrad Dybcio]

On 4.11.2024 8:38 AM, Varadarajan Narayanan wrote:
> Add a DT node for Last level cache (aka. system cache) controller
> which provides control over the last level cache present on
> IPQ5424 SoCs.
> 
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad