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From: Frank Li <Frank.li@nxp.com>
To: Claudiu Beznea <claudiu.beznea@kernel.org>
Cc: wsa+renesas@sang-engineering.com,
	tommaso.merciai.xr@bp.renesas.com, alexandre.belloni@bootlin.com,
	p.zabel@pengutronix.de, claudiu.beznea@tuxon.dev,
	linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-renesas-soc@vger.kernel.org,
	Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>,
	stable@vger.kernel.org
Subject: Re: [PATCH 03/17] i3c: renesas: Restore STDBR and EXTBR registers on resume
Date: Fri, 22 May 2026 15:10:15 -0400	[thread overview]
Message-ID: <ahCqF-OHFbV9b5ul@lizhi-Precision-Tower-5810> (raw)
In-Reply-To: <20260522101815.1722909-4-claudiu.beznea@kernel.org>

On Fri, May 22, 2026 at 01:18:01PM +0300, Claudiu Beznea wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> The Renesas RZ/G3S supports a power saving state where power to the most
> SoC componentes (including I3C) is lost.
>
> The STDBR and EXTBR are configured in initialization phase though the
> struct i3c_master_controller_ops::bus_init. Set them on resume function
> as well to keep the same state of the controller after a suspend with
> power loss and a similar initialization sequence as in bus_init.
>
> Fixes: e7218986319b ("i3c: renesas: Add suspend/resume support")
> Cc: stable@vger.kernel.org
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>  drivers/i3c/master/renesas-i3c.c | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/i3c/master/renesas-i3c.c b/drivers/i3c/master/renesas-i3c.c
> index 1917549cf6d5..6c23f956ad2a 100644
> --- a/drivers/i3c/master/renesas-i3c.c
> +++ b/drivers/i3c/master/renesas-i3c.c
> @@ -260,6 +260,7 @@ struct renesas_i3c {
>  	u32 dyn_addr;
>  	u32 i2c_STDBR;
>  	u32 i3c_STDBR;
> +	u32 extbr;

can you keep consisent with above 2 register, use upcase EXTBR,

Frank
>  	unsigned long rate;
>  	u8 addrs[RENESAS_I3C_MAX_DEVS];
>  	struct renesas_i3c_xferqueue xferqueue;
> @@ -607,10 +608,9 @@ static int renesas_i3c_bus_init(struct i3c_master_controller *m)
>  	renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR);
>
>  	/* Extended Bit Rate setting */
> -	renesas_writel(i3c->regs, EXTBR, EXTBR_EBRLO(od_low_ticks) |
> -					   EXTBR_EBRHO(od_high_ticks) |
> -					   EXTBR_EBRLP(pp_low_ticks) |
> -					   EXTBR_EBRHP(pp_high_ticks));
> +	i3c->extbr = EXTBR_EBRLO(od_low_ticks) | EXTBR_EBRHO(od_high_ticks) |
> +		     EXTBR_EBRLP(pp_low_ticks) | EXTBR_EBRHP(pp_high_ticks);
> +	renesas_writel(i3c->regs, EXTBR, i3c->extbr);
>
>  	renesas_writel(i3c->regs, REFCKCTL, REFCKCTL_IREFCKS(cks));
>  	i3c->refclk_div = cks;
> @@ -1447,6 +1447,8 @@ static int renesas_i3c_resume_noirq(struct device *dev)
>  		goto err_tresetn;
>
>  	/* Re-store I3C registers value. */
> +	renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR);
> +	renesas_writel(i3c->regs, EXTBR, i3c->extbr);
>  	renesas_writel(i3c->regs, REFCKCTL,
>  		       REFCKCTL_IREFCKS(i3c->refclk_div));
>  	renesas_writel(i3c->regs, MSDVAD, MSDVAD_MDYADV |
> --
> 2.43.0
>

  reply	other threads:[~2026-05-22 19:10 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-22 10:17 [PATCH 00/17] i3c: renesas: Suspend to RAM with power loss and runtime PM Claudiu Beznea
2026-05-22 10:17 ` [PATCH 01/17] i3c: renesas: Check that the transfer is valid before accessing it Claudiu Beznea
2026-05-22 19:02   ` Frank Li
2026-05-22 10:18 ` [PATCH 02/17] i3c: renesas: Use the divider 128 Claudiu Beznea
2026-05-22 19:06   ` Frank Li
2026-05-23  8:14     ` Claudiu Beznea
2026-05-22 10:18 ` [PATCH 03/17] i3c: renesas: Restore STDBR and EXTBR registers on resume Claudiu Beznea
2026-05-22 19:10   ` Frank Li [this message]
2026-05-28  8:29     ` Claudiu Beznea
2026-05-28 19:13       ` Frank Li
2026-05-22 10:18 ` [PATCH 04/17] i3c: renesas: Follow the reset deassert order used in probe Claudiu Beznea
2026-05-22 19:11   ` Frank Li
2026-05-22 10:18 ` [PATCH 05/17] i3c: renesas: Fix re-attach Claudiu Beznea
2026-05-22 19:13   ` Frank Li
2026-05-22 10:18 ` [PATCH 06/17] i3c: renesas: Reset the controller on resume Claudiu Beznea
2026-05-22 19:15   ` Frank Li
2026-05-23 10:24     ` Claudiu Beznea
2026-05-22 10:18 ` [PATCH 07/17] i3c: renesas: Perform Dynamic Address Assignment " Claudiu Beznea
2026-05-22 19:16   ` Frank Li
2026-05-23 10:26     ` Claudiu Beznea
2026-05-22 10:18 ` [PATCH 08/17] i3c: renesas: Clean DATBAS register on detach Claudiu Beznea
2026-05-22 19:17   ` Frank Li
2026-05-22 10:18 ` [PATCH 09/17] i3c: renesas: Use reset_control_bulk_{assert, deassert}() Claudiu Beznea
2026-05-22 19:19   ` Frank Li
2026-05-23 10:26     ` Claudiu Beznea
2026-05-22 10:18 ` [PATCH 10/17] i3c: renesas: Return immediately if there is nothing to transfer Claudiu Beznea
2026-05-22 19:20   ` Frank Li
2026-05-22 10:18 ` [PATCH 11/17] i3c: renesas: Follow a unified pattern for transfer and command initialization Claudiu Beznea
2026-05-22 19:21   ` Frank Li
2026-05-22 10:18 ` [PATCH 12/17] i3c: renesas: Drop the explicit memset() call Claudiu Beznea
2026-05-22 19:43   ` Frank Li
2026-05-22 10:18 ` [PATCH 13/17] i3c: renesas: Update HW registers after SW computations are done Claudiu Beznea
2026-05-22 19:48   ` Frank Li
2026-05-22 10:18 ` [PATCH 14/17] i3c: renesas: Organize structures to avoid unnecessary padding Claudiu Beznea
2026-05-22 19:50   ` Frank Li
2026-05-22 10:18 ` [PATCH 15/17] i3c: renesas: Use the "dev_name:irq_name" format for the interrupt name Claudiu Beznea
2026-05-22 19:51   ` Frank Li
2026-05-22 10:18 ` [PATCH 16/17] i3c: renesas: Drop unnecessary tab Claudiu Beznea
2026-05-22 19:52   ` Frank Li
2026-05-22 10:18 ` [PATCH 17/17] i3c: renesas: Add runtime PM support Claudiu Beznea
2026-05-22 20:01   ` Frank Li
2026-05-23 10:23     ` Claudiu Beznea
2026-06-02 11:49       ` Claudiu Beznea

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