[Question] x86,APIC: In apicdef.h dfr,svr,...... shouldn't be const?

[Question] x86,APIC: In apicdef.h dfr,svr,...... shouldn't be const?

[Rakib Mullick]

Hello guys, Intel System programmers guide says - dfr, svr, esr - this
registers should be readonly. So shouldn't they use const? Or is it
anything else?

And apicdef.h also contains a style problem, checkpatch warns about
following style:

              u32	spurious_vector	:  8

Check patch wants as:

                         u32	spurious_vector:8

Shouldn't this issues be fixed?

Thanks,

Re: [Question] x86,APIC: In apicdef.h dfr,svr,...... shouldn't be const?

[Cyrill Gorcunov]

On 9/1/09, Rakib Mullick <rakib.mullick@gmail.com> wrote:
> Hello guys, Intel System programmers guide says - dfr, svr, esr - this
> registers should be readonly. So shouldn't they use const? Or is it
> anything else?

Hi Rakib, i dont have sources under my hands at moment, but iirc there
were situations we nees to poke esr register.

>
> And apicdef.h also contains a style problem, checkpatch warns about
> following style:
>
>               u32	spurious_vector	:  8
>
> Check patch wants as:
>
>                          u32	spurious_vector:8
>
> Shouldn't this issues be fixed?
>
> Thanks,
> --

i dont see reason why not ;)
though i wonder why we need this structure at all. We may have
extended amd entries.
Yinghai cced.

Re: [Question] x86,APIC: In apicdef.h dfr,svr,...... shouldn't be const?

[Cyrill Gorcunov]

[Cyrill Gorcunov - Tue, Sep 01, 2009 at 12:43:06PM +0400]
| On 9/1/09, Rakib Mullick <rakib.mullick@gmail.com> wrote:
| > Hello guys, Intel System programmers guide says - dfr, svr, esr - this
| > registers should be readonly. So shouldn't they use const? Or is it
| > anything else?
| 
| Hi Rakib, i dont have sources under my hands at moment, but iirc there
| were situations we nees to poke esr register.
| 
| >
| > And apicdef.h also contains a style problem, checkpatch warns about
| > following style:
| >
| >               u32	spurious_vector	:  8
| >
| > Check patch wants as:
| >
| >                          u32	spurious_vector:8
| >
| > Shouldn't this issues be fixed?
| >
| > Thanks,
| > --
| 
| i dont see reason why not ;)
| though i wonder why we need this structure at all. We may have
| extended amd entries.
| Yinghai cced.
| 

Ingo, Yinghai, Suresh,

is there any particular reason we keep apicdef.h:struct local_apic at all?

Was there some plan on this structure usage in future? If take into
account amd extended registers this structure doesn't cover all
possible cases. And at moment we do poke apic registers via APIC_
macros mostly and it seems that is the more convenient
and flexible approach. The only thing I may imagine where we
could (possibly) use it in future is suspend/resume cases.

But perhaps I miss something?

	-- Cyrill

Re: [Question] x86,APIC: In apicdef.h dfr,svr,...... shouldn't be const?

[Maciej W. Rozycki]

On Tue, 1 Sep 2009, Rakib Mullick wrote:

> Hello guys, Intel System programmers guide says - dfr, svr, esr - this
> registers should be readonly. So shouldn't they use const? Or is it
> anything else?

 All the three have meaningful semantics on writes at least on some 
versions of the APIC (they either have writable fields or trigger side 
effects on writes).  It looks like your documentation is wrong (not 
unheard of with Intel).

  Maciej

Re: [Question] x86,APIC: In apicdef.h dfr,svr,...... shouldn't be const?

[Rakib Mullick]

On 9/2/09, Maciej W. Rozycki <macro@linux-mips.org> wrote:
>
>  All the three have meaningful semantics on writes at least on some
>  versions of the APIC (they either have writable fields or trigger side
>  effects on writes).  It looks like your documentation is wrong (not
>  unheard of with Intel).

Thanks, Maciej. If my documentation is wrong, then which documentation
should I follow? Isn't there any well defined document?
>
>
>   Maciej
>

Re: [Question] x86,APIC: In apicdef.h dfr,svr,...... shouldn't be const?

[Maciej W. Rozycki]

On Fri, 4 Sep 2009, Rakib Mullick wrote:

> >  All the three have meaningful semantics on writes at least on some
> >  versions of the APIC (they either have writable fields or trigger side
> >  effects on writes).  It looks like your documentation is wrong (not
> >  unheard of with Intel).
> 
> Thanks, Maciej. If my documentation is wrong, then which documentation
> should I follow? Isn't there any well defined document?

 You may have to track down an older revision of the document or that for 
an older CPU.  These registers may have changed as the architecture 
evolved and while Linux supports all the APIC versions, Intel may have 
omitted details for earlier implementations either deliberately or 
accidentally.

  Maciej